JPH02292850A - Lead frame - Google Patents
Lead frameInfo
- Publication number
- JPH02292850A JPH02292850A JP1113909A JP11390989A JPH02292850A JP H02292850 A JPH02292850 A JP H02292850A JP 1113909 A JP1113909 A JP 1113909A JP 11390989 A JP11390989 A JP 11390989A JP H02292850 A JPH02292850 A JP H02292850A
- Authority
- JP
- Japan
- Prior art keywords
- resin
- lead frame
- pad
- die pad
- holes
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000011347 resin Substances 0.000 abstract description 39
- 229920005989 resin Polymers 0.000 abstract description 39
- 239000004065 semiconductor Substances 0.000 abstract description 21
- 238000000034 method Methods 0.000 abstract description 9
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 abstract description 6
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 abstract description 5
- 238000007789 sealing Methods 0.000 abstract description 4
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 3
- 229910000640 Fe alloy Inorganic materials 0.000 abstract description 3
- 229910000990 Ni alloy Inorganic materials 0.000 abstract description 3
- 230000002093 peripheral effect Effects 0.000 abstract 4
- 229910052709 silver Inorganic materials 0.000 description 14
- 239000004332 silver Substances 0.000 description 14
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 13
- 238000007747 plating Methods 0.000 description 7
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 6
- 229910052737 gold Inorganic materials 0.000 description 4
- 239000010931 gold Substances 0.000 description 4
- 238000010438 heat treatment Methods 0.000 description 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229910052710 silicon Inorganic materials 0.000 description 3
- 239000010703 silicon Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000005496 eutectics Effects 0.000 description 2
- 238000002347 injection Methods 0.000 description 2
- 239000007924 injection Substances 0.000 description 2
- 238000000465 moulding Methods 0.000 description 2
- 230000035939 shock Effects 0.000 description 2
- 229910000838 Al alloy Inorganic materials 0.000 description 1
- OFLYIWITHZJFLS-UHFFFAOYSA-N [Si].[Au] Chemical compound [Si].[Au] OFLYIWITHZJFLS-UHFFFAOYSA-N 0.000 description 1
- 238000010521 absorption reaction Methods 0.000 description 1
- 238000005275 alloying Methods 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 238000005242 forging Methods 0.000 description 1
- 230000009477 glass transition Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 150000003378 silver Chemical class 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/484—Connecting portions
- H01L2224/48463—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond
- H01L2224/48465—Connecting portions the connecting portion on the bonding area of the semiconductor or solid-state body being a ball bond the other connecting portion not on the bonding area being a wedge bond, i.e. ball-to-wedge, regular stitch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73265—Layer and wire connectors
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/181—Encapsulation
Landscapes
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
産業上の利用分野
本発明は、樹脂封止型パッケージの中に半導体チップと
ともに封じ込むリードフレームの構造に関するものであ
る．
従来の技術
樹脂封止型半導体パッケージは、シリコンからなる半導
体チップを金属製リードフレームのダイバッドに固着し
て構成され、リードフレームの材質は、鉄、鉄とニッケ
ルの合金、銅系合金などが使用される．
半導体チップのグイパッドへの固着法としては、グイパ
ッド表面に１〜３μｍ程度の金メッキをほどこし、その
ダイパッドを有するリードフレームを３８０〜４００”
Ｃの還元雰囲気に置き、金メッキ面上に半導体チップの
裏面をこすり付けて、金とシリコンの合金化により固着
する金シリコン共晶法と、グイパッド表面に１〜５μｍ
程度の銀メッキをほどこし、そのダイバッド上に多点状
に銀ぺ−ストを滴下してこの銀ペースト上に半導体チッ
プ裏面を貼り付け、これを１５０〜２００℃の温度で１
〜２時間加熱することにより固着する銀ペースト法との
どちらかを用いる．
次に、半導体チップの表面上に電気的に機能させるため
に設けられた入出力端子のボンディングパッドと、リー
ドフレームのインナーリード先端付近のダイバッドと同
時にほどこされたメッキ膜部分とを、２０〜４０μｍφ
の金や銅の細線で熱圧着（超音波併用もある）ワイヤー
ボンディング法により接続する．この接続作業時の温度
は、２００〜３５０℃に設定ずる．
以上の工程を終了したリードフレームを１６０〜１９０
℃に加熱された樹脂成形用金型に装着し、金型の樹脂注
入口（ゲート部）より加熱溶融した樹脂を注入する．金
型はゲート部と所望のパッケージ外形にするためのキャ
ビティ一部とキャビティー内部の空気を抜くためのベン
ト部とで梢成されている．また、樹脂はキャビティー内
にセットされた半導体チップ、ダイパッド，インナーリ
ードおよび金属細線を包み込むように注入される．この
樹脂の注入が完了した後４０〜１２０秒間維持し、樹脂
を一次硬化する．それから、さらに炉内でその樹脂のガ
ラス転位点以上の温度で５〜１０時間加熱することで最
終硬化を行い、半導体チップの樹脂中への封止が完了す
る．
この状態で、樹脂部分から外側になるリードフレームの
アウターリードに５〜１０μｍの半田メッキをほどこし
、インナーリードのフオーミング加工を行い、機能確認
を行った後、樹脂上面部に、製品を判別するためのマー
キングをする．発明が解決しようとする課題
従来、樹脂封止型バッゲージは、樹脂中にインナーリー
ド、ダイパッド，半導体チップ，金属細線を封じ込む．
一方、近年の半導体チップは、高集積化技術が進み、１
チップ多機能内蔵型の種類が増えている．そのために半
導体チップの寸法も、著しく大型化，大面積化してきて
いる．このような大面積半導体チップを上記の樹脂封止
型バッゲージに搭載する際、幾つかの問題を生ずるが、
とりわけ、樹脂中に封じ込んだ各構成材質の熱膨張係数
の違いから生じる各材質間の境界での剥離は、完成品の
品質（特に、謝湿性や吸湿後の耐熱衝撃性）に重大な影
響を与えるという問題があった。DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to the structure of a lead frame that is sealed together with a semiconductor chip in a resin-sealed package. Conventional technology A resin-sealed semiconductor package consists of a semiconductor chip made of silicon fixed to a die pad of a metal lead frame, and the lead frame is made of iron, an alloy of iron and nickel, a copper alloy, etc. It will be done. The method for fixing a semiconductor chip to a die pad is to apply gold plating of approximately 1 to 3 μm on the surface of the die pad, and then attach a lead frame with a die pad of 380 to 400 inches.
The gold-silicon eutectic method involves rubbing the back side of a semiconductor chip on the gold-plated surface in a reducing atmosphere of C and solidifying it by alloying gold and silicon.
Silver paste is applied to the die pad at multiple points, and the back side of the semiconductor chip is pasted on the silver paste.
Use either the silver paste method, which fixes by heating for ~2 hours. Next, bonding pads for input/output terminals provided on the surface of the semiconductor chip for electrical function, and a plating film portion near the tip of the inner lead of the lead frame, which was applied at the same time as the die pad, were bonded to a diameter of 20 to 40 μm.
Connections are made using thin gold or copper wires using wire bonding (sometimes using ultrasonic waves). The temperature during this connection work should be set at 200-350°C. The lead frame after the above process is 160~190
It is attached to a resin molding mold heated to ℃, and heated and molten resin is injected from the resin injection port (gate part) of the mold. The mold consists of a gate part, a part of the cavity to form the desired package shape, and a vent part to vent the air inside the cavity. Furthermore, the resin is injected so as to enclose the semiconductor chip, die pad, inner leads, and thin metal wires set in the cavity. After the resin injection is completed, the resin is maintained for 40 to 120 seconds to primarily cure the resin. Then, final curing is performed by heating the resin in a furnace at a temperature above the glass transition point of the resin for 5 to 10 hours, completing the sealing of the semiconductor chip in the resin. In this state, solder plating of 5 to 10 μm is applied to the outer leads of the lead frame that are outward from the resin part, the inner leads are formed, and the function is confirmed. Make a marking. Problems to be Solved by the Invention Conventionally, resin-sealed bags encapsulate inner leads, die pads, semiconductor chips, and thin metal wires in resin.
On the other hand, in recent years, semiconductor chips have become more and more highly integrated.
The number of types with built-in multi-function chips is increasing. As a result, the dimensions of semiconductor chips have become significantly larger and larger in area. When mounting such a large-area semiconductor chip on the above-mentioned resin-sealed baggage, several problems arise.
In particular, peeling at the boundaries between the constituent materials encapsulated in the resin due to differences in their thermal expansion coefficients has a significant impact on the quality of the finished product (especially moisture resistance and thermal shock resistance after moisture absorption). There was a problem of giving
本発明は上記問題を解決するもので、封止樹脂に対して
剥離することのないリードフレームを提供することを目
的とするものである．
課題を解決するための手段
上記問題を解決するために本発明のリードフレームは、
ダイパッドの周辺部に複数個からなる貫通孔を設けたも
のである．
作用
上記構成により、このリードフレームのダイバッドを樹
脂中に封じ込んだ場合、貫通孔の中にも樹脂が充填され
る．したがって、貫通孔の中に入込んだ樹脂がダイバヅ
ドに係合し、これにより樹脂封止型バッゲージにおける
周囲温度の急激な上昇にともなう樹脂とグイパッド界面
での剥離は防止される．さらに、樹脂とダイパッド界面
での剥離が生じなくなってこの界面に水分が侵入して溜
まることが少なくなるため、水の蒸気圧による樹脂部の
破壊も防止できる．
実施例
以下に本発明の一実施例を、第１図．第２図を参照して
説明する．
第１図は本発明の一実施例を示すリードフレームを用い
た樹脂封止型バッゲージの平面図、第２図は第１図のＡ
−Ａ断面図を示す．第１図に示すように、鉄とニッケル
の合金や、銅系合金からなるリードフレーム１のダイバ
ッド３の周辺部には、搭載する半導体チップ４の外周部
より外側位置に複数個の貫通孔５が設けられている。こ
の貫通孔５は断面形状が、第３図（ａ）に示すように、
直線状とされている．
次にこのリードフレームを用いて樹脂封止型バッゲージ
を製造する場合について説明する。まず、リードフレー
ム１のダイバッド３の上面とインナーリード６の先端上
面に銀メッキ層７を１〜５μｍの厚さに形成する．次に
、この銀メッキ層７の上に銀ペースト８を多点滴下した
後、銀ペースト８の上に半導体チップ４を載せて、こす
りつけながら銀ペースト８を広げて均一厚さの銀ペース
ト８の層を形成する．銀ペースト８の厚さが２〜１５μ
ｍで均一になった時点で、ダイバッド３上の銀メッキ層
７への半導体チップ４の接着を終え、これを１５０〜２
００℃の温度で１〜２時間加熱して銀ペースト８の硬化
によるグイバッド３への半導体チップ４の固着を完成す
る。そして、半導体チップ４上のボンディングバッド９
とインナーリード６上の銀メッキ層７の間を、直径２５
μｍの金線１０で、熱圧着《超音波併用》によるワイヤ
ーボンディングを行うことにより接続する．この後、リ
ードフレーム１を１６０〜１９０℃に加熱した樹脂成形
用金型に装着し、樹脂１１を注入して所望のバッゲージ
外形に成形する．この樹脂１１の注入の際に、ダイパッ
ド３周辺の貫通孔５にも樹脂が充填される．この樹脂封
止を行った後、アウターリード１２のメッキ処理、さら
にアウターリード１２のフォーγングを行って樹脂封止
型パッケージ２は完成する。The present invention solves the above problem, and aims to provide a lead frame that does not peel off from the sealing resin. Means for Solving the Problems In order to solve the above problems, the lead frame of the present invention has the following features:
Multiple through holes are provided around the die pad. Effect: With the above configuration, when the die pad of this lead frame is encapsulated in resin, the through hole is also filled with resin. Therefore, the resin that has entered the through hole engages with the diverging pad, thereby preventing the resin from peeling off at the interface between the resin and the Guipad due to a sudden rise in ambient temperature in a resin-sealed baggage. Furthermore, since peeling does not occur at the interface between the resin and the die pad, moisture is less likely to enter and accumulate at this interface, and damage to the resin part due to the vapor pressure of water can be prevented. EXAMPLE An example of the present invention will be described below with reference to FIG. This will be explained with reference to Figure 2. Fig. 1 is a plan view of a resin-sealed baggage using a lead frame showing an embodiment of the present invention, and Fig. 2 is an A of Fig. 1.
-A cross-sectional view is shown. As shown in FIG. 1, in the periphery of the die pad 3 of the lead frame 1 made of an alloy of iron and nickel or a copper alloy, a plurality of through holes 5 are provided at positions outside the outer periphery of the semiconductor chip 4 to be mounted. is provided. This through hole 5 has a cross-sectional shape as shown in FIG. 3(a).
It is considered to be a straight line. Next, a case will be described in which a resin-sealed baggage is manufactured using this lead frame. First, a silver plating layer 7 with a thickness of 1 to 5 μm is formed on the upper surface of the die pad 3 of the lead frame 1 and the upper surface of the tip of the inner lead 6. Next, after dropping multiple drops of silver paste 8 onto this silver plating layer 7, the semiconductor chip 4 is placed on top of the silver paste 8, and the silver paste 8 is spread while being rubbed to form a uniform thickness of the silver paste 8. Form a layer. The thickness of silver paste 8 is 2 to 15μ
When it becomes uniform at 150-2 m, the adhesion of the semiconductor chip 4 to the silver plating layer 7 on the die pad 3 is finished, and this is done at 150-2 m.
The silver paste 8 is cured by heating at a temperature of 00° C. for 1 to 2 hours to complete the adhesion of the semiconductor chip 4 to the Guibad 3. Then, the bonding pad 9 on the semiconductor chip 4
and the silver plating layer 7 on the inner lead 6 with a diameter of 25 mm.
Connection is made by wire bonding using thermocompression bonding (combined with ultrasonic waves) using a gold wire 10 of 10 μm. Thereafter, the lead frame 1 is placed in a resin molding die heated to 160 to 190°C, and resin 11 is injected to form the desired baggage shape. When this resin 11 is injected, the through holes 5 around the die pad 3 are also filled with the resin. After this resin sealing is performed, the outer leads 12 are plated, and the outer leads 12 are subjected to forging, thereby completing the resin-sealed package 2.
上記構成において、ダイバッド３周辺の貫通孔５には樹
脂１１が入込み、ダイバッド３と係合しているため、周
囲温度が上昇しても樹脂１１はダイバッド３から剥離せ
ず、またグイパッド３と樹脂１１との界面に水分が侵入
して溜まることは少ないなめ、水の蒸気圧による樹脂部
分の破壊も生じない．なお、貫通孔５の形状は直線状に
限るものではなく、第３図ｉｂ）に示すように、階段状
に形成してもよく、この場合は貫通孔５の箇所の樹脂１
１に作用ずる剪断応力が分散されて、剪断に対する抗力
が改善される．
また、半導体チップ４を固着ずる方法は銀ペースト法に
限るものではなく、金とシリコンとの共晶法によるもの
でもよく、また、ボンディングパッド９とインナーリー
ド６上の銀メッキ層７との接続は、金線１０以外の銅線
などでもよい。In the above configuration, since the resin 11 enters the through hole 5 around the die pad 3 and engages with the die pad 3, the resin 11 does not separate from the die pad 3 even if the ambient temperature rises, and the resin 11 does not separate from the die pad 3. Since there is little chance of moisture entering and accumulating at the interface with 11, the resin part will not be destroyed by the vapor pressure of the water. Note that the shape of the through hole 5 is not limited to a linear shape, but may be formed in a stepped shape as shown in FIG.
The shear stress acting on 1 is dispersed, and the resistance to shear is improved. Furthermore, the method of fixing the semiconductor chip 4 is not limited to the silver paste method, but may also be a method using a eutectic method of gold and silicon. may be a copper wire other than the gold wire 10.
発明の効果
以上のように本発明によれば、リードフレームのダイバ
ッド周囲に貫通孔を設けた′！ＩＡ造を用いることで、
１．外部からの熱街撃による樹脂とダイパッドとの剥離
が防げて、剥離部に水分が溜まることは生じないため、
アルミニウム合金のボンディングバッドの耐腐食性が著
しく改首される。Effects of the Invention As described above, according to the present invention, a through hole is provided around the die pad of the lead frame. By using IA construction, 1. This prevents the resin from peeling off from the die pad due to external thermal shock, and prevents moisture from accumulating in the peeled area.
The corrosion resistance of aluminum alloy bonding pads has been significantly improved.
２．樹脂とダイバッドとの界面に水分を溜めないので、
急激な加熱によるダイバッド裏面での水の蒸気圧が極め
て低くなり、パッケージの樹脂部の破壊（クラック）が
防げる。2. Since moisture does not accumulate at the interface between the resin and the die pad,
The vapor pressure of water on the backside of the die pad due to rapid heating becomes extremely low, preventing damage (cracks) to the resin part of the package.
などの信顆性の向上が実現できる．It is possible to improve reliability such as
第１図は本発明の一実施例におけるリードフレーム、を
用いた樹脂封止型パッケージの平面図、第２図は第１図
のＡ−Ａ断面図、第３図（ａ）および（ｂ）は同リード
フレームの貫通孔の形状の違いを示す斜視図である。
１・・・リードフレーム、２・・・樹脂封止型バ・７ケ
ージ、３・・・ダイパッド、４・・・半導体チップ、５
・・・貫通孔、１１・・・樹脂。
代理人 森 本 義 弘
第ｌ図
ｌ２
ｔ−．Ｉ）−Ｙフレーム
３６．．夕゛４ハ０ツＹ゛
４・・・牛１４＋ツフ′
Ｓ・・・１通孔
／ｌ・・・−１′八旨FIG. 1 is a plan view of a resin-sealed package using a lead frame according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA in FIG. 1, and FIGS. 3 (a) and (b). FIG. 3 is a perspective view showing a difference in the shape of the through hole of the same lead frame. DESCRIPTION OF SYMBOLS 1... Lead frame, 2... Resin-sealed bar 7 cage, 3... Die pad, 4... Semiconductor chip, 5
...Through hole, 11...Resin. Agent Yoshihiro Morimoto Figure l2 t-. I)-Y frame 36. ．． Y゛4ha0tsuY゛4...Cow14+Tsuf' S...1 hole/l...-1'8 points
Claims (1)
フレーム。1. Lead frame with multiple through holes around the die pad.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1113909A JPH02292850A (en) | 1989-05-06 | 1989-05-06 | Lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1113909A JPH02292850A (en) | 1989-05-06 | 1989-05-06 | Lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH02292850A true JPH02292850A (en) | 1990-12-04 |
Family
ID=14624222
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1113909A Pending JPH02292850A (en) | 1989-05-06 | 1989-05-06 | Lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH02292850A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397915A (en) * | 1991-02-12 | 1995-03-14 | Matsushita Electronics Corporation | Semiconductor element mounting die pad including a plurality of extending portions |
| JP2013219373A (en) * | 2000-12-28 | 2013-10-24 | Renesas Electronics Corp | Semiconductor device |
| US9496204B2 (en) | 2000-12-28 | 2016-11-15 | Renesas Electronics Corporation | Semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5676542A (en) * | 1979-11-28 | 1981-06-24 | Hitachi Ltd | Resin-sealed semiconductor device |
-
1989
- 1989-05-06 JP JP1113909A patent/JPH02292850A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5676542A (en) * | 1979-11-28 | 1981-06-24 | Hitachi Ltd | Resin-sealed semiconductor device |
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5397915A (en) * | 1991-02-12 | 1995-03-14 | Matsushita Electronics Corporation | Semiconductor element mounting die pad including a plurality of extending portions |
| JP2013219373A (en) * | 2000-12-28 | 2013-10-24 | Renesas Electronics Corp | Semiconductor device |
| US9496204B2 (en) | 2000-12-28 | 2016-11-15 | Renesas Electronics Corporation | Semiconductor device |
| US10115658B2 (en) | 2000-12-28 | 2018-10-30 | Renesas Electronics Corporation | Semiconductor device |
| US10490486B2 (en) | 2000-12-28 | 2019-11-26 | Renesas Electronics Corporation | Semiconductor device |
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