JP2000252389A - Integrated circuit having protrusion simulating solder ball and its manufacture - Google Patents

Abstract

PROBLEM TO BE SOLVED: To greatly reduce a manufacturing cost by forming a protrusion simulating a solder ball, and incorporating a solderable surface in the protrusion. SOLUTION: A cavity 303 is provided on a first surface 307a of a sheet-like substrate 307 of an IC chip 306. Accordingly, the substrate 307 is preferably of a metal foil. A second surface 307b of the substrate 307 is formed to be soldable. The chip 306 is disposed on a lower half 302 of a mold, and positions 309 where wires are welded to the substrate 307 are aligned with positions of recesses 305 of the lower half of the mold. This alignment is indicated by reference numeral 310. Thereafter, when the mold is closed, a sealing material 311 is press injected in the cavity 303 until the cavity 303 is fully filled with the material 311. A device 320 indicates a completed device. A small ridge 312 is electrically isolated by an opening 313.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

FIELD OF THE INVENTION The present invention relates generally to the field of semiconductor devices and processes, and more particularly, to molded low cost ball grid arrays and chip scale packages, and solder balls. The method relates to a method of forming a ridge that simulates the following.

[0002]

BACKGROUND OF THE INVENTION The trend in semiconductor technology (Moore's Law) to double the functional complexity of its products every 18 months still exists today after dominating the industry for the last 30 years. It is valid, but has some implicit implications. First, the cost per functional unit should decrease with each generation of complexity, so that the cost of a doubled product increases only slightly. Second,
Higher product complexity should be achieved mainly by reducing the feature dimensions of the chip components, while keeping the package dimensions constant. Preferably, the package should also be shrunk. Third, along with the increased functional complexity, the reliability of the product should be increased as well. Fourth, while not less important, it offers the most flexible product for the application and the best economy in the market in terms of achieving complexity goals. Rewards for profits are promised. Although plastic ball grid arrays (BGAs) and chip scale packages (CSPs) have become very popular in recent years, they have been completely obscured by Moore's Law due to a number of drawbacks. There are restrictions to follow. Due to the high content of plastic materials and the constant number of manufacturing process steps, BGA and CP
It has been found that it is difficult to reduce the cost of S.
The reliability of plastic BGAs and CSPs is compromised by their susceptibility to thermo-mechanical stresses and moisture absorption. It is difficult to adjust the package design to customer requirements. As a result, the package design is not as versatile as to adapt the general application trends to smaller package geometries and thinner profiles. Known techniques include BGA and CSP for devices with a large number of leads (or number of solder balls).
The focus is on developing package designs and processes, ignoring the specific demands of BGA and CSP when the number of leads (or solder balls) is smaller. Thus, there is an opportunity in a huge application market, especially when there is a need for a low number of solder balls, but it is unnoticed. At present, low pin count plastic packages use stamped or etched lead frames. Such a lead frame is the main material cost in such a package. Plastic BGAs and CSPs use patterned polyimide films as substrates for mounting semiconductor chips. Such a film is the main material cost of such a package. Further, the scheme used in current technology for attaching solder balls (or bumps) to a package is unsatisfactory due to problems associated with ball adhesion, ball detachment, or ball duplication. .
The manufacturing processes used and the required inspections are hindering cost savings.

[0003]

SUMMARY OF THE INVENTION In accordance with the present invention, there is provided a molding device for sealing an integrated circuit (IC) device to form a ridge of a size and shape suitable for simulating a solder ball. A process is used, wherein the ridges are configured such that they have a conductive, solderable surface that is electrically connected to the input / output terminals of the IC chip. The present invention provides a high density IC,
Especially for those with low or medium number of input / output or bond pads, furthermore, need devices with conductive or metal substrates to which they are usually connected by wire bonding, and small package outline and low profile And about the device. These ICs
Include many products such as processors, digital and analog devices, mixed signal and standard linear and logic products, telephones, RF and communications devices, intelligent power devices, and both large and small area chip categories. Found in the semiconductor device family. The present invention ensures built-in quality and reliability in applications such as cellular communications, pagers, hard disk drives, laptop computers, and medical devices. The present invention provides for some material changes and some simplifications of the basic process steps commonly performed in semiconductor assembly and packaging technology, so that significant manufacturing cost savings are achieved. The chip is mounted on a substrate provided as a thin foil with a thickness in the range of about 10 to 75 μm. In this thickness range, the foil responds to the pressure during the conventional transfer molding process and is applied to the steel wall of the mold cavity and smoothly conforms to the contour of the wall surface. In this way, mounds of conductive material having solderable surfaces are created, which simulate solder "balls" and can be used for solder joints. The amount by which a foil material can stretch to change from its original flat shape to a curved shape is determined by the present invention. The bump simulating the ball has a thickness of about 30 to 40
Approximately 150 to 230 using μm annealed copper foil
It can be made to a height of μm. One aspect of the present invention is that it can be applied to a variety of different ball grid arrays and chip scale packages, especially those having a "ball" number of about 4 to 80. The most frequently used range is about 8 to 48 "balls".

[0004] Another aspect of the present invention is to provide a technique for producing low "lead" inductance in products for high frequency applications. Another aspect of the present invention is to eliminate the difficulty of placing pre-manufactured solder balls in a device package by creating bumps that simulate balls, also serving as packages. Another aspect of the present invention is to improve the reliability of the package by improving the adhesion between the molding compound and the metal foil used as an electrical contact with the outside world. Another aspect of the present invention is to introduce a manufacturing process that contributes to the trend toward lower profile, smaller profile packages, thereby conserving device space. Another aspect of the present invention is:
Improve product quality by simplifying the process, control thermo-mechanical stresses, minimize moisture absorption, and provide overall in-process management without extra cost. , To increase reliability assurance. Another aspect of the invention is to make thin-profile packages flexible so that they can be applied to many families of semiconductor products, and to enable them to be applied to future generations of products. Introducing the idea of assembly that is common in These aspects are achieved by the teachings of the present invention on a method suitable for mass production. Various modifications have been successfully used to satisfy different choices of product geometry and materials.
In one embodiment of the present invention, a low profile device is created using the dimensions of the ridge simulating a ball and, accordingly, the stretch of foil material required to achieve this ridge. In another embodiment of the present invention, using a number of bumps and an array of simulated "ball" rows, some ball grid arrays of small geometries and chip scale
Make packaged devices. The technical advances represented by the present invention and its various aspects will become apparent from the following description of preferred embodiments of the invention, when considered in conjunction with the accompanying drawings and the novel features set forth in the appended claims. Let's be.

[0005]

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an integrated circuit (IC) having a small profile and low profile ball grid array (BGA) and chip scale (CSP) package. As defined herein, the term "outline" relates to the overall width and length of the IC package of the present invention. The package outline is determined by the package bottom area (fo
otprint). This is because it determines the surface area occupied by the package on the wiring board or assembly board. The word "chip-scale package" has two meanings. In a first sense, the package has an outer shape that increases the chip area by less than 20%. A chip scale package having only the dimensions of the chip itself is sometimes called a "chip size package". In a second sense, "chip-scale packages" are simply small-sized BGs.
Point to A. The term "profile" refers to the thickness or height of an IC package. This definition does not include the height of the solder balls before reflow when mounted on the board. As used herein, the term solder "ball" does not mean that the solder contacts are necessarily spherical. These may be of various shapes, such as hemispherical, semi-dome-shaped, frusto-conical, or general bumps. The exact shape is a function of the deposition scheme (such as evaporation, plating, or pre-fabricated units), and the reflow scheme (such as infrared or radiant heat), and the composition of the material. By controlling the amount of material and uniformity of the reflow temperature, several methods can be used to achieve geometric shape consistency. The solder "balls" may be composed of a lead / tin mixture or a conductive adhesive compound. As a preferred embodiment of the present invention, FIGS. 1A to 1C show different views of a rectangular BGA with 40 connections.
FIG. 1A is a top view of the package, showing a generally flat surface 1.
3 shows a plastic encapsulant 101 (typically an epoxy-based thermosetting material as commonly used in transfer molding processes) forming 03. Although the side length 102 in the example of FIG. 1A is 8.0 mm, the present invention is easily applied to BGA and CSP devices having a square or rectangular outer shape and a side length in the range of about 4.0 to 12.0 mm. it can.

FIG. 1B is a side view of the same BGA, partially shown in cross section. The package has a generally flat upper surface 103 and a generally flat lower surface 116. The package thickness 114 is 1.0 mm in this example. As shown by the cross-section (shaded portion 115), the molded plastic 111 penetrates all ridges 112 protruding from the generally flat lower surface 116. It is a major aspect of the present invention that these ridges 112 are formed in the same plastic molding process used to encapsulate the device. These ridges 112 may be shaped as part of a sphere, and thus may simulate a part of a solder "ball". For this reason, they may be referred to as "hills". Other shapes for the ridge 112 include truncated cones, or truncated pyramids, or any other three-dimensional shape that can be manufactured today. FIG. 1B shows several arrays of these mounds, indicated generally at 113. The hill metallization 117 and its thickness 117a are described in more detail in FIG. In a bottom view of the BGA package, FIG. 1C shows two rows of these ridges 121 arranged as solder balls in a conventional BGA. In the example of FIG. 1C, there are a total of 40 mounds. Although the present invention can be used with any number of mounds, the preferred number is from 4 to 80. In the example of FIG. 1C, the pitch 122 between the hills is 1.0
mm, and the interval 123 between the hills is 20 to 200 in width.
μm. The present invention can be used in any arrangement of mounds, including making "dummy" mounds that do not provide electrical connection. Further details and electrical effects of the hill are illustrated schematically in FIG.
3B shows a cross section of a portion of the BGA of Example B. The pressure applied to the molding compound 201 during the molding process forms a ridge 202. The ridge height 203 ranges from about 0.1 to 0.25 mm, and the hemispherical bottom diameter 204 is about 0.5 to 0.75 mm.

It is essential to the invention that the outside of the mound has a conductive, solderable surface 205. It is composed of a metal foil having a thickness 206 in the range of about 10 to 75 μm. The preferred thickness range for the metal foil is about 3
0 to 40 μm. The foil can be made of a material selected from the group consisting of copper, copper alloys, iron nickel alloys, aluminum, steel, and amber. Suitable copper and copper alloy foils are manufactured, for example, by Olin Corporation of Waterbury, Connecticut, USA. The solderable surface of the foil, facing the outside of the mound, is selected from the group consisting of copper, nickel, palladium, silver, gold, and platinum. Another option is tin-lead, tin-
Deposit layers of silver, tin-indium, and other solder alloys may cover the outside of the mound. The preferred embodiment is clean copper and a highly activated solder paste for joining to a motherboard. The choice of material is
Depending on the solder reflow method used (eg, time-temperature process, effectiveness of solder paste or flux). FIG. 2 shows that ridge 202 is electrically connected to terminals of the integrated circuit by wire bonds 207 (see also FIGS. 3A-3D). After the usual wire bonding method, the stitch of the bonding wire is attached to the metal of the hill, and the ball of the bonding wire is attached to the terminal (contact pad) of the IC chip. In order to be electrically separated, the metal foil covering the ridge must be mechanically separated from each other. This is indicated by groove 208 and is made, for example, by mechanical cutting using a saw blade (approximately 130 to 170 μm in width). The hemispherical hills significantly increase the bonding area between the molding compound and the metal foil. As a result, the bond strength is significantly enhanced and the package made according to the present invention is much less prone to stress or moisture delamination. 3A to 3D
Shows a method for manufacturing an IC device according to the present invention. FIG. 3A is a simplified cross-sectional view of a mold, generally designated 300, showing an upper half 301, a lower half 302, and a cavity 303 of the mold. The lower half 302 features a generally flat surface profile including a plurality of depressions 305. These recesses have a size and shape suitable for the purpose of creating molded bumps simulating solder balls on the device to be sealed. Edge 305 of depression 305
a is polished to avoid sharp edges. These depressions may have a shape selected from the group consisting of hemispheres, truncated cones, truncated pyramids, and related geometries that can be made to the steel of the mold at low cost.

FIG. 3A shows that cavity 303 holds pre-assembled IC chip 306. In another embodiment of the present invention, multiple IC chips and / or other electronic components can be pre-assembled. The chip 306 is mounted on the first surface 307a of the conductive sheet-like substrate 307. According to the invention, this substrate is preferably a metal foil having a thickness of about 10 to 75 μm. The second side 307b of the substrate 307 is made so that it can be soldered. Tip mounting
This is done with an adhesive epoxy or polyimide film. The input / output terminals of chip 306 are connected to substrate 307, preferably by wires 308. Typically, the wires 308 are connected to the chip terminals by ball bonding and to the substrate by stitch bonding, but wedge bonding at both ends of the wires could be substituted. A chip pre-assembled on the substrate is placed on the lower half 302 of the mold, and the locations 309 where the wires are welded on the substrate 307 are aligned with respect to the respective positions of the recesses 305 in the lower half of the mold. . This alignment, as shown in FIG.
Shown as 10. Thereafter, the mold is closed (see FIG. 3B). As shown in FIG. 3C, sealing material 311 is pressed into cavity 303 until the cavity is filled with material. Preferably, with an epoxy-based molding compound, an established transfer
Molding steps and controls are used (transfer temperature is usually about 170-180 ° C., transfer time is about 6-18 seconds). Typical ram pressures range from about 500 to 700 psi, which creates a pressure in the mold cavity of about 800 to 1600 psi (depending on the dimensions of the cavity). In the present invention, it is important that in the molding process and at these pressures, the foil 307 is applied to the contour of the face of the lower half 302 of the mold, in particular to the recess 305 of the mold. Thereafter, the molding temperature is lowered. Within about 90 to 130 seconds, the molding compound solidifies and at least partially polymerizes so that the mold can be opened. Thus, the outer surface of the hill is covered with the foil 3 on the solidified sealing material body.
Molded hill 3 surrounded by 07
12 is generated. As shown in FIG. 3C, each mound has a wire bond connecting it to a respective terminal of chip 306.

[0009] As mentioned above, the formation of the mound significantly increases the surface area between the molding compound and the mound foil, thereby increasing the adhesion between the molding compound and the metal foil, Reduce the susceptibility of the completed device to stress and moisture and increase its reliability. FIG. 3D shows the completed device generally at 320. In this device, Koyama 3
12 are electrically separated from one another by openings 313. These apertures can be cut with a high speed saw, focused laser, high pressure liquid jet, or any other low cost manner. It is an important advantage of the present invention that the formation of the ridges allows the conductive foil to be separated from the high-shear zone created during the dicing operation, thereby resulting in high quality devices manufactured. . Cavity 303
If more than one unit is placed in the units, they can typically be mechanically isolated from each other by sawing along edge (vertical) 314 . In this manner, a plurality of devices similar to that shown at 320, simulating conventional solder balls and having mounds 312 having solderable surfaces 315, can be manufactured in a low cost manner. In FIG. 3D, the size of the ridge 312 represented by the diameter 316 and the height 317 is determined mainly by the mechanical properties of the metal foil 307. With appropriate microcrystalline properties and mechanical and thermal history, a copper foil about 30 to 40 μm thick can grow about 15 to 22%. This means that for a desired ridge diameter of about 0.7 mm, a ridge height of about 0.2 mm can be achieved. At this height, BGA and CSP devices can be manufactured with a 1.0 mm profile that includes the height of the "ball" in the overall thickness. Although the invention has been described with reference to the illustrated embodiments, this description should not be construed as limiting the invention. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the invention, will be apparent to persons skilled in the art upon reference to the description. For example, the material of the semiconductor chip is silicon, silicon germanium,
It may be composed of gallium arsenide, or any other semiconductor material used in manufacturing. As another example, by using a suitably flexible foil, the shape of the molded ridge simulating a "ball" can be changed to an elongated structure. It is therefore intended that the appended claims encompass any such modifications or embodiments.

With respect to the above description, the following items are further disclosed. (1) A semiconductor device, an integrated circuit chip having at least one input / output terminal, a body of a sealing material for molding around the chip, having dimensions and shapes suitable for simulating solder balls. A semiconductor device comprising: a substrate forming a generally flat surface including at least one ridge having: and a ridge having a conductive and solderable surface connected to the terminal. (2) The device according to item 1, further comprising a layer of solder attached to the mound. 3. The device of claim 1, wherein the mound has a size of about 0.5 to 0.75 mm in diameter and about 0.1 to 0.25 mm in height. The device of claim 1, wherein the conductive surface of the mound comprises a metal foil having a thickness of about 10 to 75 μm. The device of claim 4, wherein the conductive surface of the mound comprises a metal foil having a thickness of about 30 to 40 μm. (6) The device according to item 4, wherein the foil is:
A device comprising a material selected from the group consisting of copper, copper alloys, iron nickel alloys, aluminum, steel, and amber. (7) The device according to item 6, wherein the foil is:
Furthermore, copper, nickel, palladium, silver, gold, platinum, tin
A device having the outwardly solderable surface of the ridge selected from the group consisting of lead, tin-silver, tin-indium and other solder alloys. (8) The semiconductor device according to (1), wherein the conductive surface of the mound is connected to the chip terminal by a length of a bonding wire, and one end of the length is connected to the surface. A semiconductor device mounted and the other end mounted to the terminal. (9) The semiconductor device according to (1), wherein the ridge has a shape selected from the group consisting of a hemisphere, a truncated cone, and a truncated pyramid. (10) The semiconductor device according to (1), wherein the ridge is formed by a molding process for sealing the chip.

(11) In a method of manufacturing a semiconductor device, a plurality of integrated circuit chips each having a plurality of input / output terminals are provided, the first and second surfaces are provided, and the second surface is soldered. Providing a conductive sheet-like substrate that is attachable, attaching the chip to the first surface of the substrate, and connecting the terminals to the surface by wire bonding so that the wire bond is welded. Forming a mold having upper and lower halves each having a cavity for holding a semiconductor device, the lower half having a plurality of depressions having dimensions and shapes compatible with the solder balls. The lower half of the substrate such that each wire bond location is aligned with a respective one of the recesses. Placed in, and closing the mold, press-fit a sealing material into the mold,
When the material solidifies by pressing the substrate against the contour of the face of the lower half of the mold, a mound is introduced into the body of the encapsulant at each location where a wire bond is attached to the substrate. A method comprising the step of: (12) The method according to (11), further comprising the steps of: opening the mold, electrically isolating the ridges from each other, and mechanically separating the chips from each other, thereby sealing. A semiconductor device formed. (13) The method according to (12), further comprising depositing a solder material on the second surface of the substrate covering the ridge. 14. The method of claim 12, wherein the electrical isolation comprises cutting the substrate material surrounding the ridge.

(15) An apparatus for manufacturing a semiconductor device, comprising a mold having an upper half and a lower half each having a cavity for holding a pre-assembled semiconductor chip on a conductive surface, wherein one of the halves is provided. Is a device having a generally flat surface profile including a plurality of depressions having dimensions and shapes commensurate with simulating solder balls. (16) The apparatus according to paragraph 15, wherein the depression has a size of about 0.5 to 0.75 mm in diameter and about 0.1 to 0.25 mm in depth. (17) The device according to paragraph 15, wherein the depression has a shape selected from the group consisting of a hemisphere, a truncated cone, and a truncated pyramid. (18) A semiconductor device, particularly a ball grid array or chip scale package, having an integrated circuit chip having at least one input / output terminal, and being molded around said chip to simulate solder balls. A body of encapsulant forming a generally flat surface including at least one ridge having a suitable size and shape, said ridge defining a conductive, solderable surface connected to said terminal. Semiconductor device.

[Brief description of the drawings]

FIG. 1 is a simplified diagram of a ball grid array device having forty “balls” according to an embodiment of the present invention.
A is a top view of the ball grid array device.
B is a simplified diagram combining a side view and a partial cross-sectional view of a ball grid array package according to the present invention.
C is a simplified bottom view of the ball grid array package according to the present invention.

FIG. 2 is a simplified cross-sectional view of a portion of a ball grid array according to the present invention.

FIG. 3 illustrates a process for making a device according to the present invention. A, B, and C are simplified cross-sectional views of the mold cavity at that time. D is a simplified diagram of a cross section of the manufactured device.

[Explanation of symbols]

 306 Chip 307 Substrate 308 Wire 312 Mound 313 Opening 314 Edge 315 Surface 316 Diameter 317 Height 320 Device

 ──────────────────────────────────────────────────の Continued on front page (72) Inventor David Earl, Key United States Texas, Richardson, Ambleside 1513

Claims (3)

[Claims] 1. A semiconductor device, comprising: an integrated circuit chip having at least one input / output terminal; a body of encapsulant molding around the chip, the dimensions being suitable for simulating solder balls. A semiconductor device comprising: a substrate forming a generally flat surface including at least one ridge having a shape; and the ridge having a conductive, solderable surface connected to the terminal. 2. A method of manufacturing a semiconductor device, comprising: providing a plurality of integrated circuit chips, each having a plurality of input / output terminals, having first and second surfaces, wherein said second surface is soldered. Providing a conductive sheet-like substrate capable of attaching the chip to the first surface of the substrate and connecting the terminals to the surface by wire bonding, whereby the wire bonds are welded. Forming a plurality of substrate locations, providing a mold having an upper half and a lower half, each having a cavity for holding a semiconductor device, the lower half including a plurality of depressions having dimensions and shapes compatible with the solder balls. The substrate in the lower half such that each wire bond has a generally flat surface profile and each wire bond location is aligned with one of the depressions. Disposing, closing the mold and pressing a sealing material into the mold, when the material solidifies by pressing the substrate against the contour of the surface of the lower half of the mold, a wire bond is formed. Forming a mound in the body of the sealing material at each location attached to the substrate. 3. An apparatus for manufacturing a semiconductor device, comprising: a mold having upper and lower halves each having a cavity for holding a pre-assembled semiconductor chip on a conductive surface, wherein one of the halves is one of: A device having a generally flat surface profile including a plurality of depressions having dimensions and shapes commensurate with simulating solder balls.