KR101198051B1 - Thin foil semiconductor package - Google Patents

Abstract

The present invention relates to a method and arrangement for using thin foils to form electrical interconnects in an integrated circuit package. One such arrangement involves a foil carrier structure that includes a foil attached to a carrier having cavities. Some methods of the invention involve attaching dies to a foil and sealing the foil carrier structure to the molding material. In one embodiment, the molding material presses the foil, which causes portions of the foil to extend into the cavities of the carrier. As a result, concave and convex regions are formed in the foil. The carrier is then removed, and portions of the convex regions of the foil are removed through one of various techniques, such as grinding. This process helps to define and electrically isolate the contact pads to the foil. The resulting molded foil structure can then be unified into multiple semiconductor packages.

Description

Thin Foil Semiconductor Packages {THIN FOIL SEMICONDUCTOR PACKAGE}

The present invention relates generally to the packaging of integrated circuits (ICs). More specifically, the present invention relates to a packaging method and arrangement involving thin foils.

There are many conventional processes for packaging integrated circuit (IC) dies. By way of example, many IC packages use metal leadframes stamped or etched from metal sheets to provide electrical interconnects with external devices. The die may be electrically connected to the lead frame through bonding wires, solder bumps or other suitable electrical connections. Generally, the parts of the die and leadframe are encapsulated with molding material to protect sophisticated electrical components on the active side of the die, while exposing selected portions of the leadframe to facilitate electrical connection with external devices. .

Many conventional leadframes have a thickness of approximately 4-8 mils. Further reducing the thickness of the leadframe provides several benefits, including the potential for preservation of the leadframe metal and reduction of the overall package size. In general, however, thinner leadframes tend to bend more during the packaging process. A support structure, such as a backing tape, is applied to the leadframe to reduce the risk of warpage. However, such a structure may involve higher costs.

In many cases, package designs have been proposed that use metal foils as electrical interconnect structures instead of leadframes. Although many foil based designs have been developed, in part, the foil based packaging process tends to be more expensive than conventional leadframe packaging, and in part conventional packaging equipment is used for such foil based package designs. As it is not very suitable for the following, nothing has achieved widespread acceptance in the industry.

While existing techniques for fabricating leadframes and packaging integrated circuits using leadframe technology are dominant, efforts are being made to develop more efficient designs and methods for packaging integrated circuits.

The present invention relates to methods and arrangements for using thin foils to form electrical interconnects in integrated circuit packages. One such arrangement involves a foil carrier structure, including a foil attached to a carrier having cavities. The cavities on the carrier define various pedestals that help support the foil. The pedestals form a device region pattern that defines an interconnect pattern for the semiconductor package.

Some methods of the present invention fabricate integrated circuit packages using the foil carrier structure. In one such method, integrated circuit dies are attached and wirebonded to a foil on a foil carrier structure. The foil carrier structure is then sealed with a molding material. The molding material presses the foil so that the shape of the foil follows some of the contours of the underlying cavities on the carrier. As a result, convex and concave regions are formed in the foil. Some of the recessed areas become similar to interconnect components such as contact pads and / or die attach pads. The convex regions form bumps in the foil. The carrier is then removed from the molded foil carrier structure, thereby exposing the reshaped foil. At least some of the bumps in the foil are removed using any of a variety of suitable techniques, including grinding. This process exposes portions of the molding material and isolating some of the concave regions to define electrical contact pads in the foil. The resulting molded foil carrier structure is then singulated into multiple integrated circuit packages.

The method has several advantages over existing techniques. By using thin foils, this method preserves the metal. No backing tape is required to support the foil. In addition, since the contact pads can be isolated through other techniques such as grinding, no photolithography technique is required.

In an alternative embodiment, instead of the carrier, the mold has device region patterns for reshaping the foil. In this embodiment, the carrier is attached to the foil to form a foil carrier structure. The carrier has perforations to help support the foil. After the dies are attached to the foil, the foil carrier structure is placed in the mold. Molding material flows through the holes in the carrier and presses the foil. This time the foil presses the device region patterns on the carrier. As a result, concave and convex regions are formed in the foil. The carrier can then be selectively removed. In this method, subsequent removal of portions of convex regions in the foil, formation of contact pads and unification occur in a manner similar to that described above. Other foil carrier structures and molds suitable for performing the operations are also described.

The invention and its advantages can be best understood with reference to the following description in conjunction with the accompanying drawings.
1A is a schematic top view of a foil carrier structure having multiple device region patterns in accordance with one embodiment of the present invention.
FIG. 1B is an enlarged top view of one of the device region patterns shown in FIG. 1A.
1C is a schematic side view of the foil carrier structure of FIG. 1A in accordance with an embodiment of the present invention.
2 is a process flow diagram for incorporating a foil in the packaging of an integrated circuit device in accordance with an embodiment of the present invention.
3A-3I schematically illustrate the steps in the process flow diagram of FIG. 2.
4A is a schematic top view of a foil carrier structure according to one alternative embodiment of the invention.
4B is a schematic top view of a carrier in the foil carrier structure shown in FIG. 4A.
4C and 4D show steps in a packaging process involving the foil carrier structure shown in FIG. 4A.
In the drawings, like reference numerals are sometimes used to refer to like structural elements. Also, it should be understood that the depictions in the figures are schematic and not proportional.

The present invention generally relates to the packaging of integrated circuits. More specifically, the present invention relates to a low cost improved method and arrangement of using thin foils to form electrical interconnects in integrated circuit packages.

Thin foils present several challenges for semiconductor manufacturers. As mentioned earlier, thin foils tend to bend under the stress of the packaging process. In addition, existing packaging equipment configured to handle leadframes is unsuitable for processing thin foils because they are different in size and weaker than leadframes.

Name of invention “Foil Based Semiconductor Package”, Wong et al. Patent application No. In a previous application of 12 / 133,335, the inventors proposed a novel carrier-based, low cost mechanism for thin foil packaging that addresses these challenges. Various embodiments of the invention described below also relate to thin foil packaging.

First, an embodiment of the present invention will be described with reference to FIGS. 1A to 1C. This embodiment involves a specially constructed foil carrier structure. The foil carrier structure includes a thin metal foil attached to the carrier. In the embodiment shown, the embossed carrier is used to form the desired metallization pattern in the foil. The pattern may include die attach pads, contact pads and / or any other desired metallization structures.

1A is a schematic top view of a foil carrier structure 100 that includes a foil (not shown) attached to a carrier 102. In the embodiment shown, the carrier 102 is embossed with device region patterns 104 and has fiducials 106 arranged along its periphery. The carrier 102 can be formed from a wide variety of materials, including aluminum, steel, copper, other metals, polyimide, plastic, ceramic, and / or epoxy. The foil carrier structure can have different dimensions depending on the needs of the particular application. If desired, the foil carrier structure may take the form of strips of similar size as panels or conventional leadframe strips.

1B is an enlarged top view of the device region pattern 104, including lead-related pedestals 106 and die-related pedestals 108. These structures extend from the web 114. It should be noted that FIG. 1B is just one of many arrangements possible.

FIG. 1C is a side view of the device region pattern shown in FIG. 1B. 1C proposes cavities 116 that define one or more webs 114 and pedestals 112. Pedestals 112 include a die-related pedestal 108 and a lead-related pedestal 106. The foil 118 is supported by the top surfaces 112 of the pedestals so that the gap 107 is formed around the various pedestals. The gap 107 is bounded by at least a portion of the foil and one or more cavities. Some embodiments of the present invention contemplate a molding operation in which the molding material presses the foil. The foil this time presses at least some of the cavities of the carrier to form concave and convex regions in the foil. The convex regions can then be removed via techniques such as grinding. The remaining portions of the foil define device regions suitable for attachment to integrated circuit dies. Hereinafter, these operations will be described in FIGS. 2 and 3A to 3I.

2 and 3A-3I illustrate a process 200 for packaging an integrated circuit device in accordance with one embodiment of the present invention. Initially, in step 202, the carrier structure 300 of FIG. 3A is provided that includes a foil 302 and a carrier 304. Foil carrier structure 300 includes cavities 306, web 312, lead-related pedestal 310, and die-related pedestal 303. 3A shows only a small portion of the larger foil carrier structure. Foil carrier structure 300 may take the form of foil carrier structure 100 of FIG. 1A even if this is not required. In the illustrated embodiment, the foil 302 is a copper foil and the carrier 304 is formed of steel. In alternative embodiments, different metal foils may be used in place of the copper foil, and different carrier structures may be used in place of the steel carrier. For example, the carrier may optionally be formed of copper, steel, aluminum, plastic, ceramic, other metals, non-conductive materials such as polyimide or a wide variety of other suitable materials. In some embodiments, the carrier 304 is drilled. (Examples of packaging operations involving such carriers are described below in conjunction with FIGS. 4A-4D).

The dimensions of the foil carrier structure 300 can be varied widely to meet the needs of a particular application. In some embodiments, the foil carrier structure 300 is approximately the size of a typical leadframe strip. The thickness of the foil 302 and the carrier 304 can also vary widely. In some embodiments, the foil has a thickness in the range of approximately 0.6 to 2 mils. The carrier may have a thickness in the range of approximately 5-12 mils. In general, it is advantageous to match the thickness of the foil carrier structure generally to the thickness of the standard leadframe, so that standard packaging equipment configured to handle the leadframe can be used to process the foil carrier structure.

In step 204 of FIG. 2, the dies 318 of FIG. 3B are mounted on the foil carrier structure 300. In the embodiment shown, die 318 is disposed on die-related structure 302. After the dies are attached, the dies are electrically connected to the foil by suitable means such as wire bonding. The wire bonded structure is shown in FIG. 3B. In some embodiments, such wire bonding and die attach operations are performed "blind." That is, the only or main reference points used in this operation are the origins on the parts of the carrier which are not covered by the foil. It should be understood that one of the important advantages of the described approach is that commercially available die attach and wire bonding equipment can be used in the die attach and wire bonding steps. The resulting structure has a plurality of dies electrically connected to the foil by bonding wires 316. In the embodiment shown, additional layers of nickel and palladium are provided on the top surface of the foil 302. The upper palladium layer helps to anchor the anchor wires 316 to the foil more firmly.

In step 206, at least a portion of the dies 318, wires 316 and foil carrier structure 300 of FIG. 3B are sealed with the molding material 314 of FIG. 3C to seal the molded foil carrier structure 301. Form. The molding material presses on the foil 302 and causes the foil to distal. As a result, the molding material 314 fills portions of the gap 306 and extends below the top surface 315 of the carrier 304. The foil 302 this time presses the cavities 305, web 312 and pedestals 302 and 310 of FIG. 3B. Because of this pressure, the foil 302 is reshaped along the contour of the cavities in the carrier. Thus, convex regions 322 and concave regions 320 of FIG. 3C are formed in the foil. In the illustrated embodiment, the concave regions 320 define metallization structures, such as contact pads, die attach pads, and the like. Convex regions 322 form bumps that extend outwardly from the foil, making it easier to separate them from the rest of the foil in a later step of the packaging process.

In an alternative embodiment, the carrier of the foil carrier structure has cavities similar to the cavities 305 of FIG. 3C, except that the cavities extend throughout the carrier. In this embodiment, the foil carrier structure is disposed in the mold cavity. The surface of the mold cavity is supported relative to the bottom surface of the carrier and defines various concave regions with the carrier. As in the embodiment shown, the molding material presses the foil and pushes the foil into the recessed areas and against the surface of the carrier and mold cavity. As a result, the foil is stretched and reshaped to the desired configuration. Some of these types of carriers lack a web, but instead support other pedestals on the carrier using other structures, such as tie bars.

Note that in the illustrated embodiment of FIG. 3C the molding material 314 is added in a single continuous strip. That is, the molding material was applied relatively uniformly over the molded portions of the foil 302. This kind of molding is not common in leadframe based packaging. Rather, the devices moved on the leadframe strips are typically molded individually or in sub-panels. The advantages of the molding material of the continuous strip are described in conjunction with FIGS. 3D, 3E and 208.

In step 208, the carrier portion of the molded foil carrier structure 301 of FIG. 3C is removed, resulting in the molded foil structure 303 of FIG. 3D. The carrier 304 of FIG. 3C is optionally reusable. At this point, the molding material provides a structural support for the foil instead of the carrier 304. It should be understood that the advantage of the continuous strip molding approach is that it provides a good support for the entire panel so that the strip can still be handled in the form of a panel. Conversely, if molding gaps are provided between the subpanels during the molding operation, the subpanels need to be handled independently after carrier removal.

In FIG. 3E, portions of the convex regions of the foil are removed. Reshaping the foil in FIG. 3C caused the convex regions or bumps 322 in FIG. 3D to extend from the bottom of the foil carrier structure 303. These portions of the foil are more easily removed by grinding and other cutting techniques. Suitable techniques other than grinding, such as laser cutting and etching, may also be used. The convex and concave regions of the foil of FIG. 3D are designed such that the removal of the convex regions of FIG. 3E at least partially isolates and defines metallization structures, such as die attach pad 324 and contact leads 326. . In alternative embodiments, different portions of the foil may protrude from the bottom of the carrier structure 303 and be removed.

One advantage of grinding or cutting techniques is that they can be more cost-effective. Some thin foil packaging methods use photolithography to etch the foil. Photolithography typically requires the application of a photoresist layer and various other processing steps. The techniques described above avoid the costs and delays associated with photolithography.

In some embodiments, cutting or grinding operations form an electroplating interconnect in the foil to facilitate later electroplating of metals such as tin or solder. 3F schematically shows a device region 328 with such interconnects. The device region 328, at the bottom of the molded foil structure 303 of FIG. 3E, has a die attach pad 324, contact leads 326 and electroplating interconnects 334. Electroplating interconnects 334 are electrically connected to the pads and leads and typically extend over saw streets used during unification. Electroplating interconnects 334 can also form conductive links between multiple device regions. It should be understood that device region 328 represents only one of many possible arrangements. By way of example, device region 328 may include ground bus bars and other suitable interconnect features.

As discussed above, some embodiments consider step 211 of FIG. 2, involving electroplating of the solder 318 of FIG. 3G onto the die attach pad 324 and contact leads 326. In step 212, the molded foil structure 303 is singulated along the projected saw streets 336 of FIG. 3G to form individual semiconductor packages. Molded foil structure 303 may be unified using a variety of techniques, including sawing and laser cutting. Unification may remove the electroplating interconnects 334 of FIG. 3F. Electroplating interconnects may also be removed using other suitable techniques, such as selective cutting. An enlarged side view of the unified package 306 is shown in FIG. 3H. A schematic bottom view of the package is shown in FIG. 3I. Bottom view shows die attach pad 324 and contact leads 326 surrounded by molding material 314.

It should be noted that the above-described tasks sometimes add distinctive features to the underside of certain packages and / or molded foil structures. By way of example, the depicted embodiment of FIG. 3H shows the bottom surface 340 of the package 306 with the protrusion 338 of molding material. The molding material is exposed to a portion of the protrusion. In some embodiments, the sides of the protrusion are covered with a metal foil and the molding material is exposed to the bottom of the protrusion. The protrusion extends lower than most of the surface area of the die attach pad 324 and the contact leads 326. The bottom face of the package 306 may of course be arranged in other ways.

4A-4D, alternative embodiments will now be described. In this embodiment, instead of the carrier, the mold has device region patterns in which a negative image is embossed into the foil. 4A is a schematic side view of a foil carrier structure 404 having a foil 402 attached to a carrier 406. As shown in FIG. 4B, which shows a top view of the carrier 406, the carrier lacks the cavities 305 of the foil carrier structure in FIG. 3A and has holes 408. The foil carrier structure 404 can be processed using operations similar to FIG. 2. For example, die attach and wirebonding may be performed on the foil carrier structure 404.

However, some tasks are different from that shown in FIG. Prior to the sealing process, the foil carrier structure 404 of FIG. 4C is placed in the mold 410. Mold 410 has cavities 416 and supports foil 402 with carrier 406 (not shown). During the sealing process, the molding material 412 passes through the holes of the carrier 406 and pushes the foil 402, as schematically shown in FIG. 4D. As a result, portions of the foil 402 extend into the cavities. Thus, concave regions 418 and convex regions 420 of FIG. 4D are formed in the foil. After this operation, the carrier 406 may be selectively removed from the molded foil carrier structure 405. Similar to the corresponding step of FIG. 2, portions of the convex regions of the foil are then removed, device regions are formed from the remaining concave regions of the foil, and the resulting structure is singulated to form multiple integrated circuit packages. do.

Although only a few embodiments of the invention have been described in detail, it should be understood that the invention may be embodied in many other forms without departing from the spirit and scope of the invention. In the above description, many of the leadframe-shaped structures (eg, foils) described include leads and / or contacts, frequently referred to herein as contact leads. In the context of the present invention, the term contact lead is intended to include leads, contacts and other electrical interconnect structures that may be present in a leadframe-shaped structure. Accordingly, the present embodiments are to be considered as illustrative and not restrictive, and the invention is not to be limited to the details given herein, but may be modified within the scope and equivalents of the appended claims.

Claims (20)

An apparatus for including a foil in a semiconductor package,
A carrier having a plurality of cavities, the carrier defining a plurality of pedestals defining at least one device region pattern; And
A metal foil supported by the carrier, the foil comprising the metal foil overlying the at least one device region pattern to help the pedestals to support the metal foil Device to include in the package. The method of claim 1,
A plurality of integrated circuit dies attached to the metal foil, each integrated circuit die placed over a portion of an associated device region pattern and attached to the metal foil in the region of the metal foil; And
And a plurality of bonding wires electrically connecting the integrated circuit dies to the metal foil. The method of claim 2,
Further comprising a molding material encapsulating the integrated circuit dies and the bonding wires,
And the molding material disperses the metal foil into the cavities such that the metal foil includes convex and concave regions. The method of claim 3, wherein
And a portion of the molding material extends into the cavities such that the molding material extends below the top surface of the carrier. The method of claim 1,
The carrier comprises a web supporting the plurality of pedestals,
And including a foil in the semiconductor package, with a gap between the metal foil and the web. The method of claim 1,
And at least some of the cavities extend entirely across the carrier. 7. The method according to any one of claims 1 to 6,
And the metal foil has a thickness in the range of 0.6-2 mils and the carrier has a thickness in the range of 5-12 mils. 7. The method according to any one of claims 1 to 6,
At least some of the cavities have a depth of at least 3 mils. 7. The method according to any one of claims 1 to 6,
The carrier comprises fiducials arranged along a circumference of the carrier,
Wherein the fiducials are configured to function as reference points for die attach and wirebonding. 7. The method according to any one of claims 1 to 6,
And the metal foil is a copper layer having at least one surface covered with palladium and nickel. 7. The method according to any one of claims 1 to 6,
And the carrier is reusable and is made of one of the group consisting of copper, aluminum, steel and epoxy. Providing a foil carrier structure comprising a metal foil attached to a carrier;
Attaching a plurality of dies to the metal foil;
Sealing the plurality of dies and portions of the metal foil with a molding material to form a molded foil carrier structure, the sealing step forming convex and concave regions in the metal foil, the concave Said regions defining at least one device region, each device region being configured to electrically connect with an integrated circuit die;
Removing at least a portion of the convex regions of the metal foil to expose a portion of the molding material and isolating a plurality of electrical contact pads for each device region. 13. The method of claim 12,
And singulating the molded foil carrier structure to form a plurality of packaged integrated circuit devices. 13. The method of claim 12,
Removing the carrier from the molded foil carrier structure after the sealing step and before the removing step. 13. The method of claim 12,
The carrier comprises cavities defining a plurality of pedestals defining at least one device region pattern,
The pedestals define concave regions in the sealed metal foil, and the cavities define convex regions in the metal foil. The method of claim 15,
During the sealing step, the molding material pushes the metal foil against the carriers, extending portions of the metal foil into the cavities to reshape the metal foil and convex regions of the metal foil. And a recessed area, the method of packaging an integrated circuit device. The method according to any one of claims 12 to 16,
Prior to the sealing, further comprising disposing the foil carrier structure on a mold;
The carrier comprises perforations,
The sealing step includes depositing molding material through the holes into the cavities of the mold, such that the molding material pushes the metal foil against the mold, causing portions of the metal foil to be inside the cavities. Extending the metal foil to reshape the metal foil and form convex and concave regions in the metal foil. The method according to any one of claims 12 to 16,
Removing at least a portion of the convex regions of the metal foil entails grinding. The method according to any one of claims 12 to 16,
The carrier comprises origins arranged along the periphery of the carrier,
The method of packaging the integrated circuit device,
Determining wire bonding points on the metal foil using the fiducial points as reference points; And
Based on the determining, attaching wires connecting the plurality of dies with the wire bonding points. A molded foil structure used in integrated circuit packaging,
The molded foil structure,
Metal foils;
A plurality of integrated circuit dies attached to the metal foil;
A plurality of bonding wires electrically connecting integrated circuit dies to the metal foil; And
A molding material sealing the integrated circuit dies and the bonding wires,
Wherein the molding material extends the metal foil such that the metal foil comprises convex and concave regions.

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