JPS60230794A - Video signal processor - Google Patents

Abstract

PURPOSE:To obtain video signals of multiplex time division system with simple constitution by selecting an amount of data to be read in memory so that a ratio of luminance signal data vs. chrominance signal data will be 2 vs. 1. CONSTITUTION:A switch circuit 5 switches sequentially input terminals A, B and C with the aid of f1+f2+f3 equal to a sum of sampling frequencies f1-f3 of respective A/D convertors 4a-4c. As a result, respective component signals CM1, CM2 and CM3 are repetitively read in this order by 1/(f1+f2+f3) period in a single memory 6 provided on the subsequent stage of the circuit 5. In this case, an amount of data to be read in the memory 6 is selected so that a ratio of luminance signal data vs. chrominance signal data will be 2 vs. 1. The data written in such a way is continuously read out as separate signals CM1, CM2 and CM3, and multiplex time division video signals can be obtained at an output terminal of the memory 6.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a video signal processing device, and is suitable for application to, for example, a video tape recorder (VTR).

[Background technology and its problems]

Conventionally, in a VTR, a video signal is composed of a time division multiplexed signal of each component signal and recorded and reproduced.

That is, the luminance signal Y (FIG. 2(A)) of one horizontal scanning period (H) is compressed to, for example, 1/2, and the first and second color difference signals B-Y (FIG. 2(A)) forming the color signal are compressed. B)) and R-Y
(Fig. 2 (C)) are compressed to 1/4 and arranged in a time division manner within the lH interval as shown in Fig. 2 (D), and the video signal CAV (Component Analog Vi
There was a device that recorded and played back data.

FIG. 3 shows a schematic configuration of a video signal processing device that forms the video signal CAV consisting of this time-division multiplexed signal.

In FIG. 3, an analog-to-digital converter 1a samples a luminance signal Y at a predetermined frequency (for example, 10 (MHz)), converts it into, for example, 8-bit digital data, and supplies it to a memory 2a. Also,
The analog-to-digital converters L and LC each convert the color difference signals B-Y and R-Y to a predetermined frequency (for example, 5 (MH
The data is sampled at z)), converted to 8-bit digital data, and provided to the memories 2b and 2c.

The frequency of the continuous clock applied to the memory 2a is selected to be twice the frequency of the write clock.

Therefore, reading from memory 2a is performed twice as fast as writing. Further, the memory 2a is controlled so that written contents are read out in the same order as written. On the other hand, in the memories 2b and 2c, the frequency of each successive clock is selected to be four times the frequency of the write clock. The memories 2b and 2c are also controlled so that written contents are read out in the same order as written. A write clock is applied to the memories 28 to 2c so that they perform write operations simultaneously, but successive clocks are applied only to the memory 2a for a period of 1/2H, and only to the memory 2b for the next 174H, and then In the next 1/411 period, memory 2
It can only be given to c.

The switch circuit 3 is provided on the output side of the memories 2a to 2c, and outputs successive data from the memory to which the above-mentioned successive clock is applied based on a control signal from the controller to an output terminal 0.
Send to.

In this configuration, the luminance signal Y and the first and second color difference signals B-Y and RY are sent to the analog-digital converter 1a.
= lc at a predetermined frequency, each converted to 8-bit digital data, and then stored in memory 2.
8 to 2C and stored in a predetermined area.

When the 8-bit digital data for the IH period has been stored, the controller sends the data to memory 2 for a period of 172H.
A is given successive clocks, and the switch circuit 3
A control signal is given to switch the connection to the memory 2a.

As a result, the stored content, that is, the luminance signal data Y, is read out and applied to the output terminal 0 at twice the writing speed to the memory 2a. After that period, during the next 1/41 period, the controller gives the read clock to the memory 2b, and at the same time, the switch circuit 3 is switched to the memory 2b. The stored content, that is, the first color difference signal B-Y is provided.

Then, during the next period of 174H, a continuous clock is applied from the controller to the memory 2C, the switch circuit 3 is switched and connected to the memory 2c, and the second color difference signal RY is applied to the output terminal 0.

When the signal appearing at output terminal 0 is converted into an analog signal, the video signal CAV shown in FIG. 2(D) can be obtained.

However, this conventional device requires a memory for each component signal, and also requires an interface circuit between the analog-to-digital converter and the memory for each component signal, making the device complex and It was getting larger.

In particular, when the memory is configured with an IC, the total number of bins is the product of the number of bits of data handled and the number of memories, which is extremely large, which is a factor that limits miniaturization, and the bins themselves Because the reliability of the system was low, the more bins there were, the lower the overall reliability was. Furthermore, since each memory is independent, it must also be controlled independently, which also increases the size and complexity of the device.

[Purpose of the invention]

The present invention has been made with these points in mind, and it is an object of the present invention to provide a video signal processing device that can obtain time-division multiplexed video signals with a simple configuration.

[Summary of the invention]

In order to achieve this object, in the present invention, a luminance signal, a first color signal, and a second color signal that arrive as component digital input signals are sequentially stored in a memory via a switch circuit that repeatedly switches in synchronization with the clock of the digital input. At the same time, the output video signal is obtained by reading out the memory in a predetermined order, and the switch circuit outputs the data of the luminance signal and the first video signal.
and second color signal data into the memory at a ratio of 2:1, it is possible to easily obtain an output video signal in the CAV signal format with a simple configuration that requires only one memory. I can do it.

〔Example〕

First, with reference to FIG. 4, the principle of the method for forming a video signal of a time division multiplexed signal according to the present invention will be outlined.

In the present invention, each component signal CMI, CH
2. Analog-digital converters 4a to 4C for converting CH2 into digital data are directly connected to input terminals A, B, and C of switch circuit 5, respectively.

The switch circuit 5 connects each analog-digital converter 48 to
Input terminals A, B, and C are sequentially switched at a frequency fl+f2+f3 equal to the sum of sampling frequencies f1 to f3 of 4c. Therefore, the single memory 6 provided at the next stage of the switch circuit 5 receives the component signal CMI.

If CH2 and CH2 are in this order, then l/(fl+f2+f
It is written repeatedly at the cycle of 3).

In the present invention, the amount of data to be stored in the memory 6 is selected so that the ratio of luminance signal data to color signal data is 2:1. The data written in this manner is continuously read out for each component signal CMI, CH2, CH2.

Thus, a time-division multiplexed video signal appears at the output end of the memory 6.

In this manner, the present invention repeatedly stores each component signal in a single memory and controls the write address or subsequent address to form a video signal in which each component signal is arranged in a time-divisional manner. This point differs from the conventional method in which one memory stores one component signal.

Hereinafter, one embodiment of the present invention will be described in detail with reference to FIG.

In FIG. 1, each of the low-pass filters 78 to 7C passes only necessary band components of the luminance signal Y, which is a component signal, and the first and second color difference signals B-Y and R-Y, which are color signals. 4 to be applied to the corresponding analog-to-digital converters 8a to 8C.

Each of the analog-digital converters 8a to 8C converts the luminance signal Y and the first or second color difference signal BY, RY into 8-bit digital data each time it receives a clock pulse from the clock generation circuit 9. , its output end is connected to the input end of the switch circuit IO.

The clock generation circuit 9 transmits clock pulses synchronized with each component signal Y, BY, RY based on the reference signal REF to the analog-digital converters 88 to 8c.
It is designed to be given to The clock generation circuit 9 supplies a clock pulse of f=13.5 (Mllz), for example, to the analog-digital converter 8a to which the luminance signal Y is output, and the first or second color difference signal B4', RY is supplied. A clock pulse of 6.75 (Mllz), which is half the numerator, is applied to the analog digital converter 8b or 8c. Follow-C1 Figure 5 (
As shown in Δ) to (C), the analog-to-digital converter 8
From a, luminance signals Yli, Y12, Y21, Y2 are sampled and digitized every 1/f period.
2... are sent out, and the first color difference signals BYI, BY2... sampled and digitized every 2/f period are sent out from the analog-to-digital converter 8a. From 8c, second color difference signals RYI, XRY2, . . . are sampled and digitized every 27 cycles.

Here, the frequency of the clock pulse is changed depending on the analog-to-digital converter because of the frequency band (0 to 4.2 (MHz)) of the luminance signal Y and the frequency band of the color difference signal B-
Frequency band of Y, RY (0 to 500 (Mll
This is because the required number of samplings is selected in consideration of the amount of information due to the difference in z)).

The switch circuit IO has four input terminals A, B, and C.

The input terminals A and C are supplied with digital data from the analog-to-digital converter 8a, the input terminal B is supplied with digital data from the analog-to-digital converter 8b, and the input terminal is supplied with analog-to-digital converter 8a. Digital data is supplied from the device 8C.

The switching actuator 10a of the switch circuit 10 is operated at input terminals A, B, C,
D and the output terminal O as shown in FIG. 5(D), the input terminal A,
B, C, and D are sequentially switched and connected in this order, and the switching frequency is selected to be 2f (27 (MHz)). Since there are four input terminals, the cyclic frequency of the switching actuator 10a is 1/4 of the switching frequency 2f, that is, f/2(6,
75 (Mtlzl). Therefore, as shown in FIG. 5, the luminance signal Y is sampled twice while the actuator 10a goes around once, and the color difference Sakaki signals BY and RY are sampled once. Thus, the luminance signal Y and the color difference signals B-Y, II-Y are as shown in FIG. 5(E).
As shown in , the digitized luminance signal, first and second color difference signals Yll, B
It is repeated as YI, Y12, RYI, . . . and is applied to output terminal 0.

A memory 11 is connected to an output terminal O of the switch circuit 10.

The memory 11 is designed to read out the previous II worth of digital data at the same time as it writes II worth of digital data, so that the area where it is being written and the area where it is being read are separate. controlled by. The memory 11 writes 8-bit digital data (FIG. 5(E)) from the switch circuit 10 to a predetermined address (FIG. 6(E)) every time a write address signal is given from the memory controller 12.
^)) Each time a successive address signal is applied from the memory controller 12, the stored data is read out and applied to the synchronization signal addition circuit 13.

The memory controller 12 includes clock generation circuits 9 to 2.
A clock pulse of f (27 (MHz)) is received, and a write address signal is given to the memo January 1 in which the address increases (or decreases) by 1 according to the clock pulse. At the same time, as shown in FIG. 6(B), the luminance signal components Yll, Y12, Y21, . Color difference signal components BYI, BY2...
. is read out, and then the second color difference signal component RYI,
A successive address signal is applied to the memo January 1 so that RY2, . . . are read out successively. The memory controller 12 is configured to provide a control signal synchronized with successive address signals to the synchronization signal adding circuit 13.

The memory controller 12 is also provided with a clear signal Zero, which is generated when the clock generation circuit 9 detects the beginning (or end) of the IH period based on the reference signal REF. At that time, memory controller 1
2 sets the write address signal and read address signal to initial values.

Based on the clock pulse from the clock generation circuit 9, the synchronization signal addition circuit 13 adds a digital audio signal and six horizontal synchronization signals to the time-division multiplexed video signal (FIG. 6(B)) provided from the memory 11. , a vertical synchronization signal and a color burst signal are added to the digital-to-analog converter 14.
It is designed to be given to

The digital-to-analog converter 14 receives clock pulses from the clock generation circuit 9, converts the 8-bit digital data into analog data at a period of 1/2r, and supplies the analog data to the low-pass filter 15. The video signal CAV shown in FIG. 2(D) is output by suppressing high frequency components higher than the frequency that the signal can take.

In the configuration shown in FIG. 1, the first and second luminance signals Y1
The color difference signals B-Y and RY have unnecessary components removed through low-pass filters 7a-7c, respectively, and are then applied to analog-digital converters 88-8C.

Ikki signal Y is converted into digital data Y11, Y12, Y21, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y21, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y21, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22, Y22 from the analog digital converter 8a have a period of 1/f as shown in FIG.
1: Converted and applied to input terminals A and C of the switch circuit IO. On the other hand, the first color difference signal B-Y is the fifth color difference signal B-Y.
As shown in Figure (B), the digital data BYI, BY2, etc. are converted to the switch circuit 10 at a cycle of 27f.
The second color difference signal R-Y is similarly applied to the input terminal B of the digital data IIYI, RY2... (fifth
(C)) and is applied to the input end of the switch circuit 10.

These signals given to the manual inputs mA, B, C, D of the switch circuit IO are connected in the order shown in FIG. 5(E) by switching the switch circuit 10 as shown in FIG. 5(D). Video data Yll, BYI, Y12, RY
Give I, Y21... to the input end of memo January 1.

In synchronization with this, the memory 12 has a memory controller 12
A write address signal is applied from 1 to 1, and the signal applied to the input terminal of memo January 1 (FIG. 5 (E)) is stored in the order of address numbers shown in FIG. 6 (A>).

When the IH period ends, a clear signal Zero is applied from the clock generation circuit 9 to the memory controller 12, and the memory controller 12 returns the write address signal and successive address signal to their initial values. Therefore, the memory 11 moves on to the next write and read operations.

The memory 11 is given successive address signals from the memory controller 12, and stores the already stored digital data of the previous lH period (data shown in FIG. 6(A)) in the sixth
As shown in Figure (B), the luminance signal components Yll, Y12
, Y21 , .=YN2 , first color difference signal component B
YI, BY2..., BYN, and the second color difference signal components RYI, RY2..., IIYN are read out in this order.

This read signal (FIG. 6(B)) is added with a horizontal synchronization signal, a vertical synchronization signal, and a color burst signal in the synchronization signal addition circuit 13, and then sent to the digital-to-analog converter 1.
given to 4.

This signal is sequentially converted into analog data by a digital-to-analog converter 14, and then unnecessary frequency components are removed by a low-pass filter 15, and the signal is sent out from an output terminal 011T as a time-division multiplexed video signal CAν.

In this way, according to the configuration of FIG. 1, one memory 11
．． A time division multiplexed video signal CAV can be obtained with a simple configuration of one memory controller 12 and one interface (not shown). In particular, when the memory is configured with an IC, the number of IC bins is smaller than in the past, which contributes to miniaturization and high reliability.

By the way, in addition to being supplied with component signals, a video signal processing apparatus may also be supplied with a video signal that is already a time division multiplexed signal.

In this case, the analog-to-digital converter 8a converts 2f(
27 (MHz)) and converted into 8-bit digital data, and stored in the memory 1 via the switch circuit 10 in which the actuator 10a is always connected to the input terminal A, and the stored order is By sequentially outputting the signals in the same order as shown in FIG. 1, a time division multiplexed signal having the same phase as the time division multiplexed signal formed when each component signal is input can be obtained with the configuration shown in FIG.

Here, considering that the analog-to-digital converter 8a responds to this case, 2f (27 (MHz)). Note that in the conventional video signal processing device, 'C' is already given a time-division multiplexed video signal. In order to make the output signal from the device when the component signal is given the same phase as the output signal from the device when the component signal is given, a separate control circuit must be used or complicated control must be performed. With the configuration of FIG. 1, such a problem cannot occur.

In addition, in the embodiment described in -F, successive addresses are controlled so that a time division multiplexed signal can be formed, but the write address signal is controlled to write to and read out the memory so that a time division multiplexed signal is formed when viewed in the order of address numbers. may be performed in order of address number. Furthermore, the synchronization signal addition circuit 13
Although shown in FIG. 2, the device is provided before the digital-to-analog converter 14, but it can also be provided after the digital-to-analog converter 14.

〔Effect of the invention〕

As described above, according to the present invention, each component signal is given to one system of memory at a predetermined period, and the write address or successive address is controlled to obtain a time-division multiplexed video signal. Accordingly, it is possible to provide a video signal processing device having the following configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a video signal processing device according to the present invention, FIG. 2 is a route diagram for explaining the configuration of a time division multiplexed signal, and FIG. 3 is a block diagram showing the configuration of a conventional device. FIG. 4 is a block diagram showing a schematic configuration of the present invention, and FIG.
6 and 6 are route maps for explaining the operation of each part of the apparatus shown in FIG. 1. 48-4c...Analog-digital converter, 5...
Switch circuit, 6...memory.

Claims (1)

[Claims] The luminance signal and the first and second color signals that arrive as component digital input signals are sequentially read into the memory via a switch circuit that repeatedly switches in synchronization with the clock of the digital input, and the memory is read into the memory at a predetermined time. A video signal processing device characterized in that data of the ↓ read out in order and data of the second color signal are taken into the memory at a ratio of 2:1.