JP2508514B2 - Image storage - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image storage device for storing color video signals and performing special effect processing and the like.

[Outline of Invention]

The present invention relates to an image storage device, which writes data in a valid screen period of a decoded color video signal in a memory, detects a signal level in a color burst period, and writes the detected value data in an arbitrary area of the memory. By incorporating this, the increase in the storage capacity of the memory can be minimized and good color video signal processing can be performed.

[Conventional technology]

It is possible to AD-convert a color video signal and write it in a memory, and process the data written in this memory to perform time axis correction, noise reduction, special effects, and the like.

In that case, for example, as a special effect, move or enlarge the figure,
In order to perform processing such as reduction, writing the color video signal in the memory in the so-called component format can facilitate the subsequent processing. That is, for example, as shown in FIG. 6, a reproduced video signal from, for example, a VTR (91) is supplied to a YC separation circuit (92) to separate a luminance signal Y and a chroma signal C, and the separated chroma signal C Is supplied to the decoder circuit (93) to separate, for example, U-axis and V-axis signals. Then, the above-mentioned luminance signal Y and the signals of the U and V axes are independently written in the memory (94) in the component format and processed.

During reading, the luminance signal Y read from the memory (94) is supplied to the mixing circuit (95) and the memory (9
4) U and V axis signals read from the encoder circuit (96)
The chroma signal C that is supplied to and formed in the mixing circuit (95)
Is supplied to. Then, the mixed luminance signal Y and chroma signal C are taken out to the output terminal (97).

However, in this device, there is no problem if, for example, all the data from the vertical synchronization to the vertical synchronization of the video signal is written as the data to be written in the memory, but normally the video signal is effective to reduce the memory capacity. Only the data of the screen period is written. In that case, if the modulation axes of the decoding circuit (93) and the encoding circuit (96) do not completely match, hue (hue) variation may occur.

With a signal whose chroma signal level is fluctuating like VTR output, when supplying this directly to the receiver for playback, there is no problem because a color burst signal is detected on the receiver side and so-called ACC is performed, If you want to write only the effective screen to the memory as described above, add this before the decoding circuit (93).
It is necessary to provide an ACC circuit to eliminate fluctuations in the chroma signal level, which complicates the configuration.

When the signal is a black and white signal, chroma noise may occur in the reproduced image if the burst signal is added on the output side of the memory.Therefore, the output side of the memory determines whether the burst signal is color black and white. The configuration of the color killer such as the suspension of the addition is required, which also complicates the configuration.

When digitally decoding / encoding, the phases of the above-mentioned axes can be perfectly matched,
Also in this case, if there is a phase fluctuation such as an APC residual error between the sampling clock such as AD and the burst signal, a Hue fluctuation will occur.

In contrast to the above items (1) to (5), if the data is written in the memory including the burst period, the above problem is solved. However, in order to write data up to the burst period, it is necessary to increase the memory capacity by several percent, and there is a fear that the price will increase due to the increase in the size of the memory.

[Problems to be solved by the invention]

As described above, in the conventional technique, since burst information is not transmitted, there is a high possibility that image deterioration such as hue variation will occur, and in order to write to the memory until the burst period, the memory capacity will increase significantly. There were problems such as.

[Means for solving problems]

The present invention decodes a color video signal (circuit (5))
In the image storage device adapted to be written into the memory (4), the signal level of the decoded color video signal in the color burst period (sample hold circuit (8U)
(8V)) is detected (switch (6U) (6V)), and the data of the detected value and the data of the effective screen period of the decoded color video signal (AD conversion circuit (9U) (9V)) are detected. Are written in arbitrary areas of the memory (write address forming circuit (15)).

[Action]

According to this, since the burst information can be transmitted only with the memory capacity for one data, an increase in the memory capacity can be minimized, and an extremely good image can be obtained by transmitting the burst information.

〔Example〕

In FIG. 1, (1) is an input terminal to which a color video signal from a VTR (not shown) or the like is supplied, and the signal from this input terminal (1) is supplied to the YC separation circuit (2). Thus, the luminance signal Y and the chroma signal C are separated, and the luminance signal Y is supplied to the memory (4) through the AD conversion circuit (3). Also, the separated chroma signal C is the decoder circuit (5).
To separate the signals of the U-axis and V-axis, for example. These separated U and V axis signals are each switched (6U)
(6V) is supplied to one fixed contact, low-pass filter (7U) (7V), sample and hold circuit (8U)
It is supplied to the other fixed contact of the switch (6U) (6V) through (8V). The signal obtained at the movable contact of the switch (6U) (6V) is supplied to the memory (4) through the AD conversion circuit (9U) (9V).

Further, the luminance signal Y from the YC separation circuit (2) is supplied to the separation circuit (10) for the horizontal synchronization signal H, and the separated horizontal synchronization signal H is supplied to the burst sampling pulse generation circuit (11) to perform the color burst period. Pulse signal B located at the end of
Is generated and supplied to the sample hold circuit (8U) (8V).

Further, the horizontal synchronizing signal H from the separation circuit (10) is supplied to the effective screen signal generating circuit (12) to generate the pulse signal Ex in the effective screen period starting one clock before the effective screen, and at the same time, the first 1 A pulse signal Bx for the clock period is generated, and the switch (6U) (6V) is switched to the sample hold circuit (8U) (8V) side by the pulse signal Bx.

Further, the horizontal synchronizing signal H from the separation circuit (10) is supplied to the write clock generating circuit (13) to generate a write clock synchronized with the horizontal synchronizing signal H and having a color sub-carrier frequency of, for example, four times. This clock signal is supplied to one fixed contact of the switch (14), the other fixed contact of the switch (14) is grounded, and the switch (14) is supplied from the effective screen signal generating circuit (12). It is switched to the write clock generation circuit (13) side by the pulse signal Ex of.

The clock signal from the switch (14) is supplied to the write address forming circuit (15), and the formed address is supplied to the memory (4).

Further, a read clock signal having a quadruple color sub-carrier frequency from the read clock generating circuit (16) is supplied to one fixed contact of the switch (17), and the other fixed contact of the switch (17) is grounded. Further, the clock signal from the generation circuit (16) is supplied to the synchronization board (18) to generate desired control pulse signals.

That is, first, a pulse signal Ey is generated by adding one clock period to the length of the effective screen period from the position of the beginning of the burst period with respect to the horizontal synchronizing signal H, and this pulse signal Ey causes the switch (17) to generate a read clock. Switched to the circuit (16) side.

The clock signal from the switch (17) is supplied to the read address forming circuit (19), and the formed address is supplied to the memory (4).

As a result, the luminance signal Y read from the memory (4)
Is supplied from the beginning of the burst period to the delay circuit (20) for a time period corresponding to one clock before the effective screen period, and the delayed luminance signal Y is supplied to the mixing circuit (22) through the DA conversion circuit (21). It

Further, the signals Ux and Vx read from the memory (4) are supplied to one fixed contact of each of the switches (24U) (24V) through the delay circuits (23U) (23V) similar to the above, and at the same time, the memory (4) The signals Ux and Vx from the respective terminals are supplied to the other fixed contacts of the switches (24U) (24V) through the latch circuits (25U) (25V).

Further, a pulse signal By of the first one clock period of the pulse signal Ey is generated from the synchronization board (18), and this pulse signal By is generated.
Is supplied to the latch circuit (25U) (25V), and this pulse signal By and the pulse signal B located at the end of the burst period are supplied to the SR flip-flop (26), and the Q of this flip-flop (26) is supplied. Switch at output (24U) (2
4V) is switched to the latch circuit (25U) (25V) side.

Then, the signals from the switches (24U) (24V) are respectively supplied to the encoder circuit (28) through the DA conversion circuits (27U) (27V), and the encoded chroma signal C is supplied to the mixing circuit (22). It is mixed with the luminance signal Y from the conversion circuit (21). Further, the horizontal synchronizing signal H from the synchronizing board (18) is supplied to the mixing circuit (22), and the mixed signal is taken out to the output terminal (29).

Therefore, in the configuration described above, when a color video signal such as A in the writing time chart shown in FIG. 2 is supplied to the input terminal (1), the YC separation circuit (2) and the decoding circuit (5) The luminance signal Y and the chroma signal U / V axis signals as shown in FIGS. Here, the burst period in the signals on the U and V axes has a level corresponding to the phase and level of the burst signal. On the other hand, a pulse signal B as shown in FIG. 8E is generated from the horizontal synchronizing signal H in the luminance signal Y with a predetermined delay time, and the levels of the U and V axis signals (burst period) in this period are sampled and held. . Further, a pulse signal Ex as shown in FIG. F is generated, and write addresses are sequentially formed in this period, and
In the first one clock period of this period, the pulse signal Bx is generated as shown in FIG. 7G, and the switch (6U) is generated in this period.
(6V) is switched, and the level of the burst period becomes 1 immediately before the effective screen period of the U and V axis signals as shown in FIGS.
The signals Ux and Vx inserted during the clock period are formed. Then, the signals Ux and Vx and the above-mentioned luminance signal Y are added to the AD conversion circuit (9
U) (9V) (3) digitally converted and written in memory (4).

Further, at the time of reading, first, the synchronizing board (18) generates a horizontal synchronizing signal H and pulse signals Ey, By as shown in the reading time charts A to C shown in FIG. And pulse signal E
The memory (4) is read during the period y, and the medium luminance signal Y is read.
Is delayed by the time (DLY) shown in the figure and DA conversion circuit (2
The signal is supplied to 1) and the signal is as shown in FIG. On the other hand, the signals Ux and Vx are latched for the first one clock period read, and the latched signal is continuously taken out during the Q output of the flip-flop (26). The time-delayed signal is connected, and this signal is supplied to the DA conversion circuit (27U) (27V),
The signal is as shown in F. Then, by mixing these signals and further adding the horizontal synchronizing signal H, a signal substantially equal to that supplied to the input terminal (1) as shown in FIG. 7G is taken out to the output terminal (29). It

Thus, in this device, the data of the effective screen of the color video signal is written in the memory and further read out. According to the above-mentioned device, the level of the burst period of the signals of the U and V axes is one clock period. Since the data is provided immediately before the effective screen period data, the burst signal can be restored by using this data at the time of reading, and a good color video signal can be formed. That is, the information of the burst signal in the color video signal is transmitted, which can solve the above problems (1) to (3) and eliminate the risk of image deterioration.

Further, according to this apparatus, the memory capacity used for transmitting burst information is only one clock period, that is, one data, for each horizontal period, and burst information can be transmitted with an extremely small increase in memory capacity. .

The burst information may be provided immediately before the effective screen period or immediately after the effective screen period of the previous horizontal period. Further, if the memory can be randomly accessed, only burst information can be collectively written in an arbitrary memory area. In this case, the fluctuation of the burst information is relatively small. For example, one data is represented every several horizontal periods. It is possible to further reduce the memory capacity.

Further, in FIG. 4, the supply of the write clock is controlled without using the sample hold circuit or the like described above so that the same memory (4) can be written. That is, in this figure, the effective screen signal generating circuit (12) generates a pulse signal E only during the effective screen period, and this pulse signal E and the above-mentioned pulse signal B are added by the OR circuit (30) to obtain the above-mentioned document. The switch (14) is switched by a signal as shown in J of the built-in time chart.

According to this, first, the burst information is 1 in the pulse signal B.
The data is written, then the writing is stopped, and the data of the valid screen period is further written by the pulse signal E. Therefore, similarly to the above, writing is performed with the burst information data immediately before the data of the effective screen period.

In this circuit, the output of the AD conversion circuit (9U) (9V) is supplied to the low-pass filter (31U) (31V), and the output of this low-pass filter (31U) (31V) is switched only during the burst information period (32U). It is also possible to reduce the noise of burst information by switching (32V) and taking it out. Further, in this case, an average value circuit may be provided instead of the low pass filter.

Further, at the time of reading, the synchronous board (18) generates an addition signal of the pulse signal By and the pulse signal E as shown in H of the above-mentioned reading time chart, and switches the switch (17) to thereby delay the above-mentioned delay. The signal can be read out except for the circuit and the like.

Further, FIG. 5 shows a case of performing digital YC separation and decoding. In this example, the horizontal sync signal H is supplied from the horizontal sync separator circuit (10) to the sampling pulse generation circuit (40) and synchronized with the horizontal sync signal H. For example, a sampling pulse having a quadruple color sub-carrier frequency is generated, and this sampling pulse is supplied to the AD conversion circuit (3) and the YC separation circuit (2). The sampling pulse is also supplied to the switch (14) as a write clock. Further, the chroma signal C separated by the YC separation circuit (2) is supplied to one fixed contact of the switch (51) and is also supplied to the other fixed contact of the switch (51) through the inverter (52). The signal from 51) is supplied to the latch circuits (53) and (54). Then, the sampling pulse described above is converted into a pulse signal with a duty of 50% by the frequency dividing circuit (55) of 1/2,
The switch (51) is switched by this signal, and the latch circuits (53) (54) are driven by this signal and the signal obtained by inverting this signal by the inverter (56),
Chroma signal U and V axis signals are taken out from the latch circuits (53) and (54).

Therefore, also in this circuit, writing to the memory (4) similar to that described above can be performed by switching the switch (14) with the pulse signal of E + B, for example.
In this example, the sample-hold circuit may be used, and the reading may be performed by any of the above-mentioned configurations.

〔The invention's effect〕

According to the present invention, the burst information can be transmitted only with the memory capacity for one data, so that the increase in the memory capacity can be minimized and an extremely good image can be obtained by transmitting the burst information.

[Brief description of drawings]

FIG. 1 is a block diagram of an example of the present invention, FIGS. 2 to 5 are diagrams for explaining the same, and FIG. 6 is a diagram for explaining a conventional technique. (1) is an input terminal, (2) is a YC separation circuit, (4) (9U)
(9V) is AD conversion circuit, (5) is decoding circuit, (6U)
(6V) (14) is a switch, (7U) (7V) is a low pass filter, (8U) (8V) is a sample hold circuit, (10) is a horizontal sync separation circuit, (11) is a burst sampling pulse generation circuit, ( 12) is a valid screen signal generation circuit, (13) is a write clock generation circuit, and (15) is a write address formation circuit.

 ─────────────────────────────────────────────────── ─── Continuation of front page (72) Inventor Takayuki Sasaki 6-735 Kita-Shinagawa, Shinagawa-ku, Tokyo, Sony Corporation (56) Reference JP-A-58-170178 (JP, A) JP Sho 60-38998 (JP, A)

Claims (1)

(57) [Claims] 1. Decoding means for decoding first and second color signals from a color video signal, and a memory for writing a luminance signal of the color video signal and the decoded first and second color signals. The memory so that the data of the color burst section and the effective video section of the decoded first and second color signals and the data of the effective video section of the luminance signal are written in a predetermined area of the memory. Write address control means for controlling the address, and data of a color burst section and an effective video section of the decoded first and second color signals and an effective video of the luminance signal from a predetermined area of the memory. Read address control means for controlling the address of the memory so that the data of the section is read out; The decoded data of the color burst section of the first and second color signals and the data of the effective video section, and the data of the read effective video section of the luminance signal are respectively stored at predetermined positions in a horizontal period. Arranging means for arranging, and encoding the data of the color burst section of the decoded first and second color signals and the data of the effective video section of the decoded first and second color signals arranged above. An image storage device comprising: an encoding unit that performs the above-described encoding; and an addition unit that adds the encoded first and second color signals, the read luminance signal, and the synchronization signal.