KR100281874B1 - Video signal processor eliminating the line delay of luminance signal - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly, to a decimation apparatus in which a line memory of luminance (Y) data is removed. A video signal processing apparatus for decimating a video signal composed of luminance and chrominance data, comprising: a first line memory configured to delay input first color difference (Cr, Cb) data to a predetermined value and output second color difference data; A second line memory for outputting third color difference data by delaying the second color difference signal delayed in the first line memory to a predetermined value, and filtering the first, second, and third color difference data, and deciding the filtered color difference data. A decimation unit for performing a mashing process, a shuffler for inputting the luminance data and the color difference data decimated by the decimation unit at the same time to perform shuffling, according to the present invention, a delay for delay of the luminance signal By implementing decimation of the chrominance signal without using line memory, the cost and power consumption of the system can be reduced.

Description

Video signal processor eliminating the line delay of luminance signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a video signal processing apparatus, and more particularly, to a decimation apparatus in which a line memory of luminance (Y) data is removed. In general, SD DVCR (Standard Definition Digital Video Cassette Recorder) of a PAL system decimates a color difference signal in a vertical direction. 1 is a block diagram showing a color difference signal decimation apparatus in a conventional SD-VCR. In the PAL system, one luminance (Y) signal and two color difference (Cr, Cb) signals are configured as video signals. These data amounts are in a ratio of 4: 2: 2. Accordingly, the SD-DVCR performs decimation in the vertical direction to reduce the data amount of the color difference (Cr, Cb) signal by 1/2. The color difference signals composed of Cr and Cb are input at 6.75 MHz data rate, and the two color difference signals are processed on a 13.5 MHz data rate and loaded on one bus. Also, in order to perform decimation in the vertical direction, a signal input in a raster scan order must delay a color difference signal using a line memory. As illustrated in FIG. 1, the video color difference signals Cr and Cb are delayed by one line through the second line memory 120 and by one line delay through the third line memory 130. The decimation unit 140 performs low pass filtering and decimation using the outputs of the second line memory 120 and the third line memory 130 and the input video signal, that is, the color difference signal. In this case, the luminance Y signal is delayed by one line through the first line memory 110 in order to match the phase with the color difference signal output from the decimation unit 140. The shuffle unit 150 inputs luminance (Y) and color difference (Cr, Cb) signals that are matched in phase to perform shuffling.

2 is a detailed view of the shuffle unit of FIG. 1 and includes a shuffle memory 210, an address generator 220, and a timing controller 230. The timing controller 230 applies timing information to the address generator 220. The address generator 220 generates an address suitable for the input signal to the shuffle memory 210 by referring to the timing information so that the data is read and written to the shuffle memory 210. The shuffle memory 210 performs a shuffling operation by addressing designated by the address generator 220. As shown in FIG. 2, the address generator 220 recognizes an address generation time by one timing controller 230. Therefore, in order to reduce the complexity of the address generator 220 and to simplify the design, as shown in FIG. However, since the luminance signal line memory 110 is used, the system cost increases and the circuit becomes complicated.

An object of the present invention is to provide an apparatus for implementing decimation of a color difference signal without using a delay line memory for delaying a luminance signal.

1 is a block diagram showing a video signal processing apparatus in a conventional SD-VCR.

FIG. 2 is a detailed view of the shuffle portion of FIG. 1.

3 is a block diagram showing a video signal processing apparatus according to the present invention.

4 illustrates a first embodiment of the shuffle unit 340 of FIG. 3.

5 illustrates a second embodiment of the shuffle unit 340 of FIG. 3.

In order to solve the above technical problem, in a video signal processing apparatus for decimating a video signal composed of luminance and color difference data, the input first color difference (Cr, Cb) data is delayed to a predetermined value and second color difference data. A first line memory for outputting a; A second line memory for outputting third color difference data by delaying the second color difference signal delayed in the first line memory to a predetermined value; A decimation unit configured to filter the first, second, and third color difference data and to decimate the filtered color difference data; And a shuffle unit configured to simultaneously input input luminance data and color difference data decimated by the decimation unit to perform shuffling, and the luminance data of the shuffle unit is not delayed. The video signal processing device is removed.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

3 is a block diagram illustrating a video signal decimation apparatus according to the present invention, and includes a first line memory 310 and a second line memory 320 for delaying two lines of color difference (Cr, Cb) data, and the first line memory. The decimation unit 330 decimates the color difference data delayed from the line memory 310 and the second line memory 320 and the input color difference data, and the color difference data and luminance Y outputted from the decimation unit 330. The shuffler 340 performs shuffling by inputting data.

As shown in FIG. 3, the input data is composed of three pieces of data of luminance and color difference (Cb, Cr) data, and the two color difference (Cr, Cb) data are signal processed on the same bus by doubling the data rate. In addition, the video color difference signals Cr and Cb are delayed by one line through the first line memory 310 and by one line delay through the second line memory 320. The decimation unit 330 performs low pass filtering using a 3-tap low pass filter using color difference data output from the first line memory 310 and the second line memory 320 and color difference data input to the system. And decimation. In this case, the luminance data is directly input to the shuffle unit 340 without being delayed. The shuffler 340 inputs the color difference (Cr, Cb) data output from the decimator 330 and the luminance signal that is not delayed to perform a shuffling operation.

4 illustrates a first embodiment of the shuffle unit 340 of FIG. 3. The shuffle memory 410, the address generator 420, the luminance data timing controller 430, the color difference data timing controller 440, and the luminance data timing are illustrated in FIG. The first switch SW1 switches a control signal generated by the controller 430 and the color difference data timing controller 440.

As illustrated in FIG. 4, the luminance data timing controller 430 generates a timing control signal in accordance with a phase in which luminance data is input to the shuffle unit 340, and the color difference data timing controller 440 is configured to output the color difference data to the shuffler ( A timing control signal is generated in accordance with the phase input to 340. The luminance data timing controller 430 and the chrominance data timing controller 440 operate independently. The first switch SW1 switches according to the type of data, that is, luminance data or color difference data. The address generator 420 selects a timing control signal generated by the luminance data timing controller 430 and the color difference data timing controller 440 by the first switch SW1 according to the type of data written to the shuffle unit 340. To generate an address. That is, the address generator 420 generates an address by referring to a timing control signal generated by connecting the first switch SW1 to the luminance data timing controller 430 when the luminance data is written to the shuffle memory 410. When the color difference data is written to the shuffle memory 410, an address is generated by referring to a timing control signal generated by connecting the first switch SW1 to the color difference data timing controller 440. The shuffle memory 410 writes data to an address generated by the address generator 420, and performs the shuffling operation by outputting the written data at a timing required by the system after shuffling.

FIG. 5 is a second embodiment of the shuffle unit 340 of FIG. 3, and includes a shuffle memory 510, an address generator 520, a timing controller 530, a delay 540, the timing controller 530, and a delay. It consists of a second switch (SW2) for switching the control signal generated in the unit 540.

As shown in Fig. 5, the timing controller 530 generates a timing control signal in accordance with a phase in which luminance data is input to the shuffle unit 3400. The delay 540 generates a timing control signal generated by the timing controller 530. In order to match the phase of the chrominance data with the decimated data, the delay of the timing control signal depends on the amount of the chrominance signal being delayed by the decimation unit 140. The address generator 520 generates the luminance data. When writing to the shuffle memory 510 The address is generated by referring to the timing control signal generated by connecting the second switch SW2 to the timing controller 530, and when writing the color difference data to the shuffle memory 510. The two switches SW2 are connected to the delay unit 540 to generate an address by the delayed timing control signal. Data is written to the address generated at 520, and the shuffled operation is performed by outputting the written data at a timing required by the system after shuffling.

As described above, according to the present invention, by implementing the decimation of the color difference signal without using the delay line memory for the delay of the luminance signal, it is possible to reduce the cost and power consumption of the system.

Claims (4)

A video signal processing apparatus for processing a video signal composed of luminance and chrominance data, A line memory configured to delay and output input color difference (Cr, Cb) data to a predetermined line; A decimation unit configured to filter the input color difference data and the color difference data delayed by the line memory and then decimate the color difference data into a predetermined type of color difference data; The timing control signal of the luminance and color difference data is selected according to the input luminance data and the data type corresponding to the color difference data decimated by the decimation unit, and the luminance and color difference data to be shuffled according to the selected timing control signal. And a shuffler for generating an address. The method of claim 1, wherein the shuffle portion A first timing controller for generating a timing control signal for the luminance data; A second timing controller for generating a timing control signal for the color difference data; An address generator for generating an address by referring to control signals generated by the first timing controller and the second timing controller selected according to the type of data input to the first and second memories; And a memory for storing the luminance and chrominance data by addressing generated by the address generator. The method of claim 1, wherein the shuffle portion A timing controller for generating a timing control signal for the luminance data; A delayer for delaying a control signal generated in the timing controller as much as the color difference data is delayed in the decimation unit; An address generator for generating an address by referring to a control signal generated by the timing controller when luminance data is written and by referring to a control signal generated by the delay device when color difference data is written; And a memory for storing the luminance and chrominance data by addressing generated by the address generator. 4. The video signal processing apparatus of claim 3, wherein the delay amount of the delay unit is an amount by which the color difference signal is delayed in the decimation unit.

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