JPH05128243A - Digital video signal special effect device - Google Patents

Digital video signal special effect device

Info

Publication number
JPH05128243A
JPH05128243A JP31367091A JP31367091A JPH05128243A JP H05128243 A JPH05128243 A JP H05128243A JP 31367091 A JP31367091 A JP 31367091A JP 31367091 A JP31367091 A JP 31367091A JP H05128243 A JPH05128243 A JP H05128243A
Authority
JP
Japan
Prior art keywords
output
read
signal
memory
video signal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP31367091A
Other languages
Japanese (ja)
Inventor
Takao Yamashiro
孝夫 山城
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Engineering Ltd
Original Assignee
NEC Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Engineering Ltd filed Critical NEC Engineering Ltd
Priority to JP31367091A priority Critical patent/JPH05128243A/en
Publication of JPH05128243A publication Critical patent/JPH05128243A/en
Pending legal-status Critical Current

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  • Complex Calculations (AREA)
  • Image Processing (AREA)
  • Processing Of Color Television Signals (AREA)
  • Processing Or Creating Images (AREA)

Abstract

PURPOSE:To operate an inserting processing without dividing the color signal of a digital video signal into color difference signals R-Y and B-Y. CONSTITUTION:An input signal inputted from an input terminal 1 is transmitted to a delay apparatus a switcher 4. The out of the delay apparatus transmitted to a delay 3 and the switcher 4. The outputs of the delay apparatus 3 and the switcher 4 are respectively transmitted to a storage part 6 and 7, and written according to a write-in address outputted from a write-in address generator 8. Signals read from the storage parts 6 and 7 according to a read-out address outputted from a read-out address generator 9 are transmitted to a delay apparatus 13 and a subtracter 12 of an interpolation circuit. The output of the subtracter 12 is multiplied by an interpolation coefficient outputted from a read only memory 17 by a multiplier 14. The output of the multiplier 14 is added to the output of the delay apparatus 13 by an adder 18, and outputted from an output terminal 19. Thus, a digital special effect device whose circuit constitution is.

Description

【発明の詳細な説明】Detailed Description of the Invention

【0001】[0001]

【産業上の利用分野】本発明は、ディジタル映像信号特
殊効果装置、特に記憶回路及び内挿回路の改良に関す
る。
BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital video signal special effect device, and more particularly to improvement of a memory circuit and an interpolation circuit.

【0002】[0002]

【従来の技術】従来、この種のディジタル特殊効果装置
の記憶回路及び内挿回路は、映像信号の色信号を色差信
号R−Y(以後CRと記述)とB−Y(以後CBと記述)
に分離して記憶し、内挿補間を行っていた。
Conventionally, the memory circuit and the interpolation circuit of this kind of digital special effects device, a color signal of a video signal (described as hereafter C R) color difference signals R-Y and B-Y (and hereinafter C B Description)
It was stored separately and interpolated.

【0003】[0003]

【発明が解決しようとする課題】前記ディジタル映像特
殊効果装置は、色信号をCR信号とCB信号とに分けて処
理していたため、色信号に対して二系統の回路を置く必
要があった。
Since the digital video special effect apparatus processes the color signal by dividing it into the C R signal and the C B signal, it is necessary to dispose two circuits for the color signal. It was

【0004】本発明の目的は、色信号を一系統の回路に
より処理できるようにしたディジタル映像信号特殊効果
装置を提供することにある。
An object of the present invention is to provide a digital video signal special effect device capable of processing a color signal by a circuit of one system.

【0005】[0005]

【課題を解決するための手段】前記目的を達成するた
め、本発明に係るディジタル映像信号特殊効果装置にお
いては、記憶回路と、内挿回路とを有するディジタル映
像信号特殊効果装置であって、記憶回路は、ディジタル
化された映像入力信号を映像信号サンプリングクロック
の1クロック分遅延させる遅延器を2個直列に並べ、各
々の入力信号を切換える切替器と、遅延器及び切替器の
出力を記憶する記憶器を有するものであり、内挿回路
は、二つの入力信号の内、一つの信号を遅延させる遅延
器と、二つの入力信号を減算する減算器と、減算器の出
力と読出専用メモリの出力を乗算する乗算器と、乗算器
の出力と遅延器の出力とを加算する加算器と、内挿係数
を映像信号の輝度信号と色信号の2つの色差信号の内挿
係数に変換し乗算器に送出する読出専用メモリとを有す
るものである。
In order to achieve the above object, in a digital video signal special effect device according to the present invention, there is provided a digital video signal special effect device having a memory circuit and an interpolation circuit. The circuit has two delay devices arranged in series, which delay the digitized video input signal by one clock of the video signal sampling clock, and stores a switching device for switching each input signal and the output of the delay device and the switching device. The interpolation circuit has a memory, and the interpolation circuit delays one of the two input signals, a subtractor that subtracts the two input signals, an output of the subtractor and a read-only memory. A multiplier that multiplies the output, an adder that adds the output of the multiplier and the output of the delay device, and an interpolation coefficient that is converted into an interpolation coefficient of two chrominance signals of a luminance signal and a color signal In a bowl Those having a read-only memory that out.

【0006】また、前記記憶回路は、記憶器の書込番地
を発生する書込番地発生器と、記憶器の読出番地及び内
挿回路に送る内挿係数を発生する読出番地発生器とを有
するものである。
Further, the memory circuit has a write address generator for generating a write address of the memory and a read address generator for generating a read address of the memory and an interpolation coefficient to be sent to the interpolation circuit. It is a thing.

【0007】[0007]

【作用】ディジタル映像信号の色信号を色差信号R−Y
とB−Yに分けずに内挿処理を行う。
The function of converting the color signal of the digital video signal into the color difference signal RY
Interpolation processing is performed without dividing into B and Y.

【0008】[0008]

【実施例】以下、本発明の一実施例を図により説明す
る。図1は、本発明の一実施例を示すブロック図であ
る。
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing an embodiment of the present invention.

【0009】図1において、本発明のディジタル映像特
殊効果装置における記憶回路及び内挿回路は、入力信号
を1クロック分遅らせる遅延器2,3を2個直列に並べ
各々の入力信号を切換えるための切替器4と、遅延器3
及び切替器4の出力を記憶する記憶器6,7と、記憶器
6,7の書込番地を発生する書込番地発生器8と、記憶
器6,7の読出番地及び内挿回路に送る内挿係数を発生
する読出番地発生器9と、二つの入力信号の内一つの信
号を遅延させる遅延器13と、二つの入力信号を減算す
る減算器12と、減算器12の出力と読出専用メモリ1
7の出力を乗算する乗算器14と、乗算器14の出力と
遅延器13の出力とを加算する加算器18と、内挿係数
を映像信号の輝度信号と色信号の2つの色差信号の内挿
係数に変換し乗算器14に送出する読出専用メモリ17
とを有する。
In FIG. 1, the storage circuit and the interpolation circuit in the digital video special effect apparatus of the present invention are arranged in series with two delay units 2 and 3 for delaying the input signal by one clock to switch each input signal. Switching device 4 and delay device 3
And the outputs of the switch 4 to the storage devices 6 and 7, the write address generator 8 that generates the write addresses of the storage devices 6 and 7, and the read addresses and the interpolation circuits of the storage devices 6 and 7. A read address generator 9 for generating an interpolation coefficient, a delay device 13 for delaying one of the two input signals, a subtracter 12 for subtracting the two input signals, an output of the subtractor 12 and read-only Memory 1
7 for multiplying the output of 7 and an adder 18 for adding the output of the multiplier 14 and the output of the delay device 13 and the interpolation coefficient between the two color difference signals of the luminance signal and the color signal of the video signal. Read-only memory 17 for converting into an insertion coefficient and sending it to the multiplier 14.
Have and.

【0010】入力端子1から入力されるディジタル信号
は、遅延器2と切替器4に送られる。遅延器2の出力
は、遅延器3と切替器4に送られる。切替器4では輝度
信号(以後Yと記述)と色信号(以後Cと記述)を切換
え信号(入力端子5より入力)によって、Yの場合は遅
延器2の出力側、Cの場合は遅延器2の入力側を選択す
る。これは、後の内挿回路で2つのデータで内挿する
時、Yの場合には2クロック間のデータで内挿を行う
が、Cの場合、1クロック毎にデータがCR,CB
R,CB…と変化するため、同種類の信号の内挿を行う
には、2クロックおきのデータを使用する必要があるか
らである。
The digital signal input from the input terminal 1 is sent to the delay device 2 and the switching device 4. The output of the delay device 2 is sent to the delay device 3 and the switching device 4. In the switching device 4, a luminance signal (hereinafter referred to as Y) and a chrominance signal (hereinafter referred to as C) are switched by a switching signal (input from the input terminal 5), when Y, the output side of the delay device 2, and when C, the delay device. Select the input side of 2. This is because when interpolating two data interpolation circuit after, performs the interpolation in the data between the two clocks in the case of Y, the case of C, 1 data per clock C R, C B
To change C R, C B ... and, to do the interpolation of the same type of signal, it is necessary to use two clocks every data.

【0011】遅延器3と切替器4の出力は、書込番地発
生器8に従って、記憶器6,7に記憶される。記憶器に
書かれた信号は読出番地発生器9から出力される読出番
地に従って読出され内挿回路へ送られる。
The outputs of the delay device 3 and the switching device 4 are stored in the storage devices 6 and 7 according to the write address generator 8. The signal written in the memory is read according to the read address output from the read address generator 9 and sent to the interpolation circuit.

【0012】内挿回路の入力端子10から入力される信
号Aは、遅延器13と減算器12に送られる。入力端子
11から入力される信号Bは減算器12に送られ、そこ
で信号Aとの間でB−Aが行われる。
The signal A input from the input terminal 10 of the interpolation circuit is sent to the delay unit 13 and the subtractor 12. The signal B input from the input terminal 11 is sent to the subtractor 12, where BA is performed with the signal A.

【0013】減算器13の出力は乗算器14に送られ、
読出専用メモリ17からの信号kと乗算されてk(B−
A)が出力される。読出専用メモリからの信号kは読出
番地発生器9からの信号と、入力端子16に入力される
Y−C切替信号により、Y用の内挿係数あるいはC用の
内挿係数を出力する。
The output of the subtractor 13 is sent to the multiplier 14,
The signal k from the read-only memory 17 is multiplied by k (B-
A) is output. The signal k from the read-only memory outputs the Y interpolation coefficient or the C interpolation coefficient according to the signal from the read address generator 9 and the Y-C switching signal input to the input terminal 16.

【0014】C用の内挿係数は、さらに入力端子20に
入力されるCR,CB切替信号により、CR用の内挿係数
とCB用の内挿係数に切替えられる。
[0014] interpolation coefficients for C is, C R is further input to the input terminal 20, by C B switch signal is switched to the interpolation coefficients of the interpolation coefficients and for C B for C R.

【0015】上記の方法と前述のC信号を記憶器へ書込
む方法により、C信号をCR,CB信号に分離せず、Yと
同様の回路で処理することができる。乗算器14と遅延
器13の出力は、加算器18で加算され、A信号とB信
号を内挿した信号A+k(B−A)が出力端子19に出
力される。
By the above method and the above-mentioned method of writing the C signal in the memory, the C signal can be processed by the same circuit as Y without being separated into C R and C B signals. The outputs of the multiplier 14 and the delay unit 13 are added by the adder 18, and the signal A + k (BA) obtained by interpolating the A signal and the B signal is output to the output terminal 19.

【0016】[0016]

【発明の効果】以上説明したように本発明は、Y−C切
替器,読出専用メモリを組合せることにより、映像信号
の色信号を輝度信号と同様に、一系統の回路で処理する
ことができる。
As described above, according to the present invention, by combining the Y-C switch and the read-only memory, the chrominance signal of the video signal can be processed by one system of circuit like the luminance signal. it can.

【図面の簡単な説明】[Brief description of drawings]

【図1】本発明の一実施例を示すブロック図である。FIG. 1 is a block diagram showing an embodiment of the present invention.

【符号の説明】[Explanation of symbols]

2,3 遅延器 6,7 記憶器 8 書込番地発生器 9 読出番地発生器 12 減算器 13 遅延器 14 乗算器 17 読出専用メモリ 18 加算器 2,3 Delay device 6,7 Memory device 8 Write address generator 9 Read address generator 12 Subtractor 13 Delay device 14 Multiplier 17 Read only memory 18 Adder

Claims (2)

【特許請求の範囲】[Claims] 【請求項1】 記憶回路と、内挿回路とを有するディジ
タル映像信号特殊効果装置であって、 記憶回路は、ディジタル化された映像入力信号を映像信
号サンプリングクロックの1クロック分遅延させる遅延
器を2個直列に並べ、各々の入力信号を切換える切替器
と、遅延器及び切替器の出力を記憶する記憶器を有する
ものであり、 内挿回路は、二つの入力信号の内、一つの信号を遅延さ
せる遅延器と、二つの入力信号を減算する減算器と、減
算器の出力と読出専用メモリの出力を乗算する乗算器
と、乗算器の出力と遅延器の出力とを加算する加算器
と、内挿係数を映像信号の輝度信号と色信号の2つの色
差信号の内挿係数に変換し乗算器に送出する読出専用メ
モリとを有するものであることを特徴とするディジタル
映像信号特殊効果装置。
1. A digital video signal special effect device having a storage circuit and an interpolation circuit, wherein the storage circuit delays the digitized video input signal by one clock of a video signal sampling clock. It has two switching devices arranged in series and switching each input signal, and a storage device that stores the output of the delay device and the switching device. The interpolation circuit stores one of the two input signals. A delay device that delays, a subtracter that subtracts two input signals, a multiplier that multiplies the output of the subtractor and the output of the read-only memory, and an adder that adds the output of the multiplier and the output of the delay device. And a read-only memory for converting an interpolation coefficient into an interpolation coefficient of two color difference signals of a video signal and a color signal and sending the read coefficient to a multiplier. ..
【請求項2】 前記記憶回路は、記憶器の書込番地を発
生する書込番地発生器と、記憶器の読出番地及び内挿回
路に送る内挿係数を発生する読出番地発生器とを有する
ものであることを特徴とする請求項1に記載のディジタ
ル映像信号特殊効果装置。
2. The memory circuit includes a write address generator for generating a write address of the memory device, and a read address generator for generating a read address of the memory device and an interpolation coefficient to be sent to an interpolation circuit. The digital video signal special effect device according to claim 1, wherein the special effect device is a digital video signal special effect device.
JP31367091A 1991-10-31 1991-10-31 Digital video signal special effect device Pending JPH05128243A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP31367091A JPH05128243A (en) 1991-10-31 1991-10-31 Digital video signal special effect device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP31367091A JPH05128243A (en) 1991-10-31 1991-10-31 Digital video signal special effect device

Publications (1)

Publication Number Publication Date
JPH05128243A true JPH05128243A (en) 1993-05-25

Family

ID=18044101

Family Applications (1)

Application Number Title Priority Date Filing Date
JP31367091A Pending JPH05128243A (en) 1991-10-31 1991-10-31 Digital video signal special effect device

Country Status (1)

Country Link
JP (1) JPH05128243A (en)

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