JP3822920B2 - Video signal processing device - Google Patents

Description

[0001]
[Industrial application fields]
The present invention relates to a video signal processing apparatus suitable for use in, for example, a camera-integrated VTR.
[0002]
[Prior art]
Conventionally, in a camera-integrated VTR for consumer use, digital signal processing has been performed in a camera system for multifunctional functions such as adaptive image quality control, electronic zoom using a memory, and camera shake correction.
Also in the VTR system, digitalization of signal processing is being promoted in order to improve image quality such as time base correction (TBC) using a memory.
[0003]
In this way, the signal processing system of the camera-integrated VTR in which the processing of the camera signal (imaging signal) and the video signal is digitized is configured as shown in FIG. 3, for example.
[0004]
In FIG. 3, reference numeral 10 denotes a camera signal processing system which is provided before and after the camera signal processing circuit 11, the memory 12, the A / D converter 13, and the A / D converter 13, and selects and distributes signals. Switch switches 14 and 15 for use. The memory 12 is a field memory, for example.
[0005]
The switch circuit 14 includes a reproduced video signal SPB from a VTR system (not shown), a video signal SLN from a line input terminal, and an imaging signal SCM from a camera system (not shown) provided with a CCD type imaging device. And a mode signal SMD from a system control circuit (not shown) is supplied as a switching control signal. The three types of analog video signals are alternatively supplied from the switch circuit 14 to the A / D converter 13 in accordance with the mode of the camera-integrated VTR, and each corresponding digital video signal, that is, the reproduced video signal DPB, It is converted into a line video signal DLN and a camera signal (imaging signal) DCM.
[0006]
Among these, the camera signal DCM is supplied to the camera signal processing circuit 11 through the switch circuit 15, and the luminance signal and the color signal are separated and subjected to signal processing such as gamma correction and white balance, and then the memory 12. To be subjected to processing such as electronic zoom.
[0007]
A video signal processing system 20 includes a video signal processing circuit 21, interfaces (I / F) 22, 23, and 24 connected to the signal processing circuit 21, and D / A converters 25 and 26. And is formed as a single integrated circuit (IC). Note that the mode signal SMD is also supplied to the video signal processing system 20 as a control signal.
[0008]
A reproduction video signal DPB and a line video signal DLN are supplied to the first interface 22 through the switch circuit 15. The camera signal DCM is supplied to the second interface 23 through the memory 12. The memory 12 is connected to the third interface 24. That is, the second interface 23 is a camera interface, and the third interface 24 is a memory interface.
[0009]
The digital video signal from the video signal processing circuit 21 is supplied to the video head 28 through the D / A converter 25 and the recording amplifier 27. The digital video signal from the video signal processing circuit 21 is also supplied through a D / A converter 26 to a display monitor 29 which is also a liquid crystal display device and serves as a finder.
[0010]
In the camera recording mode, the camera signal DCM from the memory 12 is supplied to the video signal processing circuit 21 through the interface 24 and subjected to necessary recording signal processing such as emphasis, frequency modulation, low-frequency conversion, and the like. It is converted into an analog video signal by the converter 25, supplied to the video head 28 through the recording amplifier 27, and recorded on a tape (not shown).
[0011]
The video signal for monitoring from the video signal processing circuit 21 is converted into an analog video signal by the D / A converter 26 and supplied to the monitor 29, and the video of the subject is displayed on the screen.
[0012]
In the line recording mode, the line video signal DLN from the switch circuit 15 is supplied to the video signal processing circuit 21 through the interface 22, and a recording signal and a monitoring signal are formed as described above.
[0013]
In the playback mode, the playback video signal DPB from the switch circuit 15 is supplied to the video signal processing circuit 21 through the interface 22 so that only a monitor signal is formed. The memory 12 performs TBC processing, chroma noise reduction processing using field correlation, and the like.
[0014]
Among the digital video signals as described above, the camera signal DCM is different from the reproduction video signal DPB and the line video signal DLN, and communication (transmission processing) is performed by separating the synchronization signal components. Although omitted, the synchronization signal from the synchronization signal generation circuit is mixed under the control of the system control circuit.
[0015]
Further, for example, as shown in FIG. 4, the camera signal DCM, the playback video signal DPB, and the line video signal DLN have different signal widths, that is, the number of bits of quantization, and the quantization level of each signal. For example, when the number of bits for quantization of the camera signal is 8 bits, the quantization level is 70 for the black level, 230 for the white peak level, and 6 for the peak value (sync chip) level of the synchronization signal. On the other hand, when the number of bits of quantization of the video signal is 10, the quantization level is assigned 285 for the black level, 855 for the white peak, and 57 for the sync chip level.
[0016]
[Problems to be solved by the invention]
In the conventional camera-integrated VTR as described above, the digital signal input / output in the video signal processing system 20 includes the reproduction video signal DPB or the line video signal DLN, the camera signal DCM from the camera signal processing circuit 11, and There are four types of digital signals: input signals from the memory 12 and output signals to the memory 12.
[0017]
If the signal widths of these digital signals are all 10 bits, for example, the video signal processing system 20 requires as many as 40 pins for input and output, thereby reducing the cost and size of the IC. There was a problem of preventing.
[0018]
In view of the above, an object of the present invention is to provide a video signal processing apparatus capable of reducing the number of digital signal inputs and outputs in a video signal processing system.
[0019]
[Means for Solving the Problems]
In order to solve the above problems, a video signal processing apparatus according to the present invention provides:
A video signal processing circuit; and a memory connected to the video signal processing circuit through a memory interface, wherein the digital imaging signal of the first bit and the digital video signal of the second bit number different from the first bit number Is selectively written into the memory, and a predetermined process corresponding to the digital imaging signal or the digital video signal is performed, and the digital imaging signal or the digital video signal subjected to the predetermined process Is a video signal processing device supplied to the video signal processing circuit through the memory interface,
The digital video signal is written to the memory through the memory interface, and the digital video signal read from the memory is supplied to the video signal processing circuit through the memory interface,
The digital imaging signal is written to the memory without going through the memory interface, and the digital imaging signal read from the memory is supplied to the video signal processing circuit through the memory interface,
The memory interface is
Synchronization signal separating means for separating a synchronization signal from the digital video signal;
First gain adjusting means for gain adjustment of the quantization level of the digital video signal from which the synchronization signal has been separated, and first level shift means for level shifting the quantization level of the output of the first gain adjustment means A first quantized bit number conversion means for converting the number of bits of the digital video signal from the second number of bits to the first number of bits and generating a signal to be written to the memory ;
Second level shift means for level-shifting the quantization level of the digital video signal or digital imaging signal having the first number of quantization bits read from the memory , and output of the second level shift means Second gain adjusting means for adjusting the gain of the quantization level of the second image, and converting the number of bits of the digital video signal or the digital imaging signal from the first number of bits to the second number of bits . Quantization bit number conversion means;
Synchronization signal mixing means for mixing a synchronization signal with the output signal of the second quantization bit number conversion means;
Have
The digital imaging signal or digital video signal from the synchronization signal mixing means is supplied to the video signal processing circuit .
[0020]
[Action]
According to such a configuration, it is not necessary to prepare a dedicated interface for the digital imaging signal DCM, and the number of digital signal inputs and outputs of the video signal processing device is reduced.
[0021]
【Example】
An embodiment of a video signal processing apparatus according to the present invention will be described below with reference to FIGS.
[0022]
FIG. 1 shows the overall configuration of one embodiment of the present invention, and FIG. In these figures, the same reference numerals are given to the portions corresponding to FIG.
[0023]
In FIG. 1, the video signal processing system 20C is provided with a memory interface 24C (hereinafter referred to as a shared interface) in which the memory interface and the camera interface are shared, and the dedicated camera interface 23 as shown in FIG. 3 is deleted. Is done.
[0024]
The camera signal DCM through the camera signal processing circuit 11 is supplied to the memory 12 and the shared interface 24C, and the input / output of the memory 12 is connected to the shared interface 24C.
In the embodiment of FIG. 1, the output terminal of the shared interface 24C is bidirectional.
The rest of the configuration is the same as in FIG.
[0025]
In order to realize the sharing of the memory interface and the camera interface as described above, in this embodiment, the sharing interface 24C is configured as shown in FIG.
[0026]
That is, the common interface 24C includes a synchronization signal separation circuit 241, a first gain adjustment circuit 242, and a first level shift circuit 243 that are connected in cascade, and a second level shift circuit 244 that is also connected in cascade. The second gain adjustment circuit 245 and the synchronization signal mixing circuit 246 and two selection switch circuits 247 and 248 are included.
[0027]
Both gain adjustment circuits 242 and 245 and both level shift circuits 243 and 244 are constituted by, for example, a ROM table, and have opposite characteristics as described later.
[0028]
In FIG. 2, 21t is a signal main line of the video signal processing system 20C, and the signal DLN on the main line 21t passes through the synchronization signal separation circuit 241 to the level shift circuit 243 and is connected to the input side a of the memory 12 and the switch circuit 247. And a signal read from the memory 12 is supplied to the input terminal b side of the switch circuit 247. The memory 12 is also supplied with the camera signal DCM as described above.
[0029]
The output signal of the switch circuit 247 is supplied to the input terminal b side of the switch circuit 248 through the level shift circuit 244 to the synchronization signal mixing circuit 246. A signal of the main line 21t is supplied to the input terminal a side of the switch circuit 248.
[0030]
A synchronization signal from the synchronization signal generation circuit 31 is supplied to the synchronization signal mixing circuit 246 under the control of the system control circuit (microprocessor) 30. The selection switch circuits 247 and 248 are supplied with a switching control signal from the system control circuit 30 and are normally connected as shown in the figure.
[0031]
The output of the switch circuit 248 is supplied to the video signal processing circuit 21 through the fade circuit 41 and the character insertion circuit 42, for example. A control signal is also supplied from the system control circuit 30 to the fade circuit 41 and the character insertion circuit 42.
[0032]
Next, the operation of one embodiment of the present invention will be described.
[0033]
As shown in FIG. 4, the camera signal DCM, the playback video signal DPB, and the line video signal DLN differ in the number of quantization bits and quantization level of each signal, and the camera signal quantization level QLCM Between the reproduction video signal quantization level QLPB (= line video signal QLLN),
QLCM = k · QLPB-C
The following relationship is established.
[0034]
In the numerical example of FIG.
k = 1.125 / 4 = 0.28125
C = 10
It becomes.
[0035]
Therefore, the first and second gain adjustment circuits 242 and 245 perform multiplication processing and division processing by the predetermined coefficient k, respectively, and the first and second level shift circuits 243 and 244 respectively have the same constants. C subtraction processing and addition processing are performed.
[0036]
In the line recording mode and the reproduction mode, the reproduction video signal DPB or the line video signal DLN is separated in the synchronization signal separation circuit 241 after the synchronization signal component is separated, and then in the gain adjustment circuit 242 and the level shift circuit 243 The signal is converted into a quantization level equivalent to the camera signal DCM, supplied to the memory 12, and predetermined signal processing is performed.
[0037]
After the signal processing in the memory 12, the reproduction video signal DPB or the line video signal DLN is returned to the original quantization level in the level shift circuit 244 and the gain adjustment circuit 245, and then the synchronization signal mixing circuit. In 246, the synchronizing signal components are mixed and returned to the original reproduced video signal DPB or line video signal DLN and input to the video signal processing circuit 21.
[0038]
In the camera recording mode, the camera signal DCM from the memory 12 is converted into a quantized level of the video signal through the level shift circuit 244 to the synchronization signal mixing circuit 246 of the common interface 24C, and from the memory 12 A synchronization signal component is mixed with the camera signal DCM.
[0039]
When the memory processing is not performed in the line recording mode or the reproduction mode, the switch circuit 248 is switched to a state opposite to that shown in the figure, and the reproduction video signal DPB and the line video signal DLN on the main line 21t are shared. The video signal is input to the video signal processing circuit 21 without going through the conversion interface 24C.
[0040]
When the memory 12 is not mounted on the device, the switch circuit 247 is switched to the opposite state to that shown in the figure, and the signal DCM from the camera signal processing circuit 11 passes through the level shift circuit 244 to the synchronization signal mixing circuit 246. While being converted into a quantization level of the video signal, a synchronizing signal component is mixed with the signal DCM from the camera signal processing circuit 11.
[0041]
As described above, in this embodiment, the playback video signal DPB and the line video signal DLN are converted to the same level and gain as the camera signal DCM on the memory 12 and subjected to predetermined processing.
[0042]
As described above, since the number of bits of the camera signal DCM is smaller than that of the reproduced video signal DPB and the line video signal DLN, in this embodiment, the quantization level of the camera signal DCM is set to the video signals DPB and DLN. Compared with the case of conversion to the quantization level, the capacity of the memory 12 can be reduced, and the cost from this aspect can be reduced.
[0043]
In this embodiment, the sync signal separation circuit 241 to the gain adjustment circuit 242 convert the reproduction video signal DPB and the line video signal DLN supplied to the memory 12 to the quantization level of the camera signal DCM and adjust the gain. By converting the camera signal DCM supplied from the memory 12 to the video signal processing circuit 21 to the quantization level of the reproduction video signal DPB or the line video signal DLN by the circuits 245 to 246, the memory interface and Sharing with the camera interface can be realized, the number of digital signal inputs and outputs can be reduced, and the cost and size of the IC can be reduced.
[0044]
In this embodiment, as described above, since the output terminal of the common interface 24C is bidirectional, even when the memory 12 is not mounted, the main wiring board for mounting the memory 12 can be used in common. it can.
[0045]
Note that the fade circuit 41 and the character insertion circuit 42 and the delay time adjustment circuit for the luminance signal and the color signal, which are not shown, can be used in common in the video signal processing and the camera signal processing. By providing such a circuit after the common interface 24C, the circuit for recording the line signal SLN and the camera signal SCM can be shared, and the circuit scale of the camera signal processing circuit 11 can be increased. Can be small.
[0046]
【The invention's effect】
As described above, according to the present invention, between the video signal processing circuit and the memory, the first quantization level converting means for converting the digital video signal into the quantization level of the digital imaging signal, and the digital imaging Since the signal is connected through the memory interface having the second quantization level converting means for converting the signal to the quantization level of the digital video signal, the digital imaging signal is supplied to the video signal processing circuit through the memory interface. In addition, the digital video signal can be exchanged between the video signal processing circuit and the memory through the memory interface, and a dedicated interface is not required for the digital imaging signal. The number can be reduced.
[0047]
Further, since the output terminal of the memory interface is bidirectional, the main wiring board for mounting the memory can be used in common even when the memory is not mounted.
[Brief description of the drawings]
FIG. 1 is a block diagram showing the overall configuration of an embodiment of a video signal processing apparatus according to the present invention.
FIG. 2 is a block diagram showing a configuration of a main part of one embodiment of the present invention.
FIG. 3 is a block diagram illustrating a configuration example of a conventional video signal processing apparatus.
FIG. 4 is a diagram for explaining the present invention.
[Explanation of symbols]
11 Camera signal processing circuit 12 Memory 21 Video signal processing circuit 24C Shared interface 241 Synchronization signal separation circuit 242, 245 Gain adjustment circuit 243, 244 Level shift circuit 246 Synchronization signal mixing circuit SCM, DCM Camera signal (imaging signal)
SLN, DLN Line video signal SPB, DPB Playback video signal

Claims (2)

A video signal processing circuit; and a memory connected to the video signal processing circuit through a memory interface, wherein the digital imaging signal of the first bit and the digital video signal of the second number of bits different from the first number of bits Is selectively written into the memory, and a predetermined process corresponding to the digital imaging signal or the digital video signal is performed, and the digital imaging signal or the digital video signal subjected to the predetermined process Is a video signal processing device supplied to the video signal processing circuit through the memory interface,
The digital video signal is written to the memory through the memory interface, and the digital video signal read from the memory is supplied to the video signal processing circuit through the memory interface,
The digital imaging signal is written to the memory without going through the memory interface, and the digital imaging signal read from the memory is supplied to the video signal processing circuit through the memory interface,
The memory interface is
Synchronization signal separating means for separating a synchronization signal from the digital video signal;
First gain adjusting means for gain adjustment of the quantization level of the digital video signal from which the synchronization signal has been separated, and first level shift means for level shifting the quantization level of the output of the first gain adjustment means A first quantized bit number conversion means for converting the number of bits of the digital video signal from the second number of bits to the first number of bits and generating a signal to be written to the memory ;
Second level shift means for level-shifting the quantization level of the digital video signal or digital imaging signal having the first number of quantization bits read from the memory , and output of the second level shift means Second gain adjusting means for adjusting the gain of the quantization level of the second image, and converting the number of bits of the digital video signal or the digital imaging signal from the first number of bits to the second number of bits . Quantization bit number conversion means;
Synchronization signal mixing means for mixing a synchronization signal with the output signal of the second quantization bit number conversion means;
Have
The video signal processing apparatus , wherein the digital imaging signal or digital video signal from the synchronization signal mixing means is supplied to the video signal processing circuit . The video signal processing apparatus according to claim 1, wherein a processing circuit common to the digital video signal and the digital imaging signal is inserted in a path from the memory interface to the video signal processing circuit.

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