JPH09307915A - Signal processing circuit for single ccd color camera - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress the circuit scale to be increased by sharing a 1H delay line at the time of reducing the screen and of not reducing it. SOLUTION: In the case of using a signal processing circuit of the signal CCD color camera to which a signal from a signal CCD solid-state image pickup element is outputted respectively by two lines each, a 1H delay lien for arithmetic operation of a luminance signal Y in the vertical direction outputted from the signal processing circuit 14 being a 1H delay line 12 in two 1H delay lines 11, 12 for color separation of the solid-state image pickup element is used in common to reduce the circuit scale.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a signal processing circuit for a single plate color camera.

[0002]

2. Description of the Related Art FIG. 5 shows a signal processing block diagram of a conventional single-chip color camera, and FIG. 6 shows a CCD (solid-state image sensor) in which two lines are repeatedly arranged in the vertical direction used at that time. An example of the color filter array will be described.

The output signal Ho from the CCD input to the input terminal IN is input to the 1H delay line 11 and the 1H delay line 1
The output H1 of 1 is input to the other 1H delay line 12. The output Ho and the output H2 of the 1H delay line 12 are input to an adder 13, and the addition average output thereof is input to a signal processing circuit 14 including a luminance signal processing, a color signal processing, and a contour correction processing circuit. On the other hand, the output H1 is also input to the signal processing circuit 14. The signal processing circuit 13 outputs signals Ho and H for three lines.
The color signal C and the luminance signal Y are generated from the first and the second H2.

Now, consider a case where an image is reduced at least in the vertical direction as shown in FIG. If the line information is thinned out in accordance with the reduction ratio, it is necessary to narrow the band in advance at least for the luminance signal Y in the vertical direction through the LPF 15 in order to suppress the aliasing distortion. Therefore, it is necessary to further use at least one 1H delay line 16. The filtering process is performed by vertically operating on two lines of the luminance signal Y and the output of the 1H delay line 16. The output signal is sub-sampled by the reduction circuit 19 based on the control signal CS also generated from the reduction control circuit 18 via the switch 17 switched to the contact b side by the switching signal SS from the reduction control circuit 18. According to the reduction circuit 1
The luminance signal Y reduced from the output of 9 is obtained at the output terminal Yout.

As for the chrominance signal C, similarly to the luminance signal Y, by subsampling the reduction circuit 20 based on the control signal CS, the color signal C reduced from the output of the reduction circuit 20 is output to the output terminal Cout. obtain.

When not reduced, the contact point a of the switch 17
And the control circuit CS is stopped and the reduction circuit 1 is selected.
The luminance signal Y that has passed through 9 is obtained at the output terminal Yout. Regarding the color signal C, the color signal C that has passed through the reduction circuit 20 is obtained at the output terminal Cout.

FIG. 8 shows another conventional example, and the same components as those in FIG. 5 are designated by the same reference numerals. This conventional example
This is an example in which the band in the vertical direction is limited from FIG. 5 in order to further suppress the aliasing distortion in the vertical direction when the reduction ratio in the vertical direction is large.

FIG. 5 shows an operation [(1+
Z ^-H) / 2] but by performs processing for bandwidth, 8 calculation from three lines ^{[(1 + Z -H) 2} /4]
The bandwidth limitation processing is performed by the. However, Z ^-H
Is the Z function in the vertical direction.

In FIG. 8, the color signal C output from the signal processing circuit 14 is controlled by the reduction control circuit 18.
Is supplied to the reduction circuit 20 via the LPF 21 at the time of reduction and the luminance signal Y is reduced at the LPF.
A switch 24 for supplying the reduction circuit 19 via 23 is provided. The LPFs 21 and 23 are for suppressing aliasing distortion of the color and luminance signals C and Y by thinning out in the horizontal direction. When not reducing, LPF 21,2
Thru 3

Further, for filtering three lines, two 1H delay lines are required. Here, subsampling is performed using the horizontal subsampling circuit 25.
1H by decimating the horizontal information and halving it
The delay line 16 is equivalent to two 1H delay lines. That is, the frequency of the clock signal CK of the 1H delay line 16 is driven at a frequency obtained by dividing the frequency of the 1H delay line 16 in FIG. Therefore, a delay line of 2H can be realized with the same memory capacity.

As described above, in FIGS. 5 and 8 of the related art, the 1H delay line for applying the LPF in the vertical direction when the switch 17 is switched to the reduction mode in order to suppress the signal aliasing distortion due to the reduction. 16 was needed.

[0012]

In the signal processing circuit of the conventional single-chip color camera described above, the LPF is applied in the vertical direction as a means for suppressing the aliasing distortion due to the reduction, so that the 1H delay line is required, and the circuit scale is large. To increase.

An object of the present invention is to suppress an increase in circuit scale by sharing a 1H delay line.

[0014]

In order to solve the above-mentioned problems, in the signal processing circuit of a single-chip color camera in which the signal of the single-plate solid-state image pickup device is repeatedly output every two lines, the output of the solid-state image pickup device is changed. A first 1H delay line for input and a second 1H for inputting the output of the first 1H delay line.
H delay line, first arithmetic mean for averaging the input of the first 1H delay line and output of the second 1H delay line, the first 1H delay line output and the first addition A first color separation circuit for performing color separation from the three lines of the averaging means output;
A first brightness processing circuit separate from the first color separation circuit
The second 1H delay line is used for the first vertical arithmetic circuit for the luminance signal when the output luminance signal of the above is calculated by two or more lines, and the first color separation circuit is used for the first 1H delay. It is characterized by further comprising first switching means for switching so as to perform color separation from two lines of input and output of the line.

By such means, one of the two 1H delay lines for obtaining the three lines of color separation is used for the vertical LPF for carrying out the reduction in the vertical direction.
At this time, color separation is a two-line process. An adder that takes the arithmetic mean of the output signal of the CCD and the signal obtained by delaying it by 2H is used for the calculation of the vertical LPF for performing the reduction in the vertical direction. Therefore, the delay line for vertical reduction can be used also as the delay line for non-reduction, so that the circuit scale can be reduced.

[0016]

Embodiments of the present invention will be described below in detail with reference to the drawings. FIG. 1 is a circuit configuration diagram for explaining a first embodiment of the present invention. In this embodiment, the 1H delay line 1 shown in FIG.
6 is removed, and switches 101 and 102 are added so that it also serves as the 1H delay line 12. The same components as those in FIG.

In FIG. 1, the output H1 of the 1H delay line 11
Is input to one side of the switch 101, and the luminance signal Y of the signal processing circuit 14 is input to the other side of the switch 101. The output of the switch 101 is input to the 1H delay line 12. The output of the adder 13 is input to one of the switches 102, and CC
The output signal Ho of D is input to the other of the switches 102.
The output of the switch 102 is input to the signal processing circuit 14. The switches 101 and 102 are switched by a switching signal output from the reduction control circuit 18. When the switching signal SS of the reduction control circuit 18 is a, the vertical direction is controlled to a non-reduction state, and when the switching signal SS is b, it is controlled to a reduction state. The above configuration is the part different from FIG.

Now, a case will be described in which the switching signal SS of the reduction control circuit 18 selects the contacts a on the side of the switches 101, 102, 17 and the image is not reduced.
The output signal Ho of the CCD input to the input terminal IN is 1
The H1 delayed by 1H is output as an output via the H delay line 11. This H1 is the switch 1 that has been switched to the a side
Input to the 1H delay line 12 via 01. Here, the output H2 delayed by 1H is obtained and input to one of the adders 13. The adder 13 outputs an output obtained by adding and averaging the output Ho input to the other input. This arithmetic mean output is input to the signal processing circuit 14 having a function of performing the luminance signal processing, the color signal processing, and the contour correction processing via the switch 102 switched to the a side. On the other hand, the output H1 is also input to the signal processing circuit 14. The signal processing circuit 13 generates a color signal C and a luminance signal Y based on the signals Ho, H1, and H2 for three lines.

For the color signal C and the luminance signal Y output from the signal processing circuit 14, the reduction control circuit 1 is used.
Since the control signal CS from 8 does not sub-sample the reduction circuits 20, 19, the reduction circuits 20, 1
9 is output through.

Next, the case where the switching signal SS of the reduction control circuit 18 selects the contact on the b side of the switches 101, 102, 17 to reduce the screen will be described. C
The output signal Ho of the CD is input to the signal processing circuit 14 via the switch 102 switched to the b side. Also, C
The output signal Ho of the CD outputs the output H1 delayed by 1H via the 1H delay line 11. The output H1 is input to the signal processing circuit 14.

Color signal C output from the signal processing circuit 14
Sub-samples the reduction circuit 20 based on the control signal CS from the reduction control circuit 18. As a result, the color signal C reduced from the output of the reduction circuit 20 is obtained at the output terminal Cout.

The brightness signal Y output from the signal processing circuit 14 is filtered by vertically calculating the brightness signal Y and the output of the 1H delay line 12 through the switch 101 switched to the b side. Perform processing. Then, the luminance signal passing through the 1H delay line 12 and the luminance signal not passing through it are passed through the LPF 15 in the vertical direction to narrow the band and suppress aliasing distortion. The output of the LPF 15 sub-samples the reduction circuit 19 based on the control signal CS from the reduction control circuit 18 via the switch 17 switched to the b side, whereby the luminance signal Y reduced from the output of the reduction circuit 19 is obtained. At the output terminal Yout.

As a result, when the vertical reduction is performed, the input to the signal processing circuit 14 is only the signals of the two lines Ho and H1, and the 1H delay line 12 is used for the vertical calculation of the luminance signal Y. used. At this time, since at least the color signal C output from the signal processing circuit 14 is processed from the conventional 3-line to 2-line processing, the image of the diagonal line becomes coarse and deteriorates, but the image is deteriorated because it is reduced in the vertical direction. Is inconspicuous.

In this embodiment, when the line information is thinned and reduced according to the reduction ratio, in order to suppress the aliasing distortion, at least the luminance signal Y is narrowed in the band through the LPF in the vertical direction via the 1H delay line. Since the 1H delay line of 1 is shared with the 1H delay line that delays the signal Ho from the CCD for signal processing, the circuit scale can be reduced.

FIG. 2 is a circuit configuration diagram for explaining the second embodiment of the present invention. In this embodiment, the luminance signal Y at the time of reduction in the vertical direction of the embodiment of FIG.
The LPF 15 that passes through is removed, and the adder 13 is also used.

That is, 1 is input to one input of the adder 13.
The output of the H delay line 12 is connected, and the output of the switch 201 is connected to the other input. The contact a of the switch 201 is
Input terminal I to which the signal Ho output from the CCD is input
N is connected, and the contact b is connected to the luminance signal Y from the signal processing circuit 14.
Is connected to the line that outputs. The output of the adder 13 is
The contact a of the switch 102 and the contact b of the switch 17 are connected. Based on the switching signal SS, the switch 201 switches to the a side when the screen is not reduced and to the b side when the screen is reduced.

When the screen is not reduced, the signal processing circuit 14 outputs to the output signal Ho of the CCD input to the adder 13 and 1
Similar to the first embodiment, the arithmetic mean with the output H2 of the H delay line 12 is used as one input and the output H1 of the 1H delay line 11 is used as the other input. Therefore, the color signals C and the luminance signals Y that are not reduced are output to the output terminals Cout and Yout.
Can be obtained.

When the screen is reduced, Ho and H1 are input to the signal processing circuit 14. The color signal C output from the signal processing circuit 14 is sub-sampled by the reduction circuit 20 based on the control signal CS from the reduction control circuit 18, and the reduced color signal C is obtained at the output terminal Cout. The luminance signal Y output from the signal processing circuit 14 is the signal obtained through the b contact of the switch 201 and the switch 1
A vertical LPF output is obtained by taking an arithmetic mean with the b contact of 01 and the signal obtained via the 1H delay line 12, and this is input to the b contact of the switch 17. The luminance signal output from the switch 17 subsamples the reduction circuit 19 based on the control signal CS from the reduction control circuit 18,
The reduced luminance signal Y is obtained at the output terminal Yout. Here, the adder 13 calculates the average of the LP
The operation is equivalent to F15.

According to this embodiment, when the screen is reduced, the brightness signal Y of the vertical LPF output is obtained by using the adder 13 that performs the average addition in the vertical direction. Therefore, as compared with FIG. It can be realized by simply replacing the switch 201 with a simple structure.

FIG. 3 is a circuit configuration diagram for explaining the third embodiment of the present invention. In this embodiment, the 1H delay line 16 of FIG. 8 is removed, and the 1H delay line 12 for obtaining the delayed output of H2 and inputting it to the adder 13 is also used. Will be described with the same reference numerals.

That is, the output of the 1H delay line 11 to which the output of the CCD for outputting the Ho signal is input is the switch 1
The signal is input to the a contact point 01 and the signal processing circuit 14. The output of the switch 101 is input to one input of the adder 13 via the 1H delay line 12. The output signal Ho of the CCD is input to the other of the adder 13 and
Input to contact b of switch 102. The output of the adder 13 is input to the a contact of the switch 102. Switch 102
The output of is input to the signal processing circuit 14. Further, the output of the switch 24 is input to the b contact of the switch 101.

Here, the 1H delay line 12 changes the frequency of the CCD read clock signal CK from the reduction control circuit 18 depending on whether the screen is not reduced or reduced. When reduced, the frequency is divided by 1/2 compared to when not reduced,
The 1H delay line 12 at the time of reduction can be used as a 2H delay line. That is, the 1H delay line 12 shows the use state at the time of reduction. The output of the 1H delay line 12 and the delayed output of 1H at the time of reduction are input to the LPF 15 respectively, and the LPF 1
5 also includes the output of the horizontal sub-sampling circuit 25.
You have entered the line.

Reduction control circuit 1 when the screen is not reduced
Each switch 101, 102, 22, 24, 17 by 8
To the contact on the a side. The input signal Ho, the addition average signal of the output H2 of the 1H delay line 12 and the output H1 of the 1H delay line 11 are input to the signal processing circuit 14, and the state is the same as that shown in FIG. Therefore, from the outputs of the reduction circuits 20 and 19, non-reduced color signals and luminance signals can be obtained from the output terminals Cout and Yout, respectively.

When the screen is reduced, the control circuit 18 switches the switches 101, 102, 22, 24, and 17 to the contacts on the side b, and the clock signal is divided by half the CCD read clock signal CK. To
Input to the 2H delay line 12. Therefore, the signal processing circuit 14
Output signal Ho of CCD and output H1 of 1H delay line 11
Is input, and the state is the same as that shown in FIG. The luminance signal Y of the signal processing circuit 14 is input to the horizontal sub-sampling circuit 25, and the delay amount is 2H via the switch 101.
1H delay line 12 and 1H delay and 2H
The delayed signals are input to the LPF 15, respectively. LPF15
Also, the output of the horizontal sub-sampling circuit 25 is input to perform filtering for three lines, and the output is switched to the switch 17
Is input to the reduction circuit 19 via. The color signal C output of the signal processing circuit 14 is input to the reduction circuit 19 via the switch 22. The signals input to the reduction circuits 19 and 20 are thinned out based on the control signal CS of the reduction control circuit 18, respectively, and the reduced color signal C and luminance signal Y can be obtained from the output terminals Cout and Yout.

In this embodiment, the circuit size can be reduced by using the delay line for preventing the aliasing distortion of the luminance signal when the screen is reduced as the delay line when the screen is not reduced.

FIG. 4 is a circuit configuration diagram for explaining the fourth embodiment of the present invention. In this embodiment, only by adding a switch 401 and an adder 402,
The LPF 15 of the embodiment of FIG. 3 is deleted.

That is, the input terminal IN is switched to the switch 401.
The output of the switch 401 is connected to the other input of the adder 13 to which the output of the 1H delay line 12 is connected via the horizontal sub-sampling circuit 25. Switch 40
The b-contact 1 is connected to the b-contact of the switch 101 and is connected from the output of the switch 24. One input of the adder 402 is connected to the output of the adder 13, and
The output of the intermediate portion of the 1H delay line 12 showing the state of the delay amount of 2H when the screen is reduced is connected to the other. Adder 402
Is connected to the contact b of the switch 17. The above configuration is the part different from FIG.

At the input of the signal processing circuit 14 when each switch is switched to the contact on the a side when the screen is not reduced, the output H1 of the 1H delay line 11 and the CCD output Ho and the 1H delay line 1 are input.
A signal obtained by adding and averaging two outputs H2 is input. Therefore, the color signals C that are not reduced are output from the reduction circuits 20 and 19.
And the luminance signal Y can be derived.

Further, the input of the signal processing circuit 114 at the time of screen reduction in which each switch is switched to the contact on the b side is C
The CD output Ho and the output H1 of the 1H delay line 11 are input.
The color signal C output from the signal processing circuit 14 is input to the reduction circuit 20 via the b contact of the switch 22, where it is thinned out based on the control signal CS of the reduction control circuit 18 and reduced from the output terminal Cout. The color signal C thus obtained can be obtained.

The luminance signal Y output from the signal signal processing circuit 14 is input to the horizontal sub-sampling circuit 25 through the b contacts of the switches 24 and 401, where sub-sampling is performed to thin out the horizontal information. Adder 13
To one of the The brightness signal Y is output to the switches 24 and 101.
It is also input to the 1H delay line 12 via the b contact of the. In the 1H delay line 12, the delay amount is set to 2H based on the CCD read clock signal CK whose frequency is divided by 1/2 from the reduction control circuit 18, and the 1H delayed signal is added to the adder 40.
The signal delayed by 2H is input to the other side of the adder 13. The output of the adder 13 is input to the other of the adders 402. Therefore, the adder 402 inputs the output of the horizontal sub-sampling circuit 25, the signal delayed by 1H of the 1H delay line 12 and the signal delayed by 2H for a total of 3 lines, performs filtering, and outputs the output. Input to the reduction circuit 19 via the contact b of the switch 17. Reduction circuit 19
Then, the control signal C of the reduction control circuit 18
It is possible to obtain the luminance signal Y thinned out based on S and reduced from the output terminal Yout.

In addition to the features of the third embodiment, this embodiment uses the adders 13 and 402 instead of the filtering for the three lines of the luminance signal Y, so that the circuit configuration is simpler. Become.

[0042]

As described above, according to the single-chip color camera of the present invention, since the 1H delay line is shared, the circuit scale can be reduced.

[Brief description of drawings]

FIG. 1 is a block diagram for explaining a first embodiment of the present invention.

FIG. 2 is a block diagram for explaining a second embodiment of the present invention.

FIG. 3 is a block diagram for explaining a third embodiment of the present invention.

FIG. 4 is a block diagram for explaining a fourth embodiment of the present invention.

FIG. 5 is a block diagram for explaining a signal processing circuit of a conventional single-chip color camera.

FIG. 6 is an explanatory diagram illustrating a color filter array of a solid-state image sensor.

FIG. 7 is an explanatory diagram illustrating an example of image reduction.

FIG. 8 is a block diagram for explaining a signal processing circuit of another conventional single-chip color camera.

[Explanation of symbols]

11, 12 ... 1H delay line, 13, 401 ... Adder, 14
... Signal processing circuit, 15, 21, 23 ... LPF, 17, 2
2, 24, 101, 102, 201, 401 ... Switch, 18 ... Reduction control circuit, 19, 20 ... Reduction circuit, 25 ... Horizontal sub-sampling circuit, Cout, Yout ... Output terminal.

Claims (6)

[Claims] 1. A signal processing circuit for a single-chip color camera in which a signal from a single-plate solid-state image pickup device is repeatedly output for every two lines, wherein a first 1H delay line for inputting an output of the solid-state image pickup device and the first A second 1H delay line for inputting the output of the 1H delay line; a first arithmetic mean for averaging the input of the first 1H delay line and the output of the second 1H delay line; A first color separation circuit for performing color separation from three lines of the 1H delay line output of 1 and the output of the first averaging means; and a first color separation circuit different from the first color separation circuit.
The second 1H delay line is used for the first vertical arithmetic circuit for the luminance signal when the output luminance signal of the above is calculated by two or more lines, and the first color separation circuit is used for the first 1H delay. A signal processing circuit for a single-chip color camera, comprising: first switching means for switching so as to perform color separation from two lines of input and output of lines. 2. The first switching circuit inputs a first 1H delay line output to one side and a first luminance signal to the other side, and inputs the output to a second 1H delay line.
Of the selector and the first arithmetic mean output to one side and the first 1H delay line input to the other side, and when the first selector selects the first 1H delay line output, On the contrary, when the first selector selects the first luminance signal, the first arithmetic mean output is selected and the first 1H delay line input is selectively output, and the output is output by the first color separation. A second selector for inputting to the circuit; and the first luminance signal for one side, and the first vertical arithmetic circuit output for performing a vertical arithmetic operation from the first luminance signal and the second 1H delay line output for the other side. When the first selector selects the first 1H delay line output, the first luminance signal is input to the first selector, and conversely, the first selector outputs the first luminance signal.
And a third selector for selectively outputting the output of the first vertical operation circuit when the luminance signal of 1. is selected, the signal processing circuit of the single-chip color camera. 3. The first switching means comprises first sub-sampling means for sub-sampling the first luminance signal at a frequency of at least 1 / n or less (n is an integer), and the second 1H. A means for operating the delay line at an operating speed of at least 1 / n or less; a calculation from the first sub-sampling output and the (n + 1) line of each of the delay outputs of the second 1H delay line divided into n equal parts. The signal processing circuit for a single-chip color camera according to claim 1, further comprising: 4. The signal of a single-chip color camera according to claim 1, further comprising a second switching unit which also serves as the first vertical averaging circuit, as the first arithmetic mean. Processing circuit. 5. The second switching means inputs the first 1H delay line input to one side and the first luminance signal to the other side, and the first selector outputs the first 1H delay line output. Is selected, the first 1H delay line input is selected, and conversely, when the first selector selects the first luminance signal, the first luminance signal is selected and output, and the selected output is first added. A fourth selector for inputting to the averaging means, a first arithmetic mean for inputting the second 1H delay line output to the other, and a first arithmetic mean output for the second selector and the third selector. 5. The signal processing for a single-chip color camera according to claim 4, further comprising means for using the first averaging means also as the first vertical arithmetic circuit by inputting it to the selector. circuit. 6. The second switching means subsamples the fourth selector output at a frequency of at least 1 / n or less (n is an integer) and inputs the output to the first averaging means. Two sub-sampling means, first arithmetic mean means for inputting the second 1H delay line output to the other, and n equal divisions of the first arithmetic mean output and the second 1H delay line. 5. The signal processing circuit for a single-chip color camera according to claim 4, further comprising a first vertical calculation means for calculating from the (n + 1) line with the delayed output.