JPS6022770B2 - CRC circuit - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides that when a serial input/serial output polynomial generator is used in a cyclic/redundancy check (hereinafter referred to as CRC) generation/check circuit, the CRC character lead The present invention relates to a CRC circuit that uses simple hardware to generate a read trigger prior to timing.

When a serial input/serial output polynomial generator is used in the CRC generation/check circuit, circuits for parallel-to-serial conversion of CRC check data and serial-to-parallel conversion of CRC characters are required.

When reading a CRC character from the CRC circuit, it is necessary to apply a trigger in advance to generate a clock for serial-to-parallel conversion, and to read the CRC character after the serial-to-parallel conversion is completed using that clock. However, in a control device using a highly integrated IC such as a microprocessor, a trigger generation method prior to this read timing poses a problem. The present invention was made in consideration of the above points, and it is possible to generate a read trigger in advance of the CRC character read timing using simple hardware when using a serial input/serial output polynomial generator. The purpose is to provide a CRC circuit.

Hereinafter, embodiments of the CRC circuit of the present invention will be described based on the drawings. Figure 1 shows the C in the CRC circuit of one embodiment.
This is a circuit diagram related to RC character read, and Figure 2 shows the processor unit (which controls this CRC circuit).
For example, a microprocessor, hereinafter referred to as PU
FIG. 2 is a block diagram showing the relationship between First, the first
I will explain it from the diagram. A in FIG. 1 is an address decoder, to which address buses ADROO to ADR07 from a PU not shown in FIG. 1 are connected. This address decoder A is used to decode the address of the register that the PU attempts to read, and selects two registers depending on the address. The signals of the two registers selected by the address decoder A, that is, the registers REG, . . . REG2, are supplied to the first input terminals of the AND circuits B, .

A superimposed pulse is supplied from the PU to each second input terminal of the AND circuits B and &. The output of AND circuit B is supplied to gates F, , F2. These gates F, , F2 will be described later.
Further, the output of the AND circuit B is connected to the first input terminal of the AND circuit C in the clock generation circuit C,
(hereinafter referred to as FF) set input terminal S of C2, register C
It is designed to be transferred to the load terminal of No. 3. This clock generation circuit C is a clock generation circuit for converting CRC characters from serial to parallel.
There are eight rises and falls for each movement.

This clock generation circuit C is the above-mentioned AND circuit C, FF.
C2, register C3, and AND circuit C4. A clock signal is introduced into the first input terminal of the AND circuit C4.
The output of the AND circuit C is supplied to the second input terminal of the circuit C.4. The output from the output terminal Q of the FFC 2 is supplied to the second input terminal of the AND circuit C. A borrow signal is supplied from the resistor C3 to the reset input terminal of the FFC2. For example, a voltage of 15 volts is applied to the input terminals D, -D3 of the resistor C3, and the input terminal D4 is grounded. An AND circuit C4 is connected to the clock input terminal of the register C3.
Nine pieces of output are now available. A clock signal for serial-to-parallel conversion appears at the output terminal of this AND circuit C4. The clock signal appearing at the output of the AND circuit 4 is applied to the clock input of the polynomial generator D and the clock input of the shift register E. The polynomial generator D is a serial input/serial output polynomial generator, and the CRC data is input to its input terminal.
The output device is configured to output a CRC character, and this output is coupled to the input terminal of the shift register E. This shift register E receives C from the polynomial generator D.
This is a shift register that converts the RC character from serial to parallel, and 4 bits of the 8-bit output are supplied to the gate F2. That is,
Output terminal of shift register E○. ~0 is connected to gate F2, and output devices 04 to 07 are connected to gate F. The output terminals of gates F, ~F2 are designed to output 4-bit data, respectively, and these gates F, ~F2
The output ends of each are connected to the data bus of the PU. On the other hand, in Figure 2, DATA is the first
A data bus (8 bits) is connected to the output ends of gates F, F2 in the figure, and PUIO0 and a CRC circuit 200 are connected to this data bus DATA.

In addition, ADR is an address bus (16 bits), and corresponds to address buses ADROO to ADR07 connected to address decoder A in FIG.
D is the read pulse in FIG. This read pulse READ is designed to be transferred to PUI O 0, CRC20, and the address bus ADR is PUIO
0, the CRC circuit 200 is connected. And C.R.
A clock generation circuit C is connected to the C circuit 200. Therefore, as the relationship between Fig. 2 and Fig. 1, the second
It can be seen that the CRC circuit 200 in the figure is the remaining portion after removing the clock generation circuit C in FIG.
Next, the operation of the CRC circuit of the present invention constructed as described above will be explained based on FIG.

In explaining this operation, PUIOO is the CRC circuit 200.
The operation when reading the CRC character from is explained below. When reading a CRC character, PUIOO first reads register REG2 having a certain address. To read this register REG2, the address decoder decodes the address transferred from PUIOO through address buses ADROO to ADR07 and selects register REG2. By selecting this register REG2, its output is applied to the first input terminal of AND circuit B2. Also, P.U.
A read pulse from IOO is applied to the second input terminal of AND circuit B2, AND circuit B2 ANDs the read pulse and the output of register REG2, and outputs a CRC signal from AND circuit &. This CRC trigger is applied to the AND circuit of the clock generation circuit C, the first input terminal of the FF
It is transferred to the set input terminal S of C2 and the load terminal of register C3. By applying the CRC trigger signal to the set terminal S of FFC2, FFC2 is set, which causes the AND circuit to output the CRC trigger signal and FFC2.
The output is ANDed with the output of the AND circuit C4, and the output is sent to the second input terminal of the AND circuit C4. A clock signal is introduced into the first input terminal of the AND circuit C4, and this clock signal and the output of the AND circuit C are ANDed. Thus, the clock generator C generates serial-to-parallel conversion clock signals. The clock signal is transferred to each clock input of polynomial generator ◯ and shift register E, and is also applied to the clock input of register C3. When this clock signal is transferred to the polynomial generator D, the polynomial generator D generates a clock signal at the rising edge of this clock signal.
The CRC character is output bit by bit and transferred to the input terminal of shift register E.

Furthermore, when the clock signal for serial-to-parallel conversion is transferred to its clock input terminal, this shift register E latches the CRC character sent from the polynomial generator D at the rising edge of the clock signal and converts it into parallel. . This CRC character converted into parallel is output at the output terminal 0 of the shift register E.

Gates F2, F for every 4 bits ~03, 04~07
, and when the 8-bit CRC character has been transferred, the clock signal stops and the shift register E
The CRC characters converted in parallel are held. Next, PUIOO selects a register REG having an address different from that of register REG2 after a time interval necessary for this serial-to-parallel conversion from reading register REG2.

That is, in the same manner as above, the register RE is
The register G, is transferred to the register decoder A, where it is decoded, and the register decoder A then registers the register REG.
, select. As a result, the output signal of register REG is applied to the first input terminal of AND circuit B. When a read pulse from PUIOO is introduced into the second input terminal of this AND circuit B, it performs an AND with this read pulse and the output of register REG, and transfers the CRC read signal to gates F, F2. . When this CRC read signal is transferred to gates F,,F2, gates F,,F2
opens the gate. As a result, the CRC character converted into parallel data by shift register B is passed through gates F2 and F and the data bus in 4-bit increments to P.
U' will be transferred. In this way, PUIOO is CR
Can lead C character. As described above, the read operation of the register REG2 is for generating a trigger for a clock signal, and the read data has no meaning. A trigger for a serial-to-parallel conversion clock signal is generated by a dummy read of PUIOO. As described above, the CRC circuit of the present invention decodes the address from the processor unit to select the first register, generates a CRC trigger signal using the output of this register and the read pulse from the processor unit, and converts serial to parallel signals. A conversion clock generation circuit is triggered to generate a serial-to-parallel conversion clock signal, and this CJA-parallel conversion clock signal is used to output a CRC character bit by bit to a polynomial generator. The output CRC character is converted into parallel data based on the clock signal for serial-to-parallel conversion, and when the CRC character converted to parallel data is output, a second register is selected based on the address from the processor unit, and the second register is selected based on the address from the processor unit. Since the CRCIJ-code signal is generated by the output read pulse of the register No. 2 and the CRC character converted to parallel is read out, the ℃RC character can be used to generate the read trigger generation timing with a small amount of hardware and firmware. I can do it.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a CRC circuit of the present invention, and FIG. 2 is a block diagram showing the relationship between a processor unit, a CRC circuit, and a clock generation circuit for serial-to-parallel conversion. 100... Processor unit, 200... CRC
Circuit, A...address decoder, B, string, C,, C4...
・AND circuit, C...clock generation circuit, D...polynomial generator, E...shift register, F,, F2...
·Gate. Figure 2: Ship

Claims (1)

[Claims] 1 Decodes the first read address given from the processor unit and outputs the first decode signal, decodes the second read address given from the processor unit and outputs the second read address signal. a first logic gate that outputs a cycle redundancy check trigger signal in response to address decoding, the first decode signal and a read pulse obtained from the upper processor unit; a second logic gate that outputs a cyclic redundancy check read signal; a clock generation circuit that generates a serial-to-parallel conversion clock signal when triggered by the cyclic redundancy check trigger signal; a polynomial generator that serially outputs a cyclic redundancy check character bit by bit based on the serial-to-parallel conversion clock signal; The parallel cyclic redundancy check character held in the shift register when the cyclic redundancy check read signal is output from the second logic gate is read out and sent to the processor unit. A CRC circuit consisting of a third logic gate for transfer.