JPS60225458A - Gaas ic - Google Patents
Gaas icInfo
- Publication number
- JPS60225458A JPS60225458A JP59081361A JP8136184A JPS60225458A JP S60225458 A JPS60225458 A JP S60225458A JP 59081361 A JP59081361 A JP 59081361A JP 8136184 A JP8136184 A JP 8136184A JP S60225458 A JPS60225458 A JP S60225458A
- Authority
- JP
- Japan
- Prior art keywords
- film
- capacitor
- pga
- gaas
- insulating film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000003990 capacitor Substances 0.000 claims description 27
- 229910001218 Gallium arsenide Inorganic materials 0.000 claims description 15
- 239000010407 anodic oxide Substances 0.000 claims description 8
- 239000002184 metal Substances 0.000 claims description 5
- 238000000034 method Methods 0.000 description 4
- 239000000758 substrate Substances 0.000 description 4
- 238000007743 anodising Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 1
- 230000003321 amplification Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000008020 evaporation Effects 0.000 description 1
- 238000001704 evaporation Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 210000003127 knee Anatomy 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 235000013372 meat Nutrition 0.000 description 1
- 238000003199 nucleic acid amplification method Methods 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
- 229910052814 silicon oxide Inorganic materials 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/01—Manufacture or treatment
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D1/00—Resistors, capacitors or inductors
- H10D1/60—Capacitors
- H10D1/68—Capacitors having no potential barriers
Landscapes
- Junction Field-Effect Transistors (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
（技術分野）
本発明はＧａＡｓ集積回路に関し、特にキャパシターを
含む高周波増幅用に好適なＧａＡｓ集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a GaAs integrated circuit, and more particularly to a GaAs integrated circuit including a capacitor and suitable for high frequency amplification.
（従来技術）
Ｇ ａ Ａ ｓは電子易動度が大きく、電子飽和速度が
大きい仁とから高い遮断周波数のＦＥＴが実現できる材
料として注目され、単体のＦＥＴとして商品化されてい
る。近年Ｃ，Ｒ，Ｌ等の回路素子を含むＧａＡｓ増幅器
のモノリシック化の為の開発が進み、ＧａＡｓ集積回路
の商品化がされつつある。(Prior Art) GaAs has a high electron mobility and a high electron saturation speed, so it has attracted attention as a material that can realize a FET with a high cutoff frequency, and has been commercialized as a single FET. In recent years, development has progressed to make monolithic GaAs amplifiers including circuit elements such as C, R, and L, and GaAs integrated circuits are being commercialized.
この種のＩＣに用いられるキャパシタＩＣ）はＭＩＭ（
金属−絶縁膜−金属）構造を用いる方法が主流であシ、
該絶縁膜にはＦＥＴのパッジベージロン膜と同一のもの
、例えばシリコン酸化膜（Ｓｉｎｓ）やシリコン窒化膜
（８ｉｓＮａ） ？ニー用いる方法がとられていた。し
かしこれらの絶縁膜でＩｄ Ｇ ａ Ａ ｓ−絶縁膜界
面状態はあまシ良好でなく、界面準位が多い為、ＦＥＴ
の安定動作の観点から問題があった。The capacitor IC used in this type of IC) is the MIM (capacitor IC) used in this type of IC.
The mainstream method is to use a metal-insulating film-metal structure;
Is the insulating film the same as the padding film of the FET, such as a silicon oxide film (Sins) or a silicon nitride film (8isNa)? The knee method was used. However, in these insulating films, the IdGaAs-insulating film interface condition is not very good, and there are many interface states, so FET
There was a problem from the viewpoint of stable operation.
現在ＦＥＴのパッジベージロン膜としては多結晶ＧａＡ
ｓ（ＰＧＡ ）膜を積層する方法が最も良いとされてい
る。しかしＭＩＭＱ造のキャパシタを作る観点ではＰＧ
Ａ膜は比誘電率が１１．２と小さく・キャパシタ面積を
低減する上でよシ大きな比誘電率を持つ絶縁膜を用いる
ことが望ましい。この種のＩＣではＩＣの全面積に対し
キャパシタの占める面積は大きく、単位ウェーハ面積あ
たりのチップの収率を向上させる上でキャパシタの絶縁
膜の比誘電率は大きい程好ましい。又信頼度上からキャ
パシタの絶縁膜はあまシ薄くできない為、この観点から
も比誘電率を高めることが得策である。Currently, polycrystalline GaA is used as the padding film for FETs.
It is said that the best method is to stack s(PGA) films. However, from the point of view of making MIMQ capacitors, it is PG.
The A film has a small dielectric constant of 11.2, and in order to reduce the capacitor area, it is desirable to use an insulating film with a large dielectric constant. In this type of IC, the area occupied by the capacitor is large with respect to the total area of the IC, and in order to improve the yield of chips per unit wafer area, it is preferable that the dielectric constant of the insulating film of the capacitor be as large as possible. Furthermore, since the insulating film of the capacitor cannot be made too thin due to reliability reasons, it is a good idea to increase the dielectric constant from this point of view as well.
（発明の目的）
本発明の目的は、特性が安定で、占有面積が小さく絶縁
耐圧も優れたキャパシタを有するＧａＡｓ集積回路を提
供することにある。(Objective of the Invention) An object of the present invention is to provide a GaAs integrated circuit having a capacitor with stable characteristics, a small occupied area, and excellent dielectric strength.
（発明の構成）
本発明のＧａＡｓ集積回路は、ＭＩＭ （金属−絶縁膜
−金属）構造のキャパシタを有するＧａＡｓ集積回路に
おいて、前記絶縁膜が多結晶ＧａＡｓとその陽極酸化膜
の２層構造であることによ１１成される。(Structure of the Invention) The GaAs integrated circuit of the present invention has a capacitor with an MIM (metal-insulating film-metal) structure, in which the insulating film has a two-layer structure of polycrystalline GaAs and an anodized film thereof. In particular, 11 will be made.
（実施例）
第１図は本発明の一実施例の断面図である。第１図にお
いて、２はＧ ａ Ａ ｓ基板１上に形成されたキャパ
シタの第１電極となる電極金属、３はＰＧＡ膜・４はＰ
ＧＡ膜を陽極酸化び構成したＰＧＡ・陽極酸化膜であシ
、また５はＰＧＡ陽極酸化膜の上に形成されたキャパシ
タの第２電極となる電極金属である。(Embodiment) FIG. 1 is a sectional view of an embodiment of the present invention. In FIG. 1, 2 is an electrode metal that becomes the first electrode of a capacitor formed on a GaAs substrate 1, 3 is a PGA film, and 4 is a P
It is a PGA/anodized film formed by anodizing the GA film, and 5 is an electrode metal that is formed on the PGA anodic oxide film and becomes the second electrode of the capacitor.
以上によシ第１電極２．第２電極５．絶縁膜としてＰＧ
Ａ膜３とＰＧＡ膜を陽極酸化して形成した陽極酸化膜４
の２層構造絶縁膜よりなるキャパシタが形成できる。Based on the above, the first electrode 2. Second electrode5. PG as an insulating film
Anodic oxide film 4 formed by anodizing the A film 3 and the PGA film
A capacitor consisting of a two-layer structure insulating film can be formed.
この構造のキャパシタでは絶縁膜がＰＧＡよシ比誘電率
が大きいＰＧＡの陽極酸化膜とＰＧＡの２層構造となっ
ているためＰＧＡ単体より大きな比誘電率とすることが
でき容量を大きくすることができる。In a capacitor with this structure, the insulating film has a two-layer structure of the anodic oxide film of PGA and PGA, which has a higher dielectric constant than PGA, so it can have a higher dielectric constant than PGA alone and can increase the capacitance. can.
また、ＦＥＴのパッジベージ冒ン膜トキャパシタの絶縁
膜を共用したプロセスでもＦＥＴ活性層゛と接する膜は
ＰＧＡであるため、特性が安定したＩＣを実現できる。In addition, even in a process in which the padding film of the FET and the insulating film of the capacitor are shared, since the film in contact with the FET active layer is PGA, an IC with stable characteristics can be realized.
またキャパシタの絶縁耐量も陽極酸化膜の介在によル大
幅に向上させることができる。Furthermore, the dielectric strength of the capacitor can be greatly improved by the presence of the anodic oxide film.
第２図（旬〜（ｄ）は本発明の第２の実施例の製造方法
を説明するために工程順に示した断面図である。FIG. 2(d) is a cross-sectional view shown in the order of steps for explaining the manufacturing method of the second embodiment of the present invention.
本実施例ではＰＥＴとキャパシタの共存する場合につい
て説明する。In this embodiment, a case where PET and a capacitor coexist will be described.
第２図ｔａ＞に示すように、公知の方法によｊ５ ＦＥ
Ｔを形成する。図において２６はイオン注入活性層、２
７はソース、２８はドレイン、２９はゲートでおる。ま
た２２はＧａＡｓ基板上に形成したキャパシタの下部電
極となるキャパシタ第１層電極である。As shown in Fig. 2, j5 FE is
Form a T. In the figure, 26 is an ion-implanted active layer;
7 is a source, 28 is a drain, and 29 is a gate. Further, 22 is a capacitor first layer electrode which becomes the lower electrode of the capacitor formed on the GaAs substrate.
次に、第２図（ｂｌに示すように、フラッシュ蒸着法で
ＰＧＡ膜２３１に前記基板表面に積層形成する。Next, as shown in FIG. 2 (bl), a PGA film 231 is laminated on the surface of the substrate by flash evaporation.
これによ、ｊ７ ＦＥＴ活性層とキャパシタ第１層電極
を被覆することができる。次いでＰＧＡ膜上にホトレジ
スト膜３０１に形成し、キャパシタ形成部分に開口部３
１を形成する。This allows the j7 FET active layer and the capacitor first layer electrode to be covered. Next, a photoresist film 301 is formed on the PGA film, and an opening 3 is formed in the capacitor formation area.
form 1.
次に、第２図（ｃｌに示すように、開口部３１０ＰＧＡ
ｇを陽極酸化し陽極酸化膜２４を形成し、開口し、キ
ャパシタの第２層目の電極２５及びＦＥＴの電極配線３
２．３３を形成する０以上によυ本発明の第２の実施例
のキャパシタを有するＧａＡｓ集積回路が完成する。本
実施例のキャパシタも絶縁膜としてはＰＧＡ膜２３とＰ
ＧＡ膜の陽極酸化膜２４の２層構造となってお多容量の
大きいキャパシタが得られ、またＦＥＴの活性層に接す
る膜はＰＧＡ膜であるので特性の安定したＧ ａ Ａ
ｓ集積回路が得られる◎（発明の効果）
以上説明したとおシ、本発明によれは、特性が安定で、
占有面積がφさく、かつ絶縁耐圧も優れたキャパシタを
有するＧａＡｓ集積回路が得られる０Next, as shown in FIG. 2 (cl), the opening 310PGA
g is anodized to form an anodic oxide film 24, an opening is formed, and the second layer electrode 25 of the capacitor and the electrode wiring 3 of the FET are formed.
By 0 or more forming 2.33, a GaAs integrated circuit having a capacitor according to the second embodiment of the present invention is completed. The capacitor of this embodiment also uses the PGA film 23 and P as the insulating film.
The two-layer structure of the anodic oxide film 24 of the GA film provides a capacitor with large capacitance, and since the film in contact with the active layer of the FET is a PGA film, the G a A film with stable characteristics can be obtained.
s integrated circuit can be obtained◎ (Effect of the invention) As explained above, according to the present invention, the characteristics are stable,
A GaAs integrated circuit having a capacitor with a small occupied area and an excellent dielectric strength can be obtained.
説明するために工程順に示した断面図である。
１．２１−ＧａＡｓ基板、２．２２−・・第１層電極、
３．２３・・・ＰＧＡ膜、４，２４・・・ＰＧＡ陽極酸
化膜、５．２５・・・第２層電極、２６・・・イオン注
入活性層、２７・・・ソース、２Ｂ・・ドレイン、２９
・・・ゲート、３０・・ホトレノスト膜、３１・・・開
口部、３２．３３・・・電極配線。
代理人 弁理士 内 原 晋
′。′°２′茗２図FIG. 4 is a cross-sectional view shown in order of steps for explanation. 1.21-GaAs substrate, 2.22-...first layer electrode,
3.23...PGA film, 4,24...PGA anodic oxide film, 5.25...Second layer electrode, 26...Ion implantation active layer, 27...Source, 2B...Drain , 29
...gate, 30...photorenost film, 31...opening, 32.33...electrode wiring. Agent: Susumu Uchihara, patent attorney. '°2' Meat 2 diagram
Claims (1)
するＧａＡｓ集積回路において、前記絶縁膜が多結晶Ｇ
ａＡｓとその陽極酸化膜の２層構造であることを特徴と
するＧａＡｓ集積回路。In a GaAs integrated circuit having a capacitor with an MIM (metal-insulating film-metal) structure, the insulating film is made of polycrystalline G.
A GaAs integrated circuit characterized by having a two-layer structure of aAs and an anodic oxide film thereof.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59081361A JPS60225458A (en) | 1984-04-23 | 1984-04-23 | Gaas ic |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP59081361A JPS60225458A (en) | 1984-04-23 | 1984-04-23 | Gaas ic |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60225458A true JPS60225458A (en) | 1985-11-09 |
Family
ID=13744195
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP59081361A Pending JPS60225458A (en) | 1984-04-23 | 1984-04-23 | Gaas ic |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60225458A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0515824A2 (en) * | 1991-05-31 | 1992-12-02 | Sumitomo Electric Industries, Ltd | Capacitor element |
| WO2011028462A1 (en) * | 2009-09-03 | 2011-03-10 | Raytheon Company | Method for selective deposition of dielectric layers on semiconductor structures |
-
1984
- 1984-04-23 JP JP59081361A patent/JPS60225458A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0515824A2 (en) * | 1991-05-31 | 1992-12-02 | Sumitomo Electric Industries, Ltd | Capacitor element |
| WO2011028462A1 (en) * | 2009-09-03 | 2011-03-10 | Raytheon Company | Method for selective deposition of dielectric layers on semiconductor structures |
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