JPH0521419A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH0521419A JPH0521419A JP17080191A JP17080191A JPH0521419A JP H0521419 A JPH0521419 A JP H0521419A JP 17080191 A JP17080191 A JP 17080191A JP 17080191 A JP17080191 A JP 17080191A JP H0521419 A JPH0521419 A JP H0521419A
- Authority
- JP
- Japan
- Prior art keywords
- etching
- inp substrate
- solution
- via hole
- hydrogen peroxide
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Electrodes Of Semiconductors (AREA)
- Weting (AREA)
Abstract
Description
【0001】[0001]
【産業上の利用分野】本発明は半導体装置の製造方法に
関し、特にInP基板を用いた超高周波用電界効果トラ
ンジスタあるいはヘテロ接合バイポーラトランジスタ等
のInP基板へのバイアホールの形成方法に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for forming a via hole in an InP substrate such as a field effect transistor for super high frequency using an InP substrate or a heterojunction bipolar transistor.
【0002】[0002]
【従来の技術】InP等の化合物半導体結晶は電子飽和
速度および電子移動度が大きいことから超高速,超高周
波用素子材料として注目され、これを用いた半導体装置
の検討がいくつか行なわれている。特にInP基板を用
いたMIS型電界効果トランジスタ(MISFET)は
高電流、高耐圧が得られることから超高周波高出力FE
Tとしてのポテンシャリティーが高い。高周波高出力F
ETでは通常、FETチップの寄生インダクタンス低減
の為、ソース電極と基板裏面を電気的に接続するバイア
ホール構造が用いられている。またマイクロ波モノリシ
ック集積回路においても基板裏面との導通のためのバイ
アホールが不可欠である。このバイアホールを形成する
工程ではエッチング法は通常、硫酸と過酸化水素の混合
液、あるいは臭素とメタノールの混合液等を用いたウェ
ットエッチング法が用いられている。2. Description of the Related Art Since compound semiconductor crystals such as InP have a high electron saturation speed and electron mobility, they have attracted attention as an element material for ultra-high speed and ultra-high frequency, and some studies have been conducted on semiconductor devices using them. . In particular, since a MIS field effect transistor (MISFET) using an InP substrate can obtain a high current and a high breakdown voltage, it is possible to obtain a super high frequency and high output FE.
Potency as T is high. High frequency high power F
In ET, a via hole structure that electrically connects the source electrode and the back surface of the substrate is usually used in order to reduce the parasitic inductance of the FET chip. Also in the microwave monolithic integrated circuit, a via hole is indispensable for conduction with the back surface of the substrate. In the step of forming the via hole, a wet etching method using a mixed solution of sulfuric acid and hydrogen peroxide, a mixed solution of bromine and methanol, or the like is usually used as an etching method.
【0003】[0003]
【発明が解決しようとする課題】InP基板へバイアホ
ールを形成する工程で用いられるエッチング液は、エッ
チング速度が高くかつ面方位依存性の小さいことが要求
される。しかしながら、上述の通常用いられているよう
なエッチング液をInP基板のバイアホール形成に用い
た場合、エッチング速度が低い、面方位依存性が大き
い、ピットが発生するといった問題が生じ、良好なバイ
アホールを形成することは困難である。The etching solution used in the step of forming a via hole in an InP substrate is required to have a high etching rate and a small plane orientation dependency. However, when the above-described commonly used etching solution is used to form a via hole in an InP substrate, problems such as low etching rate, large plane orientation dependency, and pit formation occur, and a good via hole is formed. Is difficult to form.
【0004】本発明の目的はこのような問題点を解消
し、InP基板に短時間で良好なバイアホールを形成す
ることのできる半導体装置の製造方法を提供することで
ある。An object of the present invention is to solve the above problems and to provide a method of manufacturing a semiconductor device capable of forming a good via hole in an InP substrate in a short time.
【0005】[0005]
【課題を解決するための手段】本発明の半導体装置製造
方法は、InP基板へのバイアホール形成のエッチング
液として、塩酸と過酸化水素水と酢酸の混合液を用いる
ものである。The method of manufacturing a semiconductor device according to the present invention uses a mixed solution of hydrochloric acid, hydrogen peroxide solution and acetic acid as an etching solution for forming a via hole in an InP substrate.
【0006】[0006]
【作用】通常バイアホールは基板厚30〜50μmを貫
通するものであるが、このようなバイアホール形成に用
いられるエッチング液に要求される条件として、上述の
ように、まずエッチング速度が速いことがあげられる。
また面方位依存性の大きなエッチング液では、開口面積
が小さいとバイアホールが貫通しないおそれがあるた
め、面方位依存性はなるべく小さくおさえなければなら
ない。さらにエッチング荒れ、ピットなどの発生が少な
いことが必要となる。The via hole normally penetrates through the substrate with a thickness of 30 to 50 .mu.m. As a condition required for the etching solution used for forming such a via hole, as described above, the etching rate must be high first. can give.
Further, in an etching solution having a large plane orientation dependency, if the opening area is small, the via hole may not penetrate, so the plane orientation dependency should be kept as small as possible. Furthermore, it is necessary to reduce the occurrence of etching roughness and pits.
【0007】図2に本発明による塩酸、過酸化水素水、
酢酸の混合液の液温とInP基板に対するエッチング速
度を示す。液温を30℃に上げることにより、通常のバ
イアホールエッチング工程に十分なエッチング速度が得
られる。図3(a),(b)に塩酸、過酸化水素水、酢
酸の混合液を用いた場合と、硫酸、過酸化水素水の混合
液を用いた場合のInP基板のエッチングプロファイル
を示す。硫酸系のエッチング液は面方位依存性が大きい
のに対し本発明のエッチング液は比較的面方位依存性が
小さくエッチング面も急峻となる。以上のことから本発
明による塩酸、過酸化水素水、酢酸の混合液はInP基
板のバイアホール形成のエッチング液として適当である
ことがわかる。FIG. 2 shows hydrochloric acid, hydrogen peroxide solution according to the present invention,
The liquid temperature of the mixed solution of acetic acid and the etching rate for the InP substrate are shown. By raising the liquid temperature to 30 ° C., an etching rate sufficient for a normal via hole etching process can be obtained. FIGS. 3A and 3B show etching profiles of the InP substrate when using a mixed solution of hydrochloric acid, hydrogen peroxide solution and acetic acid and when using a mixed solution of sulfuric acid and hydrogen peroxide solution. While the sulfuric acid-based etching solution has a large plane orientation dependency, the etching solution of the present invention has a relatively small plane orientation dependency and the etching surface is sharp. From the above, it can be seen that the mixed solution of hydrochloric acid, hydrogen peroxide solution and acetic acid according to the present invention is suitable as an etching solution for forming a via hole of an InP substrate.
【0008】尚、混合液中の塩酸の量は過酸化水素水の
5倍以上が好ましく、それより少くなると、エッチング
面が荒れる。またバッファ液としての酢酸の量は過酸化
水素水と同量以上が好ましく、それ以下になるとエッチ
ング速度が速くなり、表面が荒れる。The amount of hydrochloric acid in the mixed solution is preferably 5 times or more than that of hydrogen peroxide, and if it is less than that, the etching surface becomes rough. Further, the amount of acetic acid as the buffer solution is preferably equal to or more than the amount of hydrogen peroxide solution, and if it is less than that, the etching rate becomes high and the surface becomes rough.
【0009】[0009]
【実施例】以下、本発明の実施例を図面を用いて説明す
る。図1(a)〜(c)は本発明の一実施例を説明する
ための工程順に示した半導体チップの断面図である。Embodiments of the present invention will be described below with reference to the drawings. 1A to 1C are cross-sectional views of a semiconductor chip shown in the order of steps for explaining an embodiment of the present invention.
【0010】まず図1(a)に示すように、表面にFE
Tが作製されたInP基板1の裏面のソース電極4と対
応する位置にフォトレジスト膜5でバイアホール開口用
のパターンを形成する。次に図1(b)に示すようにフ
ォトレジスト膜5をマスクにして液温20〜30℃の塩
酸:過酸化水素水:酢酸=20:1:20の混合液でI
nP基板1をエッチングしてバイアホール6を開口す
る。最後に図1(c)に示すように、InP基板1の裏
面に金メッキ層7を形成して導通工程を完了させる。First, as shown in FIG. 1A, FE is formed on the surface.
A pattern for opening a via hole is formed with a photoresist film 5 at a position corresponding to the source electrode 4 on the back surface of the InP substrate 1 on which T has been manufactured. Next, as shown in FIG. 1B, using the photoresist film 5 as a mask, a mixed solution of hydrochloric acid: hydrogen peroxide: acetic acid = 20: 1: 20 at a liquid temperature of 20 to 30 ° C.
The nP substrate 1 is etched to form a via hole 6. Finally, as shown in FIG. 1C, a gold plating layer 7 is formed on the back surface of the InP substrate 1 to complete the conduction step.
【0011】[0011]
【発明の効果】以上の説明から明らかなように、本発明
によれば、InP基板を用いた半導体装置に対して短時
間で形状のよい良好なバイアホールを形成することがで
きるという効果がある。As is clear from the above description, according to the present invention, it is possible to form a good via hole having a good shape in a semiconductor device using an InP substrate in a short time. .
【図1】本発明の一実施例を説明するための半導体チッ
プの断面図。FIG. 1 is a sectional view of a semiconductor chip for explaining an embodiment of the present invention.
【図2】実施例におけるエッチング液の液温とエッチン
グ速度の関係を示す図。FIG. 2 is a diagram showing a relationship between a solution temperature of an etching solution and an etching rate in the example.
【図3】従来のエッチング液によるInP基板のエッチ
ングプロファイルと本発明によるエッチング液のエッチ
ングプロファイルを示す図。FIG. 3 is a diagram showing an etching profile of an InP substrate with a conventional etching solution and an etching profile of an etching solution according to the present invention.
1 InP基板 2 ドレイン電極 3 ゲート電極 4 ソース電極 5 フォトレジスト膜 6 バイアホール 7 金メッキ層 1 InP substrate 2 drain electrode 3 Gate electrode 4 Source electrode 5 Photoresist film 6 via holes 7 Gold plating layer
Claims (2)
ちこのInP基板にウェットエッチング法によりバイア
ホールを形成する半導体装置の製造方法において、エッ
チング液として塩酸と過酸化水素水と酢酸の混合液を用
いることを特徴とする半導体装置の製造方法。1. A method of manufacturing a semiconductor device, comprising forming a semiconductor element on an InP substrate and then forming a via hole in the InP substrate by a wet etching method, wherein a mixed solution of hydrochloric acid, hydrogen peroxide solution and acetic acid is used as an etching solution. A method for manufacturing a semiconductor device, which is characterized by being used.
上である請求項1記載の半導体装置の製造方法。2. The method for manufacturing a semiconductor device according to claim 1, wherein the hydrochloric acid in the mixed solution is at least 5 times as much as the hydrogen peroxide solution.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17080191A JPH0521419A (en) | 1991-07-11 | 1991-07-11 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP17080191A JPH0521419A (en) | 1991-07-11 | 1991-07-11 | Manufacture of semiconductor device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH0521419A true JPH0521419A (en) | 1993-01-29 |
Family
ID=15911604
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP17080191A Pending JPH0521419A (en) | 1991-07-11 | 1991-07-11 | Manufacture of semiconductor device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0521419A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002198616A (en) * | 2000-12-25 | 2002-07-12 | Fujitsu Quantum Devices Ltd | Method of manufacturing semiconductor device, and method of manufacturing optical waveguide |
US7619334B2 (en) | 2003-03-31 | 2009-11-17 | Panasonic Corporation | Motor having a highly reliable grounding structure and electric equipment on which the motor is mounted |
-
1991
- 1991-07-11 JP JP17080191A patent/JPH0521419A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2002198616A (en) * | 2000-12-25 | 2002-07-12 | Fujitsu Quantum Devices Ltd | Method of manufacturing semiconductor device, and method of manufacturing optical waveguide |
US7619334B2 (en) | 2003-03-31 | 2009-11-17 | Panasonic Corporation | Motor having a highly reliable grounding structure and electric equipment on which the motor is mounted |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
A02 | Decision of refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A02 Effective date: 19991026 |