JPS60225447A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPS60225447A JPS60225447A JP8227584A JP8227584A JPS60225447A JP S60225447 A JPS60225447 A JP S60225447A JP 8227584 A JP8227584 A JP 8227584A JP 8227584 A JP8227584 A JP 8227584A JP S60225447 A JPS60225447 A JP S60225447A
- Authority
- JP
- Japan
- Prior art keywords
- film
- aluminum wiring
- layer aluminum
- layer
- wiring film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
この発明は、半導体装置の製造方法に関し、多層配Ｉｗ
Ｋおげろ層間絶縁膜の絶縁特性の向上および配慰材料、
特にアルミのヒルツク防止に関するものである。[Detailed Description of the Invention] [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and relates to a method for manufacturing a semiconductor device.
Improving insulation properties of K-Ogero interlayer insulation film and supporting material,
In particular, it concerns the prevention of aluminum hilts.
従来の半導体装置の構造ｗｌｌＬ１図に示す。この図に
おいて、１はシリコン半導体基板、２はこのシリコン半
導体基板１上に形成した素子間分離用のフィールド酸化
膜、３はゲート酸化膜、４はこのフィールド酸化膜２お
よびゲート酸化膜３上に選択的に形成したゲートおよび
配線用の多結晶シリコン膜、５は前記シリコン半導体基
板１上に拡散により形成したソースおよびドメイン領域
、６はコンタクト孔の領域以外の部分に形成された燐を
含んだシリコン酸化膜、７は前記シ・リコン半導体基板
１上に形成された素子領域と電気的忙接続された第１層
のアルミ配線膜、８は前記第１層のフルミ配締膜７上に
形成されるスルーホール領域以外の部分に形成された層
間絶縁膜であるシリコン酸化膜、３は前記１１ｇ１層の
アルミ配線膜７と電気的に接続された第２層のアルミ配
線膜である。The structure of a conventional semiconductor device is shown in FIG. In this figure, 1 is a silicon semiconductor substrate, 2 is a field oxide film for isolation between elements formed on this silicon semiconductor substrate 1, 3 is a gate oxide film, and 4 is a silicon semiconductor substrate formed on this field oxide film 2 and gate oxide film 3. A selectively formed polycrystalline silicon film for gates and wiring, 5 a source and domain region formed by diffusion on the silicon semiconductor substrate 1, and 6 containing phosphorus formed in a portion other than the contact hole region. A silicon oxide film 7 is a first layer aluminum wiring film electrically connected to the element region formed on the silicon semiconductor substrate 1, and 8 is formed on the first layer FLUMI interconnection film 7. A silicon oxide film 3, which is an interlayer insulating film formed in a portion other than the through hole region, is a second layer aluminum wiring film electrically connected to the aluminum wiring film 7 of the 11g1 layer.
以上のように、従来の半導体装置は形成されているため
に、第１層の７ルミ配線膜１が層間絶縁膜であるシリコ
ン酸化膜８ｙ！？形成する際に加えられる熱のために異
常膨張（一般にヒロックなどと呼ばれている）を生じ、
シリコン酸化膜８中に成長し、第２層のアルミ配線膜９
と電気的に短絡現象を生じるなどデバイスの特性を不能
にしたり、特性欠悪化させるなどの欠点があった。As described above, since the conventional semiconductor device is formed, the first layer 7 lumen wiring film 1 is a silicon oxide film 8y! which is an interlayer insulating film! ? The heat applied during formation causes abnormal expansion (commonly called hillocks),
A second layer of aluminum wiring film 9 grows in silicon oxide film 8.
This has disadvantages, such as causing electrical short-circuits and disabling the characteristics of the device, or worsening the lack of characteristics.
この発明は、上記のような従来のものの欠点を除去する
ためになされたもので１層間絶縁膜にプラズマデポジシ
ョン技術で形成できるＣ、Ｈ，Ｆを主成分とする膜（以
下プラズマ重合膜という）を用いることによってヒロッ
クの発生ケ抑制することができる半導体装置の製造方法
を提供するものである。以下、この発明の一実施例を図
面について説明する。This invention was made in order to eliminate the drawbacks of the conventional ones as described above, and it is a film mainly composed of C, H, and F (hereinafter referred to as a plasma polymerized film) that can be formed on a single interlayer insulating film by plasma deposition technology. ) The present invention provides a method for manufacturing a semiconductor device that can suppress the occurrence of hillocks. An embodiment of the present invention will be described below with reference to the drawings.
第２図はこの発明の一実施例を説明するための半導体装
置の断面略図で、第１層のフルー配線膜７を形成した後
に、例えばプラズマデポジション技術を用いてプラズマ
重合膜１１に’スルーホール領域以外の部分に形成し、
さらに、プラズマ重合！１０の上に層間絶縁膜としての
シリコン酸化膜８ン形成し、その上に第１層のアルミ配
線膜Ｔと電気的に接続されて第２層のアルミ配線膜９を
形成する。FIG. 2 is a schematic cross-sectional view of a semiconductor device for explaining one embodiment of the present invention. After forming a first layer of a wiring film 7, a plasma polymerized film 11 is formed using, for example, a plasma deposition technique. Formed in a part other than the hole area,
Furthermore, plasma polymerization! A silicon oxide film 8 is formed as an interlayer insulating film on 10, and a second layer of aluminum wiring film 9 is formed thereon to be electrically connected to the first layer of aluminum wiring film T.
このように形成すると、プラズマ重合膜１０がプラズマ
デポジション技術を用いることにより、極めて室温に近
い温度で形成が可能であり、プラズマ重合膜１０の特性
的にも安定な膜であることから、第１層のアルミ配線膜
Ｔから従来化じていたヒロックなどの異常現象を完全に
抑えることができ、電気的に極めて安定な層間絶縁膜と
なる。When formed in this manner, the plasma polymerized film 10 can be formed at a temperature extremely close to room temperature by using plasma deposition technology, and the plasma polymerized film 10 is stable in terms of characteristics. The single layer aluminum wiring film T can completely suppress abnormal phenomena such as hillocks that have conventionally occurred, resulting in an electrically extremely stable interlayer insulating film.
なお、上記の実施例では、プラズマ重合膜１０の上にさ
らにシリコン酸化Ｊｉ！８など、従来層間絶縁膜に用い
られていた膜との２層構造で示したが。In the above embodiment, silicon oxide Ji! is further applied on the plasma polymerized film 10. 8 and a film conventionally used as an interlayer insulating film.
プラズマ重合膜１０の一層構造でもよく、この一層構造
による眉間絶縁膜でも良好な特性を示す。A single layer structure of the plasma polymerized film 10 may be used, and even a glabella insulating film with this single layer structure exhibits good characteristics.
また、２層目のシリコン酸化膜８の形成方法としては、
プラズマデポジション技術のほかスパッタデポジション
技術、常圧または減圧ＣＶＤ法。Further, as a method for forming the second layer silicon oxide film 8,
In addition to plasma deposition technology, sputter deposition technology, normal pressure or low pressure CVD method.
光ＣＶＤ法によるシリコン酸化膜またはシリコン窒化膜
でもよい。また、ポリイミドなどの樹脂系絶縁膜でもよ
い。A silicon oxide film or a silicon nitride film formed by photo-CVD may be used. Alternatively, a resin-based insulating film such as polyimide may be used.
以上説明したよ５に、この発明は、半導体基板上の素子
領域と第１層のアルミ゛配線膜とを絶縁膜に形成された
コンタクト孔を介して接続した後、全面に層間絶縁膜と
して少なくともプラズマ重合膜を形成し、このプラズマ
重合膜に形成されるコンタクト孔を介して第１層のアル
ミ配線膜と第２層のフルー配線膜とを接続するようＫし
たので、熱処理時におけるアルミ配線膜からのヒロック
発生を抑えることができ、良好な絶縁性の眉間絶縁膜を
有した半導体装置が得られる効果がある。As explained above, the present invention connects the element region on the semiconductor substrate and the first layer aluminum wiring film through the contact hole formed in the insulating film, and then forms at least an interlayer insulating film over the entire surface. A plasma-polymerized film was formed, and the first-layer aluminum wiring film and the second-layer flute wiring film were connected through contact holes formed in the plasma-polymerized film, so that the aluminum wiring film during heat treatment This has the effect of suppressing the occurrence of hillocks and providing a semiconductor device having a glabella insulating film with good insulation properties.
第１図は従来の半導体装置を示す断面略図、第２図はこ
の発明の一実施例を説明するための半導体装置の断面略
図である。
図中、１はシリコン半導体基板、２はフィールド酸化膜
、３はゲート酸化膜、４は多結晶シリコン膜、５はソー
スおよびドＶイン領域、６は燐を含んだシリコン酸イヒ
膜、７は第１層のアルミ配線膜、８はシリコン酸化膜、
９は第２層のアルミ配線膜、１０はプラズマ重合膜であ
る。
なお、図中の同一符号は同一または相当部分を示す。
代理人 大岩 増雄 （外２名）FIG. 1 is a schematic cross-sectional view showing a conventional semiconductor device, and FIG. 2 is a schematic cross-sectional view of the semiconductor device for explaining an embodiment of the present invention. In the figure, 1 is a silicon semiconductor substrate, 2 is a field oxide film, 3 is a gate oxide film, 4 is a polycrystalline silicon film, 5 is a source and V-in region, 6 is a silicon oxide film containing phosphorus, and 7 is a silicon oxide film containing phosphorus. 1st layer aluminum wiring film, 8 silicon oxide film,
9 is a second layer aluminum wiring film, and 10 is a plasma polymerized film. Note that the same reference numerals in the figures indicate the same or corresponding parts. Agent Masuo Oiwa (2 others)
Claims (1)
と、前記素子領域の所要のものと絶縁膜に形成されるコ
ンタクト孔な介して電気的に接続される第１層のアルミ
配線膜を形成する工程と、全面に眉間絶縁膜として少な
（ともプラズマ重合膜を形成する工程と、前記第１層の
アルミ配線膜と少なくとも前記プラズマ重合膜に形成さ
れるコンタクト孔を介して接続される第２層のアルミ配
線膜を形成する工程とを含むことを特徴とする半導体装
置の製造方法。A step of forming an element region on the main surface of a semiconductor substrate, and a first layer of aluminum wiring film electrically connected to necessary elements of the element region through contact holes formed in an insulating film. a step of forming a plasma polymerized film on the entire surface as an insulating film between the eyebrows; and a step of forming a plasma polymerized film on the entire surface as an insulating film between the eyebrows; 1. A method for manufacturing a semiconductor device, comprising the step of forming a two-layer aluminum wiring film.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8227584A JPS60225447A (en) | 1984-04-23 | 1984-04-23 | Manufacture of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8227584A JPS60225447A (en) | 1984-04-23 | 1984-04-23 | Manufacture of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60225447A true JPS60225447A (en) | 1985-11-09 |
| JPH0564464B2 JPH0564464B2 (en) | 1993-09-14 |
Family
ID=13769940
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8227584A Granted JPS60225447A (en) | 1984-04-23 | 1984-04-23 | Manufacture of semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60225447A (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653212A (en) * | 1979-10-01 | 1981-05-12 | Toray Ind Inc | Method of drawing around synthetic filament yarn |
| JPS5948929A (en) * | 1982-08-13 | 1984-03-21 | ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド | Semiconductor device |
-
1984
- 1984-04-23 JP JP8227584A patent/JPS60225447A/en active Granted
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5653212A (en) * | 1979-10-01 | 1981-05-12 | Toray Ind Inc | Method of drawing around synthetic filament yarn |
| JPS5948929A (en) * | 1982-08-13 | 1984-03-21 | ウエスタ−ン・エレクトリツク・カムパニ−・インコ−ポレ−テツド | Semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JPH0564464B2 (en) | 1993-09-14 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| EXPY | Cancellation because of completion of term |