JPS60224248A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To omit activator treatment of Pt when copper or tin is plated on a diffused barrier plated layer, by providing a Pt layer on the diffused barrier layer of a bump electrode, and providing a tin plated layer at the outside of the bump electrode. CONSTITUTION:A bump is formed on a field oxide film 2, which is formed on a semiconductor substrate 1. An Al electrode pad 3 is formed at a part, where the bump is to be formed. A passivation film 4 is formed by a CVD method. Then, a through hole is provided on the Al electrode pad 3. Thereafter, an Al layer 10 is evaporated on the entire surface of the substrate 1. Then, Ti11 and Pt12 are evaporated. Patterning of the Ti11 and the Pt12 is performed at the place, where a bump electrode is formed. A part other than a place, where the bump electrode is to be formed is coated, by a resist 7. A diffused barrier plated 8a is applied with the Al layer 10 as a conducting layer of a current. Then lead 13 is plated on the entire surface and tin 14 is plated thereon continuously.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field of the Invention) The present invention relates to a method of manufacturing a semiconductor device having bump electrodes.

(Prior Art) Conventionally, methods for forming solder electrodes of semiconductor flip chip devices include selective vapor deposition, electroplating, solder pole method, and solder dip method. T
ech, Rev Vol 34', 74, etc.

The former selective deposition method is not generally practiced because it requires a very long deposition time, it is difficult to control the thickness of the deposited film, and it requires a large investment in manufacturing equipment.

An example of a method for forming bump electrodes of a semiconductor flip chip device using the conventional electroplating method is shown in FIGS. 1(a) to 1(h).
). First, as shown in FIG. 1(a), an M electrode pad 3 is formed on a field oxide film 2 formed on a semiconductor substrate 1 at a location where a panda is to be formed, and then a CV
A passivation film 4 is grown using the D method, and a through hole is then formed on the M electrode pad 3.

Next, as shown in FIG. 1(b), the A/-Ni alloy layer 5
, Ni layers 6 are sequentially deposited.

Next, as shown in FIG. 1(e), masking is performed with a resist or the like to remove the N
The i-layer 6 is etched to expose a portion of the At--Ni alloy layer 5.

Next, as shown in FIG. 1(d), the At-Ni alloy layer 5
In the exposed areas, a resist 7 is used to cover areas other than the areas where bump electrodes will be formed using a normal photolithography process.

Next, as shown in FIG. 1(e), an At-Ni alloy layer 5 is formed.
As a current conducting layer, a υ copper plating layer 8 gold is plated by electroplating. This copper plating layer 8 usually has a thickness of about 10 μm.

Thereafter, as shown in FIG. 1(f), non-damping is performed to form bump electrodes of the non-damping layer 9. The thickness of this solder is about 40 to 60 μm.Next, as shown in FIG. -,
Remove each with enchantment.

Finally, as shown in Figure 1 5), it is usually 340 to 350
The non-damaged layer 9 is melted at a temperature of .degree. C. to make the disc-shaped bump electrode into a hemispherical shape.

Here, the intermediate metal layer A7-Ni alloy layer 5 is a metal that adheres to the field oxide film 2 and the M electrode pad 3, and the intermediate metal layer Ni 6 and the copper plating layer 8 are made of AI! Electrode pad 3
This is a diffusion barrier layer that prevents mutual diffusion between the oxide layer 9 and the oxide layer 9. Here, the copper plating layer 8 will be referred to as a diffusion barrier plating layer.

The manufacturing method shown in FIG. 1 has two drawbacks. One of them is that when forming the diffusion barrier plating layer 8, since the underlying layer is the Ni layer 6, it is necessary to perform treatment with an activator to remove oxides on the Ni surface. If this activator treatment is insufficient, oxides remain and adversely affect adhesion strength. Moreover, if the treatment time is not long, Ni will be etched too much and the diffusion effect will not be even greater.

Therefore, this activator treatment is very difficult to control, and it is preferable not to perform it in order to simplify the manufacturing process. Note that since the non-damping layer 9 can be formed continuously after the diffusion barrier plating layer 8, activator treatment is not required. Another drawback is that the At-Ni alloy layer 5 shown in FIG. The problem is that the non-damaged layer 9 is etched together in the removal process. If the solder plating layer 9 is etched, the solder bump spheroidization process shown in FIG. As a preventive measure, there is a method of covering the bump electrodes with resist, but since the height of the bump electrodes is about 40 μm, photorining cannot be performed well.

As shown in FIG.
Although the metal configuration of sn is illustrated, other representative metal configurations include Ti-Cu-Ni-Pb/Sn, Cr-Cu
-Ni-Pb/Sn.

In these cases as well, Ni plating is performed on the underlying vapor deposited film Cu, but copper (a surface activator treatment step is required). sn is also etched at the same time, which adversely affects bonding reliability.

In addition, in the case of the solder ball method or )-under dip method, a diffusion barrier plating layer is also required, and activation treatment must be performed (However, in these methods, when removing the current conductive layer of the plating) There is no need to worry about your data being etched). In addition, bonding reliability is adversely affected.

(Object of the invention) The object of the invention is to
When performing i-plating, there is no need for Pt activator treatment, which simplifies the manufacturing process and provides a highly reliable barrier effect. It also allows for spheroidization treatment with high yield, making it possible to attach free lag chips to the substrate. An object of the present invention is to obtain a method for manufacturing a semiconductor device that can improve the reliability of bonding.

(Summary of the Invention) The main point of this invention is that PT is used in the diffusion barrier layer of the bump electrode.
This is because a tin plating layer is provided on the outside of the bump electrode.

(Example) Hereinafter, an example of the method for manufacturing a semiconductor device of the present invention will be described based on the drawings. Figures 2(a) to 2(color) are process explanatory diagrams of one example.
) to Fig. 2(h), Fig. 1(a) to Fig. 1(h)
) The same parts will be described with the same reference numerals.

First, as shown in FIG. 2(a), an M electrode pad 3 is formed on a field oxide film 2 formed on a semiconductor substrate 1 at a location where a bump is to be formed, and then a passivation film is formed using a CVD method. After growing the 1M electrode pad 3, a through hole is formed on the electrode pad 3.Next, as shown in FIG. Deposit layer 10.

Next, as shown in FIG. 2(0), after patterning with resist, Ti 11-Pt 12 is deposited, and then the resist is dissolved with a solvent such as acetone to form bump electrodes. Ti 11-
Perform Pt 12 patterning.

Next, as shown in FIG. 2(d), a resist 7 is used to cover the area other than the area where the bump electrode will be formed using a normal photolithography process.

Next, as shown in FIG. 2(e), using the M layer 10 as a current conductive layer, a diffusion barrier plating layer 8 is formed by electroplating.
Plate a. This diffusion barrier plating layer 8a may be copper or nickel. This diffusion barrier plating layer 8
The thickness of a is usually about 10 μm.

Next, as shown in FIG. 2(f), the entire surface is plated with lead 13.
Then, tin plating 14 is performed continuously. Lead plating 13
The ratio between the thickness of the tin plating 14 and the thickness of the tin plating 14 is determined from the required solder composition. Generally, the composition of solder is Pb
/5n=90/1o is used.

Next, as shown in Fig. 2 □□□), after removing the plating resist 7 with an ordinary solvent, such as acetone,
The pure M layer 10 of the current conducting layer is etched with a common M etchant used in the semiconductor industry, ie, a mixture of phosphoric acid, nitric acid, glacial acetic acid, and water. The surface of the bump electrode is covered with tin plating 14.
is not attacked by a mixed etchant of cynic acid, nitric acid, glacial acetic acid, and water.

Next, as shown in Figure 2 (color), the temperature is usually 340 to 350℃.
The lead plating layer 13 and the tin plating layer 14 are respectively melted and alloyed with solder at a temperature of .

In this invention, AJ! Layer 10 is a plated current conducting layer, T
The i layer 11 serves as a metal adhesion to the field oxide film 2 and the M electrode pad 3, the Pt layer 12 serves as a diffusion barrier plating layer between the M electrode pad 3 and the solder plating layer 9, and the copper plating or Ni plating serves as the diffusion barrier plating layer. fulfill.

(Effects of the Invention) As described above, in the present invention, since the PT layer is provided in the diffusion barrier plating layer, Pt activator treatment is not required when performing copper or Nl plating for the diffusion barrier plating layer.

In addition, instead of using alloy solder plating for plating the bump electrode, tin plating is performed continuously after lead plating to cover the outside of the bump electrode with tin, so when etching the current conductive layer, it is difficult to etch the current conductive layer. Even with an etchant mainly composed of phosphoric acid, the current conducting layer can be etched without damaging the bump electrodes. Therefore, by eliminating the need for activator treatment, it is possible to simplify the manufacturing process and provide a highly reliable barrier effect, and the bump electrodes are not attacked when etching the current conducting layer, resulting in a high yield. Spheroidization processing can be performed, increasing the reliability of flip-chip bonding to substrates.

[Brief explanation of drawings]

1(a) to 1(h) are process explanatory diagrams of the conventional bump electrode forming method, respectively, and FIGS. 2(a) to 2(h) are respectively illustrations of the process of manufacturing a semiconductor device of the present invention. It is a process explanatory diagram of one Example. 1... Semiconductor substrate, 2... Field oxide film, 3...
...Aluminum electrode pad, 4...Passivation film, 7
...Resist% 8a...Diffusion barrier plating layer, 9
...Solder plating layer, 10...Aluminum layer, 11...
・Ti layer, 12... pt layer, 13... lead plating layer,
14...Tin plating layer.

Claims (1)

[Claims] A process of covering the semiconductor substrate with an insulating film other than the area where the protruding electrode is formed, a process of depositing a plated current conductive layer on the entire surface of the semiconductor substrate, and a process of depositing Ti and PT on the area where the protruding electrode is to be formed. a step of sequentially depositing the PTFE by vapor deposition; a step of applying current to the current conducting layer to form a diffusion barrier plating layer of copper or nickel on the PT; and a step of plating lead on the diffusion barrier plating layer; A method for manufacturing a semiconductor device comprising the step of plating tin on the lead plating.