JPS60219817A - Digital-analog converter - Google Patents

Abstract

PURPOSE:To simplify a D/A converter by inputting a digital signal to a preset counter and outputting a pulse width signal proportional to an output of the counter. CONSTITUTION:A digital signal DATA to be converted into an analog signal is inputted sequentially in parallel with the preset counter CNT1, the counter is converted sequentially at a prescribed period tf repetitively and after the counter value reaches a preset value, the time width tw up to the period tf is outputted sequentially to form the pulse width tw in response to the input digital signal into an analog signal. The constitution of the D/A converter is extremely simplified.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an apparatus for converting a digital quantity into an analog quantity, and particularly relates to a converting apparatus of a type in which the analog quantity is obtained as a pulse width.

(2) Prior Art When converting a digital signal into an analog signal, highly accurate conversion can be achieved by treating the digital signal as a pulse amount and outputting the result, that is, the analog amount as a pulse width. This type of conversion device uses pulse density modulation (P
Various devices have been proposed for converting a digital signal subjected to NM) or pulse code modulation (PCM) into a pulse width.

However, in order to use this type of device, complex processing must be performed to convert the output digital signal into a PNM or PCM signal.

Therefore, for example, when a microcomputer wants to output the contents of its memory as an analog signal, it must read the contents of the memory and output a signal modulated according to the contents to a predetermined output port, which takes time. Furthermore, if this processing is performed by hardware, the hardware configuration becomes complicated.

(2) Purpose of the Invention The present invention can be used without special modulation processing. It is an object of the present invention to provide a pulse width modulation type digital/analog conversion device with a simple configuration.

(2) Structure of the Invention For example, in a counter having a function of presetting data, the time it takes for the count value to reach a predetermined value after presetting the data changes depending on the value of the data to be preset. Therefore, by using such a counter, input parallel digital data can be directly converted into pulse width.

Furthermore, if the input digital data is held using a latch circuit, and this data is compared with the counted value of a counter, the time required for the counted value of the counter to match the held data can be reduced. , corresponds to the value of the data applied to the latch. Therefore, even with this type of circuit element, parallel digital data can be converted into pulse width.

■Example Hereinafter, the present invention will be described in detail with reference to the drawings.

One digital/analog converter is shown in FIG. 1a. See Figure 1a. CLOC is the input terminal for the clock pulse, DAT^ is the input terminal for the digital data to be converted (4 bits in this example), OE is the signal output permission control input terminal, and OUT is the analog signal (pulse width modulation pulse).
This is the output terminal of

The counter CNTl used in this example is an up counter with a preset function. Terminals R8T, PRE, and CL provided in [CNT] are respectively reset (function to inhibit counting and clear the counted value) signal input terminal, and preset (DI, D2, D3, and D4 data as the initial value of the counter). function to set) signal input terminal,
and an input terminal for a clock pulse signal to be counted.

A simple explanation of the functions of the main components is the divide-by-1 circuit DV.
D generates the timing of each cycle of the conversion operation, the Nant gate NAI determines whether the count value of the counter CNT1 has reached a predetermined value, and the AND gate ANI controls the counting function of the counter.

FIG. 1b shows the signal timing of each part of the circuit of FIG. 1a. The operation will be explained with reference also to FIG. 1b. When using this circuit, the signal output permission control input terminal ○E should be set to high level H, and a fixed periodic clock pulse should be sent to the terminal C.
Apply to LOCK. The frequency divider circuit DVD divides the clock pulse to generate a fixed-cycle timing signal SGl having a relatively long cycle.

When this timing signal SGI is at a high level H, a reset level is applied to the reset terminal R8T of the counter CNT1, and the count value of the counter CNT1 is cleared to zero.

After this, when the signal SGI changes to low level L, this is applied to the monomulti MM via the inverter TNI,
This generates preset strobe signal SG2. When the signal SG2 is generated, the value of the 4-bit input data applied to the data terminals Do, DI, D2 and D3 of the counter CNTl is set as the initial value of the count value.

When the signal SGI changes to low level, the counter CNT
Since the reset of l is released, the counter CNTl is
Counting of pulses applied to the clock input terminal CLK via the AND gate ANI is started. At the start of this counting, the counter CNT 1 has already been set to a value that matches the 4-pinto input data as a count value.

In this example, the Nant gate NAI has a counter CNTl
The count value of rl, 1. I am constantly checking whether it matches L and IJ. Normally, the output level of NAND gate NAI is high level, but the count value rl, 1, 1 . At IJ, the output level of NA1 becomes low level L. This is K
Therefore, AND gate AN1 closes and counter CNT1
No clock pulses are applied to.

When the time tf has elapsed since the counter CNT1 started counting, the signal SGI is inverted to high level H.

The counter CNT1 is reset again and the count value is cleared to 0. The level of the output terminal OUT is set during the period when the output terminal of the Nant gate NAI is at a low level L, that is, after the count value of the counter CNT1 reaches a predetermined value, the level of the output terminal OUT is changed to the next signal SG.
It is at a high level during the period tv until I changes to a high level, and is at a low level during the other periods.

In other words, the level of the output terminal OUT changes at a cycle of 2tf in synchronization with the timing of the signal SGI, and in each cycle, the level of the output terminal OUT is at a high level H for a period tv.
is proportional to the value of data preset in the counter CNT1. In this example, when the preset data is 0, the setting is such that the time from when the counter CNT 2 starts counting until the counted value reaches the set value of NAI is set to be tf. Therefore, the signal obtained at the output terminal OUT becomes a pulse signal, that is, an analog quantity, having a pulse width corresponding to the input digital data.

Note that this embodiment has an analog signal output permission control function, but if this is not required,
The AND gate AN2 shown in the figure is unnecessary. In addition, in this embodiment, the data is preset, that is, the digital signal is read at each cycle of the timing signal S01.1 For example, when connecting this converter to a microcomputer, the preset terminal is connected to the output port of the microcomputer. may be connected to control the preset pulse to be output at the timing of outputting digital data. In that case, the inverter INI and mono-multi MM become unnecessary. Furthermore, when a microcomputer is used, the frequency divider circuit DVD can be omitted.

FIG. 2 shows another embodiment. Referring to FIG. 2, this circuit includes a digital comparator 171&c:MP and a latch LA. Further, the counter CNT2 does not have a preset function.

A latch LA holds the digital data input into this circuit. A terminal SET of latch LA is a strobe signal input terminal for latching data.

The digital comparator CMP has an input terminal AI of the A group,
A2. Digital data applied to A3 and A4 and B
Group input terminals Bl, B2 . It compares the digital data applied to B3 and B4 and outputs the result. When the two match, the output terminal rA=BJ becomes a high level H.

Therefore, in this embodiment, the counter CNT2 starts counting from 0 for each cycle of the timing signal generated by the frequency divider circuit DVD. When the count value of the counter CNT2 matches the digital data held in the latch LA, the output terminal of the digital comparator CMP becomes a high level H, and counting of the counter CNT2 is prohibited. That is, in this embodiment, instead of changing the preset value, the set value for determining the count value is changed. Therefore, by the same operation as the circuit shown in FIG. 1a, an analog signal having a pulse width corresponding to input digital data is output.

(2) Effects of the Invention As described above, according to the present invention, digital/analog conversion can be performed using a circuit with a very simple configuration, and there is no need to perform special signal processing such as modulation during use.

[Brief explanation of the drawing]

FIG. 1a is an electric circuit diagram showing one embodiment of the present invention, and FIG. 1b is a timing chart showing signal waveforms of the circuit shown in FIG. 1a. FIG. 2 is an electrical circuit diagram showing another embodiment of the invention. CNT15 counter (counting means child signal holding means) CNT
22 counter (counting means) DVD: Frequency divider circuit (timing means) NAI: NAND gate (comparison means) CMP: Digital comparison Im (comparison means) LA 2 latch (
Signal holding means) ANI, AN3: AND gate (counting inhibition means) Me1b
Country

Claims (3)

[Claims] (1) Counting means for counting clock pulse signals of a predetermined period; Timing means for clearing the count contents of the counting means at a predetermined period longer than the clock pulse; Signal holding means for holding an input digital signal; A digital/analog conversion device comprising: a comparison means for comparing a count result of the counting means with a predetermined value; and a counting prohibition means for prohibiting counting by the counting means when the comparison results of the comparison means match. (2) The counting means and the signal holding means are a preset counter, and the comparison means is a logic gate circuit that compares the output signal of the preset counter with a predetermined value. A digital/analog conversion device according to claim 1. (3) The comparison means is a digital comparison circuit that compares the output signal of the counting means and the output signal of the signal holding means. A digital/analog conversion device according to claim (1).