SU754330A1 - Device for monitoring digital-analogue converter parameters - Google Patents

Description

The invention relates to digital-analog computing and can be used to control the parameters of digital-to-analog converters.

Known control devices integrated circuits, sotsderzhaschie generator ⁵

the set of signals connected through the switch mode of operation, the converter analog-code, matching unit and the transmitter with the input of the display unit, the comparison unit connected to the reference voltage source and to the input of the control unit £ ΐ].

The disadvantage of this device is a large range of commands issued to the inputs of the tested circuits, and a large range of reference voltages connected to the comparison unit (when controlling output parameters using a calculator, a large amount of permanent memory is required ^.

A device for monitoring the parameters of electrical circuits is known.

2

A constant voltage reference voltage source connected via a key to one of the terminals of two reference elements, the outputs of which through a switch are connected to a controlled circuit and the inputs of the integrator and differentiator whose outputs are respectively connected to the inputs of two threshold circuits, the outputs of the threshold circuits are connected via logic to the output of the device , and a control unit with a key and a switch I.

The disadvantages of the device include the inability to check on this device more complex electrical circuits, as well as the presence in the device of the reference elements.

The purpose of the invention is to expand the functionality of the device and improve the accuracy of control.

This goal is achieved by

that the device containing the control unit-differentiator switch

and a two-threshold circuit whose output

3

754330

four

connected to the first input of the logic circuit; a binary pulse counter, a matching unit, an amplifier, a storage unit, a multi-input logic circuit and a clock generator connected to the second input of the logic circuit, the output of which is connected to the input of the binary pulse counter and the output of the control unit, are input multi-input. the logic circuit and the matching unit are connected to the outputs of the binary pulse counter, and the output of the matching unit is connected to the input of the digital-to-analog converter, the output of which is through the differentiator, amplifier and storage unit are connected to the first input of the switch, the second input of which is connected to the output of the digital-to-analog converter; the output of the multi-input logic circuit is connected to the control input of the switch, the output of which is connected to the input of the two-threshold circuit.

Functional diagram of the device shown in the drawing.

The generator 1 clock pulses output connected to the first input of the logic circuit 2, the output of which is connected to the input of the binary counter 3.

The discharge buses of counter 3 are connected to the inputs of matching unit 4 and to the inputs of a multi-input logic circuit 5 that implements the function of equivalence: -the output of this circuit forms a logical unit only when all the discharge buses of the counter have either zeroes or ones.

The input of the controlled DAC 6 is connected to the output of the matching unit 4, and the output is connected to the input of the differentiator 7, the output of which is connected to the input of the storage unit 9 through a pulse amplifier 8.

Switch 10, switching signals from the outputs of blocks 6 and 9, the output is connected to a two-threshold circuit 11 that performs the function of the device tolerance control. The output of the circuit 11 is connected to the inhibit input of the logic circuit 2. The output of the control unit 12 is connected to the input of the counter 3.

In the initial state, the counter 3 is in the zero state when zeros are set on the bit buses, as a result, the output of the circuit 5 is set to the potential of the logical unit by which the switch 10 is set in such a state that to the input of the circuit 11

the output of the controlled HAII 6 is connected. The voltage at the output of the monitored DAC is zero, i.e., its input through the matching unit 4 from the output of · counter 3 receives a code, all of which have zeros.

At the output of the two-threshold circuit 11, a “not normal” signal is set, which prevents the passage of clock pulses from generator 1 through circuit 2.

In this state, the scheme remains until the beginning of the test.

To begin testing from the output of control unit 12, a single pulse is applied to the input of counter 3, resulting in a unit level in the low-order discharge, and a logic zero level at the output of circuit 5, under the action of which switch 10 is triggered and to the input of a two-way circuit 11 connects the output of the storage unit 9.

In addition, the binary code through the matching unit 4 is fed to the input of the controlled DAC 6.

The matching unit 4 eliminates the effect of the binary counter transient on the process of establishing the voltage at the output of the DAC. This is achieved by the fact that information to the input of the DAC from the output of the matching device is fed synchronously in time over all code buses. As a result, the DAC keys controlling the operation of the decoding matrix are switched simultaneously and, thus, their operation is coordinated in time.

After a single pulse has been applied to the input of the counter 3, a verification code is set up on its code buses, in the low-order bit of which there is a one, and in the remaining digits it is zero. When a verification code arrives at the input of the tested D / A converter, a voltage jump dts appears at its output, corresponding to the weight of the low-order bit, and at the output of the differentiator 7 a pulse is generated with the amplitude dc.

The gain K of the amplifier 8 is selected from the ratio K-2 ^p -1, where P is the number of bits of the controlled DAC.

In this case, the output of the pulse

amplifier 8, an amplitude pulse arises and d 6 and (ι ¹¹ ~ 4) ·

The amplitude of the output pulse is memorized by block 9, as a result of which

five

6

7ί

at its output a constant voltage is established by the value of i) _ei) y.

The resulting voltage and _b1 * * corresponds to the maximum voltage at the PAP output when setting the maximum verification code at its input, in all digits of which there is one. This circumstance makes it possible to use the same two-threshold circuit with a constant value of the tolerance field A both for controlling the maximum output voltage of the DAC and for controlling the minimum increment of the output voltage dO.

In this case, the parameters of the circuit 11 are selected so that when a controlled voltage is found within the limits of the tolerance field and ry * 1 D, the "norm" signal is formed.

Voltage I) circuits from the output of the storage device 9 through the switch 10 is fed to the input of the two-way circuit 11. If the voltage is O e, b, h ~

-k is within the specified tolerance, the output of the circuit 11 forms a ²⁵ "norm" signal, under the action of which the prohibition is removed from the logic circuit

2. In this case, the output of the clock generator 1 through the circuit 2 to the input of the counter 3 receives the second clock ³⁰ pulse, under the action of which the next increment of L11 occurs at the output of the DAC, which again differentiates, is remembered and evaluated again by the circuit 11. Noah verification of the DAC proceeds cyclically until the output of the counter 3 of the maximum verification code, which has units in all digits.

40

..If in the verification process in the discharge kakomlibo a1) does not correspond to the allowable value, the output circuit 11 is formed by the signal "not normal", the circuit 2 is locked and checking osganav- ⁴⁵ Lebanon.

When the maximum code appears at the output of the DAC, the voltage A ^ OUT 'appears, ^{and at the} output of circuit 5 there appears a unit, under the action of which ⁵⁰ switch turns on and connects the output of the DAC to the input of the two-threshold circuit 11. When the "normal" signal appears, the next clock pulse counter 3 is set to zero position, and the signal "not the norm" appears at the output of circuit 11. In this case, the test ends, and the scheme is set to its original state.

ten

Claims (1)

Claim A device for controlling the parameters of a digital-to-analog converter, co- ¹⁵ holding control unit, differentiator, switch and two-threshold circuit, the output of which is connected to the first input of the logic circuit, different heme, that, in order to (2rash ² θ rhenium functionality of the device and improve the accuracy of control, it introduced a binary pulse counter, matching unit , an amplifier, a storage unit, ^one multi-input logic circuit and a clock generator coupled to the second input of the logic circuit whose output is connected to the input binary pulse counter and the output sound control unit The inputs of the multi-input logic circuit and the matching unit are connected to the outputs of the binary pulse counter, and the output of the matching unit is connected to the input of the digital-to-analog converter, the output of which is connected to the first input of the switch, the second input of which is connected to the output of the digital-analog converter, the output of the multi-input logic circuit is connected to the control input of the switch, the output of which is connected to the input of the two-threshold circuit.