JPH042222A - One-bit d/a converter - Google Patents

Abstract

PURPOSE:To simplify the constitution, to facilitate monolithic circuit integration and to attain high speed and highly accurate analog conversion by comparing an input digital.data with the counted value of a serial clock.pulse, and converting the data into the pulse width of a PWM waveform. CONSTITUTION:An input data inputted from a bus line at the time of starting a processing cycle is latched tentatively in a latch circuit 2. On the other hand, a counter 3 starts counting clock.pulses at the time of starting the processing cycle. The counted value of the counter 3 and the input data are compared by a digital.comparator 4 and when the counted value exceeds the input data, the output of a PWM conversion circuit 5 having so far been at an H level is inverted to an L level, and the L level is latched up to the end of cycle. The output of the PWM conversion circuit 5 is integrated by a low pass.filter and the result is outputted as an analog waveform. Thus, the circuit constitution is simplified, the monolithic circuit integration is facilitated and high speed and highly accurate analog conversion is implemented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a 1-bit D/A converter capable of converting an input digital signal into an analog signal.

[Prior art] Conventionally, D/A converts digital signals into analog signals.
Known converters include a weighted resistance or current type, a resistor voltage division type, a current or voltage addition type, and a segment current type.

[Problem to be solved by the invention]

However, in the conventional method described above, accuracy, miniaturization,
It had advantages and disadvantages in terms of monolithic IC, etc., and was not necessarily a sufficient/A converter.

SUMMARY OF THE INVENTION An object of the present invention is to provide a 1-bit D/A converter that has a simple configuration, can be easily fabricated into a monolithic IC, and can perform analog conversion with high precision.

[Means to solve the problem]

In order to achieve the above purpose, the present invention includes a counter that counts input clock pulses for each processing cycle and is cleared when a predetermined number corresponding to the cycle end is counted, and a binary counter that is input from a hash line. A latch circuit that captures and holds input data consisting of numerical values at each start of a processing cycle, a digital comparator that compares the binary numerical value held in the latch circuit with the count value of the counter, and outputs the comparison result;・Based on the comparison result of the comparator, the period from the start of the processing cycle until the count value exceeds the input value is set to H level output, and the other periods are set to L level output.
It is characterized by comprising a WM conversion circuit and a low-pass filter that integrates the output signal of the PWM conversion circuit.

[Operation] Since the present invention is configured as described above, the input data input from the bus line at the start of a processing cycle is temporarily held in the latch circuit. On the other hand, the counter starts counting clock pulses at the beginning of a processing cycle. The count value of the counter and the input data value are compared by a digital comparator, and when the count value exceeds the input data value, PW, which was at H level until then,
The output of the M conversion circuit is inverted to L level and the cycle begins.

The L level is maintained until the end. The output of the PWM conversion circuit is integrated by a low-pass filter and output as an analog waveform.

〔Example〕

Embodiments of the present invention will be described below based on the drawings.

In this embodiment, input digital data consisting of 16 bits is converted into analog data and outputted every time the maximum value FFFF clock pulses are counted. The specific configuration of the embodiment, as shown in FIG. 1, includes a strobe detection circuit 1, a counter circuit 2, a counter 3, a digital comparator 4, a JK flip-flop 5, and the like.

Next, the operation of each part will be explained with reference to the timing chart of FIG.

In FIG. 1, each part other than the digital comparator 4 uses the clock C while the clear signal CLR is at L level.
The operation proceeds sequentially according to LK.

When strobe signal ST1 is input, strobe detection circuit 1 outputs enable signals El and E2 at the rising timing of clock CLK.

The enable signal E1 is at the H level for one pulse of the first clock CLK every unit data exchange cycle, and is sent to the latch circuit 2. Enable signal E2 is always at H level and sent to counter 3 while clear signal CLR is at H level.

The specific configuration of this strobe detection circuit 1 is shown in FIG.

The latch circuit 2 includes 16 D flip-flops, and while the enable signal E1 is input, the 16-bit data D0 is sent from the outside as a D/A input.
~DI5 is latched at the timing when the first clock CLK falls, and continues to be sent to the digital comparator 4 until the next processing cycle.

The counter 3 is composed of 16 bits, counts the clock CLK while the enable signal E2 is at H level, sends the count value C0 to CIS to the digital comparator 4, and when the count value reaches FFFF, the counter 3 counts the clock CLK while the enable signal E2 is at H level. Send out signal 0.0 to JK flip-flop 5.

As shown in FIG. 3, this counter 3 is constructed by connecting 4-bit counters 31 to 34 to form a 16-bit counter.

The digital comparator 4 compares the input latch data Q0 to Qrs with the count values 00 to CI5, and keeps the output at H level until the sequentially increasing count values 00 to CI5 exceed the latch data Qo -QCs. When it exceeds the level, it is inverted to the L level and sent to the JK flip-flop 5.

The JK flip-flop 5 receives the H level output signal of the digital comparator 4 from the beginning of the processing cycle and holds the output Q at the H level. Next, when the output of the digital comparator 4 is inverted to the L level, the output Q is inverted to the L level at the rising timing of the next clock CLK and held until the end of the processing cycle, and finally returned to the H level by the run layout signal C90. do.

The output of the JK flip-flop 5 is a PWM signal whose duty ratio is the ratio of the size of the 16-bit input data to the maximum value FFFF of the 16-bit binary numerical value. By inputting the second PWM signal to a low-pass filter (not shown) and integrating it, an output signal having an analog waveform is obtained.

With the above configuration, 16-bit data from the D/A input is captured at the timing of the enable signal E1 in each processing cycle when the clock CLK counts FFFF times, and is processed as a PWM signal with a pulse width proportional to the data value. Output.

An analog waveform is obtained by simply integrating this PWM signal using a low-pass filter.

2, in the above embodiment, the value of the input digital data is compared with the serial or lock pulse count value and converted to the pulse width of the PWM waveform, so the circuit configuration is relatively simple. Furthermore, since no special circuit components are required, it is easy to form a monolithic IC.

Furthermore, the conversion process is highly accurate because the analog exchange follows the clock pulse count-up.

In particular, the D/A converter of this embodiment is suitable for medical equipment and the like that do not require very high conversion speed.

Note that although the embodiment has shown an example of converting digital data consisting of 16 bits, it is also possible to convert other 8-bit, 32-bit data, etc. in the same way.

〔Effect of the invention〕

As explained above, according to the present invention, the input digital data is compared with the count value of the 4° lock pulse every processing cycle, and a PWM waveform proportional to the magnitude of the input data value is output. Furthermore, since it is converted to an analog waveform by a low-pass filter and output, the circuit configuration is simplified and monolithic ICs are used.
This makes it easier to Further, since analog conversion is performed in units of clocks for each processing cycle, extremely high precision conversion is possible.

[Brief Description of the Drawings] Figure 1 is a circuit diagram showing the overall configuration of the embodiment, Figure 2 is a circuit diagram showing the specific configuration of the strobe detection circuit, and Figure 3 is the specific configuration of the counter. The circuit diagram and FIG. 4 are timing diagrams showing the operation. 1... Strobe detection circuit 2... Latch circuit 3
...Counter 4...Digital comparator
5...JK flip flop. Figure 2

Claims (1)

[Claims] (1) The input clock pulses are counted for each processing cycle, and the counter is cleared when a predetermined number corresponding to the end of the cycle is counted, and the input data consisting of a binary value input from the bus line is counted for each processing cycle. A latch circuit that captures and holds data at each start, a digital comparator that compares the binary value held in the latch circuit with the count value of the counter and outputs the comparison result, and a processing cycle based on the comparison result of the digital comparator. A PWM conversion circuit that outputs an H level during the period from the start of the count value until the count value exceeds the input numerical value and outputs an L level during the other periods, and a low-pass filter that integrates the output signal of the PWM conversion circuit. A 1-bit D/A converter featuring: