JPS60214058A - Memory access control circuit - Google Patents

Abstract

PURPOSE:To improve the throughput of a data processing system by performing partial write with a data buffer and a store buffer to make it possible to execute partial write with a minimum burden. CONSTITUTION:A data transfer means 5 is started by a data processing system 1 and transfers data from a data buffer 3 to a store buffer 4. Overwriting is performed for bytes to be partially written when data of an address to be overwritten is transferred from the data buffer 3 to the store buffer 4 by the data transfer means 5, and this overwritten data is written from the store buffer 4 onto a memory unit 2 overall.

Description

Detailed Description of the Invention (al) Technical Field of the Invention The present invention relates to a data processing device having a memory unit, a store buffer for the memory unit, and a data buffer. The present invention relates to a memory access circuit that performs control to avoid partial write operations as much as possible.

(b) Background of the Technology Memory access in general data processing systems is mainly byte access.

However, in order to improve the throughput of data processing systems, the data transfer width (word length) for the memory unit is
is on a trend of becoming longer and longer.

Therefore, in order to perform the above-mentioned byte access to a memory unit with a long data width (word length), partial writing is necessary, and the frequency of occurrence of partial writing will continue to increase in the future. Therefore, a measure is desired to reduce as much as possible the reduction in processing capacity of the data processing system due to the partial writing.

Furthermore, in recent data processing systems, in order to improve processing performance, the number of devices (eg, central processing units, channel devices, etc.) that access memory units is increasing, such as in the construction of multiprocessor systems.

Therefore, in order to efficiently access memory from a plurality of devices, it is necessary to minimize the busy rate within the memory unit.

For this reason, there is a need for a memory access method that reduces the busy rate of the memory unit that occurs when a partial write occurs in a central processing unit, etc., which is commonly used in the past. was.

On the other hand, in large-scale data processing systems, in order to improve processing performance, the main storage device (memory unit) and the data processing system (central processing unit, channel device, etc.) A buffer is provided, frequently used data and programs are transferred to this data buffer, and when the program is running, only this buffer memory can be accessed, reducing the appearance from the data processing system's perspective. The above method is used to shorten the memory access time. This focuses on the locality of memory addresses accessed when executing a program, and in normal data processing, the hint rate for the data buffer is currently quite high.

Furthermore, in order to perform store processing to the memory unit,
By providing a store buffer between the data processing system and the memory unit, and providing a buffer function to handle busy conditions that occur within the memory unit, the apparent speed of the above store processing from the data processing system's perspective is achieved. ing.

However, in a large data processing system, when a partial write is required, just as in the case of a full write to a memory unit, data is shortened by the word length of the memory unit and data corresponding to the write position is written. Send a byte mark, look at the byte mark in the memory unit,
Generally, a partial write operation is performed, and there is a problem that the overhead in the memory unit is large.

The present invention is based on the fact that the hit rate for the data buffer when memory access is performed from the data processing system is actually quite high, the access time in this case is short, and there is a store buffer, so that the data processing system can easily access the data buffer. Focusing on the apparent high speed of the above store processing, when a partial write is required in the data processing system, data existing in the data buffer is used to write data between the data buffer and the store buffer sofa. The idea was to perform the partial writing.

(C) Prior Art and Problems FIG. 1 is a diagram showing the configuration of a conventional data processing system, where 1 is a data processing system, which may also be a central processing unit or a channel device. 2 is a memory unit (main memory) and 3 is a data buffer.

31 is a fetch control unit, 4 is a store buffer, and 41 is a store control unit.

Data read from the memory unit 2 is provided to the data processing system 1 via the data buffer 3. Data written from the data processing system 1 to the memory unit 2 is transferred to the C memory unit 2 via the store buffer 4.

-i, since the unit of access to memory unit 2 (i.e. data width, e.g. 8 bytes, 16 bytes, etc.) is larger than the processing unit of data processing system 1 (e.g. 1 byte), the store data is A mark (anus) is added, and the memory unit 2 looks at the byte mark (BM) and performs either a partial write process [the byte mark (BM) is not all "1"] or a full write process [the byte mark (BM)]. (
BM) is all 1'', and then executes the write process.

FIG. 2 is a time chart schematically showing the operation when the data processing system 1 accesses the memory unit 2, in which (a) shows the operation at the time of fetch;
(b) shows the operation at the time of storage, and (C) shows the operation at the time of partial write. ■ is the fetch control unit 21
(2) is an operation in the memory unit 2, and (2) is an operation in the store control unit 31. Also, (1) is a memory read operation within the memory unit 2, (2) is an editing operation for partial writing, and (3) is a memory read operation within the memory unit 2.
It shows the memory write operation within.

As is clear from this diagram, the operation in memory unit 2
is characterized in that it is much longer than the access operation (2) to the data buffer or the access operation (2) to the store buffer.

In particular, the partial write shown in (c) requires two memory accesses within the memory unit 2: read (1) and write (3).

For this reason, in a data processing system that frequently performs partial writing, there is a problem in that the throughput of the memory unit 2 decreases, and the performance of the data processing system is degraded, including the impact on other systems.

In addition, if there is data at the address for partial writing in the data buffer 2, in order to avoid partial writing, if all writing is performed using that data, the data processing system will also handle unnecessary data. Therefore, there was a problem that overhead occurred in the data processing system.

(d) Object of the Invention In view of the above-mentioned drawbacks of the conventional art, the present invention focuses on the fact that the access time to a data buffer or store buffer is extremely short compared to the access time to a memory unit. The purpose of this invention is to provide a method for performing partial writing, which was previously processed in the above, using the data buffer and store buffer.

According to the present invention, the present invention provides an apparatus having a memory unit, a store buffer sofa and a store control circuit for the memory unit, and a data buffer, and a data processing system for operating these. , providing means for transferring data from the data buffer to the store buffer sofa upon activation from the data processing system, independently of the operation of the data processing system after activation, and using the data transfer means,
This is achieved by providing a method for controlling the partial write operation to the memory unit so that it becomes a full write operation, and the partial write that occurs in the data processing system can be executed with a minimum burden on the data processing system. There are advantages.

(fl Embodiments of the Invention First, to summarize the gist of the present invention, the present invention has a memory unit, a store buffer and store control circuit for the memory unit, and a data buffer, and a data processing system that operates these. In the apparatus having the apparatus, means is provided for transferring data from the data buffer to the store buffer upon activation from the data processing system, and the data transfer means transfers data at an address for partial writing from the data buffer to the store buffer. At that point, overwrite the byte you want to partially write, or transfer the overwritten data to the store buffer for the byte you want to partially write in the data buffer, and then All stored data is written from the store buffer to the memory unit.

Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 3 is a block diagram showing an embodiment of the present invention, and 1, 2, 3, 31, 4, and 41 are the same as those explained in FIG. 1, and 5 is an embodiment of the present invention. When the data transfer means necessary to transfer the data receives the control information A from the data processing system 1 and starts the data transfer, the control information A (
Transfer start buffer address.

Based on the transfer destination store buffer address, the number of transfer bytes, etc.), data of the number of transfer bytes is read from the transfer start address of the data buffer 3, and one take is transferred to the transfer destination address of the store buffer 4.

When a partial write is executed in the data processing system 1, the control information A is immediately sent to the data transfer means 5 when a data block containing the data is present in the data buffer 3.

Based on the control information A, the data transfer means 5 operates to read the current data from the data buffer 3 and transfer it to the store buffer 4.

In the data processing system 1, when the transfer of the data by the data transfer means 5 is completed, the store buffer 4 is accessed using the byte mark and the partial write data necessary for the partial write, and the transferred data is It operates so as to overwrite the partially written data at the hide position specified by the height mark in the data.

Subsequently, in the data processing system 1, when the above-mentioned overwriting is completed, a store request is sent to the store control unit 41.

Based on the store request signal, the store control unit 41 reads the latest data in the store buffer 4 (this data is the overwritten write data) and stores all the data in the memory unit 2. works.

Therefore, according to the present invention, when a partial write is executed, the data read from the write address and the editing operation for the partial write, which were conventionally executed in the memory unit, are performed in the data buffer 3. Data transfer means 5. This is executed in the store buffer 4, and the control unit controls the memory unit 2 so that it is a normal full store process, so that no deterioration in performance occurs due to data read and edit operations within the memory unit.

If the data processing system 1 executes a partial write and the data at the address does not exist in the data buffer 3, the control information A is not sent to the data transfer means 5 and the normal partial write is performed. controlled so that

Therefore, after sending the word address, hide mark, partial write data, etc. necessary for partial writing to the side store buffer, the memory unit 2 operates to send a store request to the store control section 41. , data read, data edit, and data write operations are
Since the processing is executed according to the time chart shown in FIG. 2(c), the overhead in the memory unit 2 increases. However, in a data processing system having the data buffer 3 as described above, there is a very high probability that the target data exists in the data buffer.
Most partial writing is performed using the processing mode of the present invention, and its effects are significant.

In particular, in the processing of input/output processors, etc., data that has been read out to the data bus sofa is often rewritten, and the present invention is a very effective means.

In the present invention described in detail above, the overwrite request and store request operation after data transfer from the data buffer 3 to the store buffer 4 are the same as the partial write request operation in the conventional method from the perspective of the data processing system 1. Therefore, by implementing the present invention, the additional operation in the data processing system 1 is only the activation of the data transfer described above (i.e., the operation of sending out the control information A).
It has the characteristic that there is almost no increase in the burden on

In this embodiment, the data buffer 3 is treated as a read-only memory, but it goes without saying that it may have a structure that allows normal writing.

In this case, data can be edited on the data buffer 3. Therefore, after performing partial writing on the data buffer 3, it is also possible to transfer the data from the data buffer 3 to the store buffer 4.

In this way, the data editing process (specifically, partial writing) necessary to implement the present invention may be performed using the store buffer or the data buffer, but this does not impede the gist of the present invention. It goes without saying that this is true.

(g) Effects of the Invention As explained in detail above, the memory access control circuit of the present invention has a memory unit, a store buffer and a store control circuit for the memory unit, and a data buffer, and operates the memory unit. In an apparatus having a data processing system, means is provided for transferring data from the data buffer to the store buffer upon activation from the data processing system, and the data transfer means transfers data from the data buffer at an address for partial writing. At the time the data is transferred to the store buffer, the bytes to be partially written are overwritten, and the overwritten data is completely written from the store buffer to the memory unit. Partial writing can be performed in the data processing system with a minimum burden on the processing system, and the processing capacity of the data processing system can be improved.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing the configuration of a data processing system using a conventional method, Fig. 2 is a time chart showing the operation when a memory unit is accessed using the conventional method, and Fig. 3 is a diagram showing the present invention. 1 is a block diagram illustrating an embodiment of the present invention. In the drawing, 1 is a data processing system, 2 is a memory unit, 3 is a data buffer, 31 is a fetch control section, 4 is a store buffer, and 41 is a store control section. 5 indicates a data transfer means, and A indicates control information for the data transfer means 5, respectively. spear l day

Claims (1)

[Claims] In an apparatus having a memory unit, a store buffer and a store control circuit for the memory unit, and a data buffer, and a data processing system that operates these, the data processing system after startup is activated by the data processing system. Independently from the operation, a means for transferring data from the data buffer to the store buffer is provided, and using the data transfer means, a partial write operation to the memory unit is controlled to become a full write operation. A memory access control circuit featuring: