JPS63280355A - Information processor - Google Patents

Abstract

PURPOSE:To quickly perform processing by transferring block data in accordance with the conceptual execution order of an instruction, which issues an operand read-out request, at the time of absence of block data in plural buffer memories from which data can be read out simultaneously and independently of one another. CONSTITUTION:Operand addresses calculated in accordance with preceding and succeeding instructions in the conceptual execution order are sent to buffer memories 201 and 202, and a block transfer request signal circuit 301 (302) generates a block transfer request signal if a buffer data read-out request is issued but data is absent in buffers. When this signal is generated from the circuit 301 (302), a precedence deciding circuit 305 prefers the request from the memory 201 and sends a corresponding request signal to a main storage 3 and transmits it to a block transfer monitor circuit 306 to suppress following data write.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an information processing device, and in particular, to obtain high-speed processing operation by simultaneously processing two or more instructions that read operands from a storage device and perform arithmetic operations. The present invention relates to an information processing device suitable for the purpose of the present invention.

[Conventional technology]

Conventionally, as a method for processing multiple operand read requests at the same time, there is a method of providing multiple buffer memories, for example, as disclosed in ``About rFLATS cache memory'', p. 115 of Proceedings of the Information Processing Society of Japan Section 27 Annual Conference. is proposed.

[Problem that the invention seeks to solve]

For example, the above conventional technology can be applied to a general-purpose computer 111TAc.
- When applied to simultaneous multiple memory operand read requests from multiple instructions of a computer that processes consecutive instructions sequentially, such as a series.

It is necessary to adhere to the architectural convention that the order of memory reads must be equivalent to being performed according to the conceptual order of the instructions to be executed. Therefore, if block data absence, which is a factor that disturbs the memory read order, occurs in one or more buffer memories, the memory operand read request or buffer memory read request corresponding to the subsequent instruction of the instruction that caused the block data absence, or the block Data transfer needs to wait until the first block data absence occurs, that is, the block data transfer ends.

An object of the present invention is to process memory operand read requests by a plurality of conceptually consecutive instructions in accordance with the conceptual execution order of the instructions and as simultaneously as possible, thereby increasing the efficiency of memory operand reading, thereby achieving high-speed operation. Our goal is to provide an information processing device that can.

[Means for solving problems]

In order to have multiple buffer memories and read out multiple consecutive instructions in an order that does not violate the execution order of the corresponding instructions, it is necessary to read instructions when block data is absent in the buffer memory. The simplest control method is to obtain information corresponding to the conceptual execution order of instructions indicated by order information, perform block data transfer according to this order, and suppress buffer memory read requests for subsequent instructions until the transfer is completed. It's a method.

[Effect]

The plurality of buffer memories are provided for memory operands of a plurality of instructions, and each operates independently in response to a read request signal from the instruction processing device. As a result, memory operand reading is performed independently in the processing of each instruction.
Processing is performed at high speed without delay caused by referencing operands and waiting.

Furthermore, due to the operation of the block transfer order control circuit,
Even when block data absence occurs simultaneously at different block addresses in several of the multiple buffer memories, the order of block data transfers is performed without violating the conceptual execution order of the corresponding instructions, so that operand references to main memory are Order is guaranteed.

〔Example〕

An embodiment of the present invention will be described below with reference to FIGS. 1, 2, 3, and 4.

FIG. 4 shows an example of the overall configuration of an information processing device using the present invention, where 1 is an instruction processing unit, 2 is a buffer memory unit, 3 is a main memory, 201°202'' is a buffer memory, and 203 is a buffer memory. This is a control circuit. FIG. 2 shows an example of the configuration of the instruction processing unit 1.
01 and 102 are instruction registers, 103 is a general-purpose register group, 104 and 105 are address adders, IOE, 107 are instruction decoders, and 108 and 109 are arithmetic units.

In the instruction processing unit 1, JP-A-58-17F1751
As disclosed in , the instruction register 101 is set with an instruction whose conceptual execution order precedes, and the instruction register 102 is set with an instruction whose conceptual execution order is subsequent. The 0241 part of the first instruction word stored in the instruction register 101 is decoded by the instruction decoder 106, the instruction code is sent to the arithmetic unit 108, and from the contents of the general-purpose register group 103 specified by the 841 part and the 041 part, Address adder 1
04 to calculate the operand address.

In parallel with this, the second
The instruction decoder 107 decodes the 0P82 part of the instruction word of BS2. and sends the instruction code to the arithmetic unit 109. D#
The operand address is calculated from the second part using the address adder 105. Two operand addresses of 0 or more and each buffer data read request signal are sent to the buffer memories 201 and 2 using signals [41 and 51, respectively.
Send on 02.

Furthermore, the buffer data read request signal and the operand address of signals 11A 41 and 51 are sent to the buffer memory control circuit 203.

The buffer data read request signal is sent to the buffer memory 201.
If data corresponding to the requested address exists in at least one of both buffer memories when reaching step 202, the buffer memory transfers the data to the instruction processing unit for processing using the signal line 42 or 52. At the same time, the data-in-buffer signal is set to rtO'' and is sent to the buffer memory control circuit 203 using the signal line 63 or 66.

If buffer data is missing in at least one of the buffer memories 201 or 202, the buffer memory in which the data is missing sets the buffer data missing signal to "1".
'' and sends it to the buffer memory control circuit 203 using the signal line 63 or 66. After the block transfer described later is performed and the necessary data is obtained from the main memory 3, the requested data is sent to the buffer memory control circuit 203 using the signal line 63 or 66. It is sent to the arithmetic units 108 and 109 of the instruction processing unit 1 using the line 42 or 52.

FIG. 3 shows an example of the configuration of the buffer memory control circuit 203. 211 is a BS block address generation circuit, 212 is a replacement array, 213 is a block transfer control circuit, 214 is a buffer memory write control circuit, and 215 is a replacement array update i-way. In addition, below, r
"BS block" refers to an area on the buffer memory corresponding to a predetermined block length on the main memory, and "BS block address" refers to the address of the BS block on the BS. memory 2
01 to signal line 63. The buffer memory 202 receives and receives the buffer data presence signal via the signal line 66.

FIG. 1 shows an example of the configuration of the block transfer control circuit 213. 301 and 302 are block transfer request signal generation circuits 3
03 and 304 are block transfer request holding circuits, 305 is a block transfer request priority determining circuit, 306 is a block transfer letter 7IIil monitoring circuit, and 307 is a block transfer end determining circuit.

When the buffer data present signals received and received via the signal lines 63 and 66 are both “0”, the buffer memory control circuit 203 controls the replacement array 21
Only 2 updates are performed.

The BS block address generation circuit 211 receives data via the signal line 41. A BS block address is determined based on the operand address corresponding to the first instruction and sent to the replacement array update circuit 215. Upon receiving the BS block address, the replacemen 1 to array update circuit 215 uses a conventional LRU algorithm to update the contents of the replacement array 212 so that the block indicated by the BS block address is the most recently used block. Next, the replacement array 212 is updated in the same manner as described above for the operand address corresponding to the second instruction received via the signal line 51. The replacement array has a much faster processing capacity than the main memory and buffer memory, and uses high-speed storage elements to sequentially perform the above two updates during one buffer memory reference time.

When a buffer data read request is sent via the signal line 41, and the data-in-buffer signal on the signal line 63 becomes '1' accordingly.

Alternatively, when a buffer data read request is sent via the signal line 51 and the buffer data present signal becomes '1' via the signal line 66, that is, the buffer data read request signal and the buffer data When both the presence signals are "1", block transfer from the main memory 3 to the buffer memories 201 and 202 is performed. When the above conditions are met, a block transfer request signal is generated in the block transfer request signal circuit 301 or 302 and sent to the block transfer request holding register 303 or 304 via the signal line 601 or 602. When the block transfer request holding register 3o/1 receives the block transfer request signal, it receives a reset instruction from the block transfer state monitoring circuit 306 along with the operand address sent via the signal line 41 or 51. Until there is
This is held and subsequent data writing is inhibited. In addition, the held block transfer request operand addresses are connected to signal lines 603 and 604, or signal lines 605 and 60.
6, the block transfer request priority determination circuit 30
5 continuously. The block transfer request priority determination circuit 305 determines that the block transfer request is
01 and 202, in this embodiment, the preceding instruction is always placed on the left side, so the left side is prioritized, that is, the buffer corresponding to the first instruction that is conceptually preceding in execution order. It gives priority to the request from the memory 201, generates a corresponding main memory read request signal, and sends it to the main memory 3 together with the operand address.At the same time, the block transfer state indicates that the block transfer to the buffer memory 201 is currently being executed. Signal line 6 for monitoring circuit 306
21 to convey the message.

However, at this time, if two BS block addresses for which block transfer is requested belong to the same block on the main memory, the request is recognized as one.

Note that in this embodiment, since the instructions with the preceding conceptual execution order are placed on the left side during instruction decoding, by giving priority to the left side when determining the priority, block transfer requests are issued in accordance with the conceptual execution order. It will be done.

In parallel with sending the main memory read request signal, the BS block address generation circuit 211
In response to the request, the replacement array 212 sends a replacement request signal to the BS block address that is to be replaced.
After that, the replacement array update circuit 215 sends the block address to the replacement array 21.
2 in the same way as above. BS block address generation circuit 211 sends the BS block address to buffer memories 201 and 202 using signal line 92.

When the main memory 3 receives the read request signal and address, it simultaneously sends the data corresponding to the address to the buffer memories 201 and 202 via the signal line 8.
The in-block address corresponding to the data being sent to the buffer memories 201 and 202 is sent to the buffer memory write control circuit 214 via the signal line 72, and The 9-buffer memory write control circuit 214, which is informed of the completion of reading of the memory, communicates with the buffer memories 201 and 2 via the signal line 91.
02, the corresponding BS block internal address and buffer write instruction signal are sent. After the main memory 3 receives the read request signal, the buffer memories 201 and 20
The series of operations from sending data to the block 2 to sending the buffer write instruction signal is repeated a number of times corresponding to one block length while increasing the main memory read address by a predetermined increment. When the buffer memories 201 and 202 receive the buffer write instruction signal, the data sent from the main memory 3 is written to an address position uniquely determined by the combination of the BS block address and the address within the BS block. . Also, buffer memory 2
When 01 first receives data corresponding to the address requested to be read from the instruction processing unit 1 from the main memory, it sends the data to the instruction processing unit 1 via the signal line 42.

When the block transfer based on the series of requests from the buffer memory 201 is completed, the block transfer completion determination circuit 307 operates, and the transfer of one block is completed to the block transfer status monitoring circuit 306 via the signal line 622. Let me know. The block transfer request S monitoring circuit 306 uses the signal line 611 to block transfer request holding register 303
(Ft line 613 is used to notify the block transfer request priority determination circuit 305 of the end of the block transfer requested from the buffer memory 201. When the block transfer request priority determination circuit 305 detects this, , accepts a block transfer request from the buffer memory 202 corresponding to a second instruction that is later in conceptual execution order.Thereafter, a series of block transfers starting with a data read request to the main memory is performed in the same manner as above. Later, the buffer memory 202 sends out data corresponding to the address requested to be read from the instruction processing unit 1 using the signal line 52.

Further, when the block addresses for which block transfer is requested from the buffer memories 201 and 202 are the same, the block transfer to the buffer memory 202 is not performed and only data is sent to the instruction processing unit 1.

Block transfer request is from buffer memory 201 or 202
If the request is issued from only one of the two, the block transfer request priority determination circuit 305 unconditionally accepts the request, and the corresponding block transfer is performed.

In addition, in the BS block address generation circuit, in order to synchronize with the operation of the block transfer control circuit 213,
A priority determination circuit similar to 305 is provided.

In the instruction processing unit 1, the arithmetic units 108 and 109 input the data sent from the buffer memory to the signal line 4.
2 and 52, the instruction decoder 1
A predetermined operation is performed based on the instruction codes sent from 06 and 107, and the result of the operation is sent via signal lines 111 and 112 to the instruction registers R#1 and R#2 of instruction registers 101 and 102. It writes to the general-purpose register group 103 in accordance with the value.

Furthermore, the arithmetic units 108 and 109 send out arithmetic unit busy signals via the signal lines 121 and 122 until the arithmetic operations are completed. The arithmetic unit busy signals are logically summed by an OR gate and sent to the instruction registers 101 and 102 via signal lines 123 and 124. When the instruction registers 101 and 102 receive the arithmetic unit busy signal, they inhibit the setting of subsequent instructions.

As described above, reading and block transfer are performed in an order corresponding to the conceptual execution order of instructions. Note that the instruction execution order is not disturbed due to a delay in calculation, and the contents of the buffer memories 201 and 202 are always the same.

〔Effect of the invention〕

According to the present invention, even if block data is absent in different blocks at the same time in a plurality of buffer memories, block transfer is performed in an order corresponding to the conceptual execution order of instructions.

Furthermore, conventionally, when the required data does not exist in the buffer memory, it takes a very long time to transfer the data from the main memory to the buffer memory.

Compared to a method in which independent data is stored in multiple buffer memories, when multiple memory operand addresses exist in the same block in main memory, the memory operand data required for one block transfer is Since the information is obtained on each buffer memory, this has the effect of making it possible to speed up instruction processing.

Note that simulations have revealed that there is a very high probability that each memory operand of a plurality of consecutive instructions exists in the same block on the main memory.

Memory reading is conventionally a time-consuming process, but according to the present invention, the processing time can be significantly shortened, which is very effective.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a schematic configuration diagram of a block transfer control circuit according to the present invention. Figure 2 is a schematic diagram of the instruction processing unit;
FIG. 3 is a schematic configuration diagram of a buffer memory control circuit when the present invention is utilized, and FIG. 4 is a schematic configuration diagram of an information processing apparatus when the present invention is utilized.

Claims (1)

[Claims] 1. It has a plurality of buffer memories composed of a plurality of blocks, which can be read independently and simultaneously when operand read requests are made by a plurality of instructions at the same time; An information processing apparatus comprising block data transfer order control means that transfers block data when block data is absent in a plurality of blocks in accordance with the conceptual execution order of the instruction that issued the operand read request. 2. The information processing device further comprises instruction word decoding means for simultaneously decoding a plurality of consecutive instructions and issuing an operand read request corresponding to the plurality of instructions to each of the plurality of buffer memories. Range 1
The information processing device described in the section. 3. The information processing apparatus according to claim 1 or 2, further comprising buffer memory control means for controlling the contents of the plurality of buffer memories to be the same.