JPH06149673A - Cache control system - Google Patents

Abstract

PURPOSE:To suppress waiting for the end of replacing processing due to a preceding cache mishit and the drop of cache efficiency due to slashing. CONSTITUTION:A cache memory CM consists of a directory part CM2, a data part CM3 for reading out and storing a part of data from a main memory MM and a cache control part CM1 for controlling data reading or the like to/from the memory MM in accordance with accesses from plural processors P and the control part CM1 is constituted of a data control part for transmitting/receiving a block to/from its corresponding processor P when address information obtained from the processor through the 1st network B1 is a cache hit and a replacing processing part for replacing the block to the memory MM through the 2nd network B2 at the time of generating a cache mishit. Thereby even when a preceding access generates a mishit, the continuous execution of the succeeding access is permitted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention is a computer provided with a cache memory, which is accessed from the processor and stores a part of the stored contents of the main memory, between the processor and the main memory connected by a network. hand,
The present invention relates to a cache control method in which a cache miss hit process for a preceding access to the cache memory is provided with a bypass means that does not block a subsequent access. For example, a single processor system for pipeline processing or multi-threat processing, or The present invention relates to a cache control method suitable for a multiprocessor system sharing a cache memory.

[0002]

2. Description of the Related Art Conventionally, when a cache memory is used in a computer, a preceding memory access from a processor causes a cache mishit, and a block replacement process between the main memory and the cache memory due to the mishit occurs. A so-called blocking cache method that does not accept the subsequent memory access is adopted during the process, but a processor that can issue the next memory access without waiting for the end of the preceding memory access (for example, , A processor for pipeline processing or multi-threat processing), or a cache that can be explicitly cached by the processor (such as a cache controller that accepts multiple access information in advance). Prior access or capture It is possible to adopt a so-called non-blocking cache method that allows the processor to continue executing the next access even if the access accompanying the cache operation causes a cache miss hit. preferable.

By the way, conventionally, as a block replacement processing (replacement) method, an LRU (least-rec) is used to expel the oldest used block.
ENTLY-USED) method is often adopted, and in addition to this, the FI for expelling from the block stored first
Some of them use the FO method.

[0004]

However, when the non-blocking cache method using the above-described conventional block replacement processing method is adopted, the cache
There is a need to resolve the cache entry contention problem for allocating blocks in the cache that correspond to missed accesses.

When the conventional data update processing method is used, a certain block is replaced according to the above-mentioned replacement processing algorithm, but cache miss hits are successively made to different blocks having the same set address. When the error occurs, there is a problem in that the data fetch is not yet completed, and therefore, the situation may occur in which the block for which the replacement process is not completed and the service for the access is not completed becomes the replacement target. It was In order to solve all of these problems with hardware, a complicated and huge control circuit is needed, which is not economical.

On the other hand, when a non-blocking cache system is adopted in a parallel computer to perform the mishit processing in parallel, if the degree of parallelism becomes large, the mishit processing in executing a plurality of mishit processings in parallel. Since the order of completion and the order in which the mishit processing is started do not always match due to the network processing time and the like, update processing algorithms that use history information such as the LRU method and the FIFO method cause thrashing to the cache. However, there is also a problem that the performance of the entire system cannot be fully exhibited. For example, as shown in FIG. 5, three processors (P0, P
1, P2) and a cache memory with two ways (W0, W1), the processor P0 accesses addresses A0, A1, A2 in the same block, and the processor P1 accesses the above addresses A0, A1. , A2
Address B of the same block different from the block containing
0, B1, B2 are accessed, and the processor P2 includes the block including the addresses A0, A1, A2 and the address B.
Consider the case of accessing addresses C0, C1, C2 of the same block other than the block containing 0, B1, B2. In this case, since the number of different blocks is 3 and the number of ways is 2, the access request time is represented by Q, and the replacement process completion time is represented by A, (12, 10, 7, 13,
11, 14, 8), the other replacement process (25, 16, 27, 18, 20, 29, 31) is performed immediately after each update process completion A. Thrashing will occur.

An object of the present invention is to use a non-blocking cache method and to replace a block which is performing a data block replacement process associated with a preceding cache mishit, until the replacement process is completed. The present invention is to provide a highly economical cache control method that can suppress the cache efficiency decrease due to thrashing without using the cache control method.

[0008]

In order to achieve this object, the first characteristic configuration of the cache control system according to the present invention is as follows.
When the subsequent access causes a cache hit, the bypass means determines that the data block replacement process is completed based on the value of the status flag that is set for each cache entry and indicates the completion or incompletion of the data block replacement process. It is configured to permit the execution of the service for the access when the determination is made. In the above-mentioned configuration, when the subsequent access to the bypass means causes a cache miss, it is determined that the data block replacement process is not completed in all ways in the same set based on the value of the status flag. It is preferable that the access be interrupted at times.

[0009]

According to the first characteristic configuration, a status flag indicating completion or incompletion of the block replacement process set for each cache entry is set in, for example, the directory portion of the cache memory, and subsequent access is prevented. When there is a cache hit, the bypass means determines whether or not the block replacement processing corresponding to the preceding access is completed based on the status flag, and when the block replacement processing is completed, the access from the processor is handled. By doing so, it is possible to avoid the replacement by the subsequent access during the block replacement processing corresponding to the preceding access. Furthermore, when a subsequent access causes a cache miss, when it is determined that the block replacement process corresponding to a plurality of preceding accesses in all ways in the same set is incomplete based on the value of the status flag. By interrupting the access, frequent block replacement processing, that is, occurrence of thrashing is avoided. In this case, the processor whose access has been suspended continues its processing while avoiding the occurrence of thrashing by performing processing such as stopping access to the cache for a certain period of time.

[0010]

As described above, according to the present invention, in the block replacement process associated with a cache mishit, a cache entry that is a candidate for the replacement process is reserved for the preceding update process when the candidate is determined. It is guaranteed that it is not an entry, which simplifies the control circuit of the block replacement process and prevents the cache efficiency from degrading due to thrashing. Therefore, a cache control method that can improve the throughput of the entire system is provided. It is now available.

[0011]

EXAMPLES Examples will be described below. As shown in FIG. 3, a shared cache memory CM connected to the plurality of processors P0, P1, P2 via the first network B1 is provided, and these cache memories CM are connected to the main via the second network B2. A computer C is configured by being connected to the memory MM.

The cache memory CM has a directory section CM2, a data section CM3 for reading and storing a part of data from the main memory MM, and the main memory MM corresponding to accesses from the plurality of processors P. And a cache control unit CM1 that controls reading and writing of data between the two and the like, and constitutes a 2-way set-associative cache memory.

The directory unit CM2 has a capacity corresponding to the number of sets and the number of ways, and as shown in FIG. 2, each unit is an address tag unit CM21 that represents the position of corresponding data on the main memory MM. That is, a block address, whether the way is allocated as a block indicated by an address tag, that is, a valid bit V that indicates whether data is valid or invalid, and a status bit that indicates whether the replacement process of the block is completed. Including B,
The attribute section CM20 indicates the attribute of the block allocated to the way. Here, the effective bit V
Is reset by a control signal indicating that the consistency of the data transmitted from the main memory MM cannot be maintained,
The status bit B is a flag that is set when a block is allocated as a target of the replacement process, that is, when the replacement process starts, and the status bit B is a flag that is set when the replacement process starts and reset when the replacement process ends.

The cache control unit CM1 compares the address information obtained via the first network B1 with the block address of the address tag unit T, and the comparison unit determines that the addresses match. If the valid bit V is set (hereinafter,
In the case where the data transfer control unit and the comparison unit that exchanges the relevant block with the processor P determine that they do not coincide with each other (referred to as “cache hit”) or the valid bit V is reset (hereinafter, referred to as “cache hit”). (Hereinafter referred to as "cache miss hit"), a replacement processing unit that performs a block replacement process on the main memory MM via the second network B2, and a logic circuit that controls the operations thereof. Even if the preceding access from the processor P causes a cache miss, a so-called non-blocking cache method is adopted which permits the subsequent access to be executed continuously.

More specifically, when the subsequent access causes a cache hit and the status bit B of the block is reset, normal service is performed, that is, the corresponding data is exchanged with the processor P, Status bit B
During the replacement process in which is set, the process for the access is suspended, and after the status bit B is reset, the normal service, that is, the exchange of the corresponding data with the processor P is performed. Further, if a way in which the status bit B is reset in the same set when a subsequent access causes a cache miss hit, normal service is provided for the way, that is, a block is provided for the main memory MM. When the replacement process is performed and the status bits B of all the ways in the same set are set, the processor P is notified that all the ways are busy via the first network and the access is interrupted. Let In other words, for the 7 states that occur due to the combination of the valid bit V and the state bit B of each way when a cache miss hit occurs, the way for which data is to be updated is appropriately selected as shown in FIG. For example,
Any of the ways may be selected in the state 1, and the state 4
Then, the way is selected by the LRU method. Incidentally, "-" in the figure indicates that it may be ON or OFF. In states 5 and 6 in which both the valid bit V is set, the way in which the state bit B is reset is selected, and in state 7 in which both the valid bit V and the state bit B are set, both ways are selected. There is no such thing.

In the cache memory CM constituted by the ways W0 and W1, for example, the processor P0 accesses addresses A0, A1 and A2 in the same block BLA, and the processor P1 is in the same block BLB different from the above block A. B0, B1, B2 of the block BLA, the processor P2 accesses the addresses C0,
When accessing C1 and C2 (the number of different blocks is 3
The number of ways is 2), as shown in FIG. 4, the access request time is represented by Q, the access request completion time including replacement is represented by A, and (6, 9, 1
When a cache miss hit occurs for each of the access requests Q generated in the order of 2), first the way W
0, the replacement process for the access request Q (6) is started (at this time, the valid bit V of the address tag portion T concerned).
And the status bit B is set), and the way W1 is issued to the access request Q (6) generated during the replacement process.
The replacement process is started at this time (at this time, the valid bit V and the status bit B of the address tag portion T are similar to those described above.
Is set). When a new access request Q (12) is generated while the replacement processing is being performed on both ways W0 and W1, the status bit B is set for all the ways to the processor P2 which issued the access request Q (12). Is notified and the access is suspended.
The processor P2 whose access has been interrupted avoids thrashing by waiting while performing internal processing without accessing the cache memory CM for a predetermined time (which is not particularly limited and can be set as appropriate), and then again. The access request Q (13) is issued.

That is, the valid bit V, the status bit B, and the cache control unit CC indicate the completion or non-completion of the replacement process set for each cache entry when the subsequent access causes a cache hit. When it is determined that the replacement processing is completed based on the value of the status flag, the execution of the service for the access is permitted, and when a subsequent access causes a cache miss, the same set is set based on the value of the status flag. It becomes a bypass means for interrupting the access when the replacement process is judged to be incomplete in all the ways.

Another embodiment will be described below. The bypass means described in the above embodiment is a processor that can issue the next memory access without waiting for the end of the preceding memory access (for example, a processor for pipeline processing or multi-threat processing is applicable), Alternatively, it can be appropriately used for a cache in which an explicit cache operation by a processor (corresponding to one in which a cache controller accepts a plurality of access information in advance corresponds), and further for a parallel computer.

[Brief description of drawings]

FIG. 1 is an explanatory diagram of a replacement permission / prohibition state based on values of a valid bit V and a state bit B.

FIG. 2 is a block diagram of a tag array section.

FIG. 3 is a block configuration diagram of a main part.

FIG. 4 is a timing chart of access from a processor.

FIG. 5 is a timing chart of access from a processor showing a conventional example.

[Explanation of symbols]

 CM cache memory MM main memory P0, P1, P2 processor

Claims (2)

[Claims] 1. A computer having a cache memory, which is accessed from the processor and stores a part of the stored contents of the main memory, between the processor and the main memory connected via a network, the computer comprising: In the cache control method in which the cache mishit processing for the preceding access of (1) provides a bypass means that does not block the subsequent access, the bypass means is provided for each cache entry when the subsequent access causes a cache hit. A cache control method configured to permit execution of a service for the access when it is determined that the block replacement process is completed based on a value of a status flag indicating completion or incompletion of the block replacement process that is set. . 2. The bypass means, wherein when the subsequent access is a cache miss hit, it is determined that the data update processing is not completed in all ways in the same set based on the value of the status flag. 2. The cache control method according to claim 1, wherein the cache access method is configured to interrupt the access.