JPS60213061A - Charge transfer device - Google Patents

Abstract

PURPOSE:To enable charge transfer at high speed by small power consumption by forming a thin layer having a conduction type reverse to a semiconductor substrate having one conduction type on the upper surface of the substrate and providing a means completely depleting the thin layer and shaping a charge transfer elctrode on an insulating film formed on the thin layer. CONSTITUTION:When voltages are applied in three-phase pulses of phi1=phi3=0 and phi2= positive and there are signal charges under a phi2 electrode, reverse bias voltage 303 is increased sufficiently, and P type semiconductor thin layer 302 is depleted completely. A series capacitance of the capacitance of SiO2 102, the capacitance of the depleted P type thin layer and the capacitance of a depleted N substrate is obtained at that time. Since the capacitance of the depleted N substrate can be designed arbitrarily in a small value when donor concentration is lowered, a capacitance viewed from the electrode can also be reduced arbitrarily. The capacitance of potential in the depth direction under phi1, phi3 electrodes can be minimized arbitrarily when the donor concentration of the N substrate is lowered similarly. Signal charges transfer under the phi3 electrode on the right side of the phi2 electrode when phi1=phi2=0 and phi3 is brought to positive potential, and signal charges transfer under the phi1 electrode on the right side of the phi3 electrode when phi2=phi3=0 and phi1 is brought to positive potential.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a charge transfer device that can perform charge transfer with low power consumption.

(Prior art and its problems) CCD (Charge Coupled Device)
It is a device in which multiple MO8N capacitors are arranged continuously on the surface of an eM semiconductor with no gaps between them, and these MO8 capacitors have the function of storing charge and the function of moving it, and can be used as an imaging device, a signal Used in processing devices, memory devices, etc. The CCU has a surface channel structure and a buried channel structure, and their basic structures are shown in Figure 1, respectively.
It is expressed as shown in FIG. Figure 1 shows the surface channel CC
A metal electrode having the structure D, 104 is a means for wiring metal to the pole 103, φl, φ2 . φ3 is a three-phase pulse applied to the metal electrode 104. Also, Fig. 2 11
! 201 is an N-type silicon thin film layer, 202 is a battery for applying a reverse bias between the P-type silicon substrate 101 and the Nff1 thin layer 201 formed on its upper surface, and 203 is a A lead wire connects the battery, the P-type substrate, and the ~-type silicon thin layer. Further, the reverse bias voltage is set to a magnitude sufficient to deplete the N region 105.

The operations of these CODs will be explained.

Suppose now that φl; φ3=0, a positive voltage is applied to φ2, and the signal electron is under the φ2 electrode.

Next, when a positive voltage is applied to φ3 with φl; φ2=0, the signal electrons move under the φ3 electrode, which is one position to the right of the φ2′l11 pole. Furthermore, when a positive voltage is applied to φ1 with φ2; φ3=0, the signal electrons are transferred to φl tffl one position to the right below the φ3 electrode.
Move down. The energy E that must be supplied from the power supply for these movements per transfer is calculated as follows.

E=CV 2 Here, C is the capacitance of the electrode storing signal electrons, and ■ is the voltage applied to the electrode. Here, C is the series capacitance of capacitance tC2 from the electrode to the signal electron (!:(!!) to the P substrate, so it can be written as c1+c2.

Now, in imaging devices and memory devices that use CCDs, the number of transfer stages is 500,000 to 1 million, and the area is tiO,5.
It also reaches ~lcd. Therefore, the energy required for charge transfer is extremely large (and the transfer speed is also 10 to 2
Since it is not rare for the frequency to reach 0 MHz, the amount of power required for transfer becomes extremely large.

(Object of the Invention) An object of the present invention is to provide a CCD which can improve the above-mentioned drawbacks and can perform high-speed charge transfer with low power consumption.

(Structure of the Invention) According to the present invention, there is provided a means for forming a thin layer having a conductivity type opposite to that of the semiconductor substrate on the upper surface of a semiconductor substrate having one conductivity type and completely depleting the thin layer; A charge transfer device characterized in that a charge transfer electrode is provided on the formed insulating film is obtained.

Further, according to the present invention, there is a means for completely depleting the thin NI by forming a thin layer having the same conductivity type as a thin layer having a conductivity type opposite to that of the semiconductor substrate on the upper surface of a semiconductor substrate having one conductivity type. A charge transfer device is obtained, characterized in that a charge transfer electrode is provided on an insulating film formed on the thin layer having the same conductivity type.

(Example) Hereinafter, one example of the present invention will be described using the drawings.

3 and 4 illustrate embodiments of the present invention, respectively, with FIG. 3 for a surface channel and FIG. 4 for a buried channel.

In FIG. 3, 301 is an N-type semiconductor substrate, 302 is a P-type thin layer formed on the N-type semiconductor substrate 302, and 302 is a P-type thin layer formed on the N-type semiconductor substrate 302;
03 is an N-type semiconductor substrate 301 via a lead wire 304.
and a power source for reverse biasing the P-type semiconductor thin layer 302.

Further, in FIG. 4, 401 is a hexagonal semiconductor substrate, 402
Vi P-type thin layer formed on the hemi-shaped semiconductor substrate, 40
N-type semiconductor substrate 401 via 4tilJ-do wire 404
and a power supply for reverse biasing the PM semiconductor thin layer. In addition, in FIGS. 3 and 144, the P-type semiconductor thin layer 3
02 and 402 play the same role as the P-type semiconductor substrate 101 in FIGS. 1 and 2.

First, the operation in the case of a surface channel will be explained using the potential of the P-type semiconductor as a reference (0 volts).

As the initial state, φ1=φ3=0, as in the case of FIG.
Assume that a positive voltage is applied to φ2 and there is a signal charge under the φ2 electrode. At this time, the reverse bias voltage 303 is sufficiently large P
Assuming that the type semiconductor thin layer 302 is completely depleted, φ
21m! The bottom closed pole downward potential is rg5 diagram a,
It can be expressed as b. This is the case when the amount of atd signal charge is small and the amount of bVi is large.

At this time, 1! The capacitance seen from the pole is the series capacitance of the capacitance of 8i02102, the capacitance of the depleted P-type thin layer, and the capacitance of the depleted substrate. Of these capacitances, the capacitance of the depleted substrate can be designed to be arbitrarily small by lowering the donor concentration of the substrate, so that the capacitance seen from the electrode can also be made arbitrarily small. Further, the botical in the direction of the electrode edge under the φl and φ3 electrodes is expressed as C, and its capacity t can be arbitrarily reduced by lowering the donor concentration of the N substrate, as in the case of a and b. Next, when φl=φ2=O9φ3 is set to a positive potential, the signal charge moves to the right side of the φ2 electrode and below the φ3 electrode, and further φ2=
φ3=0. When φl is set to a positive potential, the signal charge is −I! on the right side of the φ3 electrode. Move to the very bottom. Therefore, the power frequency for charge transfer is f, the low level of the transfer mill 2!1
-vL1 high level and apply voltage to the substrate to Ivζ Vs g
b, then f(l(Vsub-VL)CLI-1(Vs
ub-VH)CHI). Here, since CL and CB are capacitances when the transfer voltage is at a low level or a high level, power consumption can be extremely reduced.

In the case of a buried channel, φ1=φ3 as in the case of Fig. 2.
If a positive voltage is fully applied to Q and φ2 and the area under the φ2 electrode is depleted, the potential in the depth direction under the φ2 electrode is expressed as shown in FIGS. 6a and 6b.

aFi when there is no signal charge, b when there is the maximum signal charge, the capacitance seen from the electrode in this case is expressed as U8i02
102 and the depleted N-type thin pigeon 105 capacitance,
The capacitance of the depleted P-type thin layer 402 and the capacitance of the depleted portion of the hexagonal substrate form a series capacitance.

At this time, the capacitance of the depleted N substrate can be arbitrarily reduced by lowering the donor concentration of the N substrate! The capacitance seen from the pole can also be made arbitrarily small. Further, the potential hc in the depth direction under the φ1 and φ3 electrodes is expressed as the potential hc, and the capacitance can be made arbitrarily small as the donor concentration of the substrate is lowered by 8L.

Next, when φl=φ2=0 and φ3 is set to a positive potential, the signal charge moves below the φ311 pole on the right side of the φ2 electrode, and further φ2=
When φ3=O1φ is set to a positive potential, the signal charge moves below the φ1 electrode on the right side of the φ3 electrode. Therefore, even in the case of a buried channel, the capacitance seen from the transfer electrode can be reduced by reverse biasing the lightly doped N substrate and the P-type thin layer formed on its upper surface, and completely depleting this P-type thin layer. Therefore, as in the case of the surface channel, charge transfer of the CCD can be performed with extremely low power consumption.

(Effects of the Invention) As described above, according to the present invention, it is possible to realize a charge transfer device with extremely low power consumption for charge transfer.

In the above embodiments, the case of the H channel was explained, but it goes without saying that the principles of the present invention can also be applied to the case of the P channel. Further, in the above example, the case of three-phase drive has been explained, but it is obvious that the present invention can also be applied to four-phase drive, two-phase drive, etc.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIGS. 1 and 2 are cross-sectional structures of a charge transfer section of a conventional CCD, FIGS. 33 and 4 are cross-sectional structures of a charge transfer section of a COD according to the present invention, and FIGS. FIG. 6 shows the potential distribution in the depth direction of a cross-sectional view of the charge transfer section of the COD according to the present invention. In these figures, 101 P-type semiconductor substrate, 102 5i0
2 thin film, 103 transfer to pole 104 wiring 201 N-type semiconductor thin layer, 202 battery, 203 lead wire, 301, 401
N-type semiconductor substrate, 302.402P-type semiconductor thin layer, 3
03.403 Battery, 304.404 Wiring date - Warishun procedure amendment C'j5 Phantom Patent Office Commissioner 1, Indication of the case 1988 Patent Junko 70436
No. 2, Title of the invention Charge transfer device 3, Relationship to the amended person case Applicant 5-33-1 Shiba, Minato-ku, Tokyo (423) NEC Corporation Representative Tadahiro Sekimoto 4, Agent address 108 Resident Mita Building 5, 37-8 Shiba 5-chome, Minato-ku, Tokyo Date of amendment order July 31, 1980 (shipment date) 6 Item name 7 of the statement subject to amendment, Contents of amendment Item name `` The first page containing "Scope of Patent Claims" will be replaced with the attached one. ,,,--"-,. Description Title of the invention Charge transfer device Claim (1) - Forming a thin layer having a conductivity type opposite to that of the semiconductor substrate on the upper surface of a semiconductor substrate having a conductivity type, A charge transfer device comprising: means for completely depleting the thin layer; and a charge transfer electrode provided on an insulating film formed on the thin layer. (2) - Upper surface of a semiconductor substrate having a conductivity type. forming a thin layer having the same conductivity type as a thin layer having an opposite conductivity type to the semiconductor substrate, and completely depleting the thin layer; and an insulating film formed on the thin layer having the same conductivity type. A charge transfer device characterized by having a charge transfer electrode provided thereon.Detailed Description of the Invention (Field of Industrial Application) The present invention relates to a charge transfer device that can perform charge transfer with low power consumption.

Claims (1)

(11-Means for forming a thin layer having a conductivity type opposite to that of the semiconductor substrate on the upper surface of a semiconductor substrate having a conductivity type, and completely depleting the thin layer; and forming a thin layer on the thin layer. A charge transfer device characterized in that a charge transfer electrode is provided on an insulating film having a conductivity type. A charge transfer method, characterized in that a charge transfer electrode is provided on an insulating film formed on an insulating film having a conductivity type as described in MiJ, and a means for completely depleting the thin layer. device.