JPH03163836A - Charge coupled device - Google Patents
Charge coupled deviceInfo
- Publication number
- JPH03163836A JPH03163836A JP1303897A JP30389789A JPH03163836A JP H03163836 A JPH03163836 A JP H03163836A JP 1303897 A JP1303897 A JP 1303897A JP 30389789 A JP30389789 A JP 30389789A JP H03163836 A JPH03163836 A JP H03163836A
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- coupled device
- group
- electrode group
- upper layer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000005036 potential barrier Methods 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims description 12
- 239000000758 substrate Substances 0.000 claims description 12
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract description 4
- 230000006866 deterioration Effects 0.000 abstract description 4
- 238000000034 method Methods 0.000 abstract description 3
- 229910052681 coesite Inorganic materials 0.000 abstract description 2
- 229910052906 cristobalite Inorganic materials 0.000 abstract description 2
- 239000000377 silicon dioxide Substances 0.000 abstract description 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract description 2
- 229910052682 stishovite Inorganic materials 0.000 abstract description 2
- 229910052905 tridymite Inorganic materials 0.000 abstract description 2
- 230000001747 exhibiting effect Effects 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 230000000694 effects Effects 0.000 description 3
- 238000001444 catalytic combustion detection Methods 0.000 description 2
- 230000005684 electric field Effects 0.000 description 2
- 230000000994 depressogenic effect Effects 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 1
Landscapes
- Solid State Image Pick-Up Elements (AREA)
- Transforming Light Signals Into Electric Signals (AREA)
- Facsimile Heads (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は転送効率が良好で、かつ高密度化に適した電
荷結合素子に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge coupled device that has good transfer efficiency and is suitable for high density.
第2図(a)は従来の電荷結合素子の断面図であり、図
において、1は例えばp形の半導体基板、2は半導体基
板1上に設けられた、例えば熱酸化によ?形戒されたS
iO■膜であり、絶縁膜の働きをする。3,4,5.6
は絶縁膜2上に設けられた、例えば多結晶シリコンから
なる電極群であり、各電極間の間隔は図中Sで示され、
これにより各電極は電気的に分離されている。FIG. 2(a) is a cross-sectional view of a conventional charge-coupled device. In the figure, 1 is a p-type semiconductor substrate, and 2 is a semiconductor substrate formed on the semiconductor substrate 1 by, for example, thermal oxidation. Formally precepted S
It is an iO film and acts as an insulating film. 3, 4, 5.6
is a group of electrodes made of polycrystalline silicon, for example, provided on the insulating film 2, and the spacing between each electrode is indicated by S in the figure.
This electrically isolates each electrode.
第2図(a)の電荷結合素子は4相駆動の場合を示して
おり、電極3.4,5.6にはそれぞれクロックφl,
φ2.φ3.φ4が与えられ、この4電極がCCDの1
段に相当する。ここでφ1.φ2がクロツクHigh状
態でφ3,φ4がクロ・ンクLow状態の場合の半導体
基板1中の電子に対するポテンシャル分布を第2図(b
)に示す。図中7は転送されるべき電子を示しており、
クロツクI4ighが印加されている電極3.4下に形
成されたポテンシャルウェルに閉し込められている。電
極3,4.5.6には間隔Sが設けられているので、こ
の部分では電極から半導体基板中に及ぼす電界が弱くな
り、ポテンシャルハリアΔφが生じる。このポテンシャ
ルバリアΔφは転送効率を劣化させる要因となる。この
様子を第2図(C)を用いて説明する。第2図(C)は
第2図(b)の状態からφ3をHigh状態、φ1をL
ow状態とし、電荷をl電極分だけ転送させた状態のポ
テンシャル分布を示す。同図に見られるようにポテンシ
ャルバリアΔφのために電極3下に残留電荷8が生し、
転送効率が劣化することになる。The charge-coupled device in FIG. 2(a) shows the case of four-phase drive, and the electrodes 3.4 and 5.6 have clocks φl and φ1, respectively.
φ2. φ3. φ4 is given, and these four electrodes are one of the CCDs.
Corresponds to a stage. Here φ1. Figure 2 (b) shows the potential distribution for electrons in the semiconductor substrate 1 when φ2 is in the clock high state and φ3 and φ4 are in the clock low state.
). 7 in the figure indicates the electrons to be transferred,
It is confined in a potential well formed under the electrode 3.4 to which the clock I4high is applied. Since the electrodes 3, 4, 5, 6 are provided with a spacing S, the electric field exerted from the electrodes into the semiconductor substrate becomes weak in this portion, and a potential halia Δφ occurs. This potential barrier Δφ becomes a factor that deteriorates transfer efficiency. This situation will be explained using FIG. 2(C). Fig. 2(C) shows that φ3 is in the High state and φ1 is in the L state from the state of Fig. 2(b).
The potential distribution is shown in the OW state and the charge is transferred by l electrodes. As seen in the figure, a residual charge 8 is generated under the electrode 3 due to the potential barrier Δφ,
Transfer efficiency will deteriorate.
この問題を解決する手段として一般に広く用いられてい
る方法がオーバラップ電極構造と呼ばれるもので、その
構造を第3図に示す。第2図(a)で示した従来例と異
なる所は電極3.4,5.6が2層電極構造となってお
り、下層電極4.6と上層電極3.5はオーバラップ部
I!1 を設けて重なり合う構造となっている。A generally widely used method for solving this problem is called an overlap electrode structure, and the structure is shown in FIG. The difference from the conventional example shown in FIG. 2(a) is that the electrodes 3.4 and 5.6 have a two-layer electrode structure, and the lower layer electrode 4.6 and the upper layer electrode 3.5 have an overlap portion I! 1 is provided and has an overlapping structure.
このような構造にすれば、第2図(a)で示したような
電極がない部分Sが存在しないため、ポテンシャルバリ
アが生しなくなる。しかし、このような構造をとった場
合、CCDを高密度化する場合、下層電極と上層電極の
マスク合わせ精度から決まるl,,及び上層電極の加工
精度から決まる間隔I!.2により電極長が制限されて
しまう。即ち、下層電極群の各々の電極長は21+ +
p2より短くできない。これに対し、第2図の従来例で
は加工の点だけで見れば、高密度化を制限する要因は間
隔Sのみである。With such a structure, there is no portion S without electrodes as shown in FIG. 2(a), and no potential barrier is generated. However, when such a structure is adopted, when increasing the density of the CCD, the distance l, determined by the mask alignment accuracy of the lower layer electrode and the upper layer electrode, and the interval I!, determined by the processing accuracy of the upper layer electrode, are determined. .. 2, the electrode length is limited. That is, the length of each electrode in the lower electrode group is 21+ +
It cannot be made shorter than p2. On the other hand, in the conventional example shown in FIG. 2, from the viewpoint of processing only, the only factor that limits the increase in density is the spacing S.
従来の電荷結合素子は以上のように構威されているので
、第2図の素子では電極群間に生しるポテンシャルハリ
アにより転送効率が低下するという問題点があり、第3
図の素子では上述のように電極群の電極長が制限され、
高密度化できないという問題点があった。Since conventional charge-coupled devices are constructed as described above, the device shown in FIG.
In the device shown in the figure, the electrode length of the electrode group is limited as described above.
There was a problem that high density could not be achieved.
この発明は上記のような問題点を解消するためになされ
たもので、高密度化に適し、かつ転送効率が良好な電荷
結合素子を得ることを目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a charge-coupled device that is suitable for high density and has good transfer efficiency.
この発明に係る電極結合素子は半導体基板上に絶縁膜を
介して複数の互いに重なり合わない電極群を設け、この
電極群の上層に新たな電極を設け、この電極に直流電圧
を印加するようにしたものである。The electrode-coupled device according to the present invention has a plurality of electrode groups that do not overlap each other on a semiconductor substrate via an insulating film, a new electrode is provided on the upper layer of this electrode group, and a DC voltage is applied to this electrode. This is what I did.
?作用〕
この発明においては、電極群の上層に更なる電極を設け
、該電極に直流電圧を印加して、下層電極群の電極間下
のポテンシャルを制御しするようにしたから、オーバラ
ップ電極構造のように電極群の電極長が制限されること
なく転送効率劣化のもととなる上記電極群間のポテンシ
ャルバリアをなくすことができる。? Effect] In this invention, an additional electrode is provided in the upper layer of the electrode group, and a DC voltage is applied to the electrode to control the potential between the electrodes of the lower electrode group, so that an overlap electrode structure is achieved. The potential barrier between the electrode groups, which causes deterioration in transfer efficiency, can be eliminated without limiting the electrode length of the electrode groups.
以下、この発明の一実施例を図について説明する。 An embodiment of the present invention will be described below with reference to the drawings.
第1図(a)は本発明の一実施例による電荷結合素子を
示す図であり、図において、1は半導体基板、2は絶縁
膜、3,4,5.6は電極群であり、電極間の間隔はS
で示されている。ここまでの構或は第2図(a)で示し
た従来例と全く同じである。本発明では電極3,4,5
.6からなる下層電極群の上層に、例えばSiO■膜か
らなる絶縁膜9を介して上層電極10が設けられており
、この電極には直流電源11より直流電圧が印加されて
いる。FIG. 1(a) is a diagram showing a charge-coupled device according to an embodiment of the present invention. In the figure, 1 is a semiconductor substrate, 2 is an insulating film, 3, 4, 5.6 is a group of electrodes. The interval between
It is shown in The structure up to this point is exactly the same as the conventional example shown in FIG. 2(a). In the present invention, electrodes 3, 4, 5
.. An upper layer electrode 10 is provided on the upper layer of the lower layer electrode group 6 with an insulating film 9 made of, for example, a SiO2 film interposed therebetween, and a DC voltage is applied to this electrode from a DC power source 11.
次に動作について説明する。Next, the operation will be explained.
第2図(b)に対応して電極3,4にクロックH ig
hレベルが印加され、電極5.6にクロックLowレベ
ルが印加された状態のポテンシャル分布を第1図(b)
に示し、また第2図(C)に対応して電極5.4にクロ
ツクH i ghレヘルが印加され、電極3,6にクロ
ックLowレベルが印加された状態のポテンシャル分布
を第1図(C)に示す。これら図に示すように、本実施
例では電極10に印加された直流電圧による電界で、従
来、電極間で生じていたポテンシャルバリアをなくすこ
とができる。Corresponding to FIG. 2(b), the clock H ig is applied to the electrodes 3 and 4.
Figure 1(b) shows the potential distribution when the h level is applied and the clock low level is applied to the electrode 5.6.
1 (C) shows the potential distribution when the clock high level is applied to the electrode 5.4 and the clock low level is applied to the electrodes 3 and 6, corresponding to FIG. 2(C). ). As shown in these figures, in this embodiment, the electric field caused by the DC voltage applied to the electrode 10 can eliminate the potential barrier that conventionally occurs between the electrodes.
ところで、電極10に印加する電圧は大きすぎると、逆
にポテンシャルのへこみが生じるため、電極間隔S及び
電極10から半導体基板表面までの距離に応じて適宜調
節する必要がある。By the way, if the voltage applied to the electrode 10 is too large, the potential will conversely be depressed, so it is necessary to adjust it appropriately according to the electrode interval S and the distance from the electrode 10 to the surface of the semiconductor substrate.
このように本実施例では、電極群3〜6の上層に絶縁膜
9を介して上層電極10を設け、該電極10に電極群間
に生じるポテンシャルバリアをなくすように直流電圧を
印加する構威としたから、電極群の電極長に制限を与え
ることなく、電荷の転送効率を大幅に向上することがで
きる。As described above, in this embodiment, the upper layer electrode 10 is provided on the upper layer of the electrode groups 3 to 6 via the insulating film 9, and a DC voltage is applied to the electrode 10 so as to eliminate the potential barrier generated between the electrode groups. Therefore, the charge transfer efficiency can be greatly improved without limiting the electrode length of the electrode group.
なお、上記実施例では表面チャネル形電荷結合素子につ
いて示したが、本発明は埋め込みチャネル形電荷結合素
子にも適用可能であるまただし、埋め込みチャネル形の
場合、従来例では電極間の間隔Sによりポテンシャルの
へこみができるので、第1図の実施例に示した電源11
の極性を逆にする必要がある。In the above embodiment, a surface channel type charge coupled device was shown, but the present invention can also be applied to a buried channel type charge coupled device. Since a potential depression is created, the power source 11 shown in the embodiment of FIG.
It is necessary to reverse the polarity of
また、上記実施例では4相駆動の電荷結合素子について
示したが、3相駆動の電荷結合素子にも適用可能である
ことはいうまでもない。Furthermore, although the above embodiments have been described with reference to a four-phase drive charge coupled device, it goes without saying that the present invention can also be applied to a three-phase drive charge coupled device.
以上のように、この発明によれば、オーバラップ構造を
持たない電極群とその電極群の上層に直流電圧を印加し
た電極を設けたことにより、電極群の電極間隔に起因す
るポテンシャルの凸凹をなくすることができ、従って転
送効率劣化がなく、かつオーハラップ構造の場合生した
電極長の制限がないため、高密度化に適した電荷結合素
子が得られる効果がある。As described above, according to the present invention, by providing an electrode group that does not have an overlapping structure and an electrode to which a DC voltage is applied in the upper layer of the electrode group, unevenness in potential due to the electrode spacing of the electrode group is reduced. Therefore, there is no deterioration in transfer efficiency, and there is no limit on the electrode length that occurs in the case of the Ohara wrap structure, so there is an effect that a charge coupled device suitable for high density can be obtained.
第1図(a)はこの発明の一実施例による電荷結合素子
の断面構造を示す図、第1図(b), (C)は本発明
の電子に対するポテンシャル分布を示す図、第2図(a
)は従来の電荷結合素子の断面構造を示す図、第2図(
b), (C)は第2図(a)の電荷結合素子における
電子に対するポテンシャル分布を示す図、第3図はオー
バランプ電極構造の電荷結合素子の断面構造を示す図で
ある。
1は半導体基板、2は絶縁膜、3,456は電極群、9
は絶縁膜、lOは上層電極、11は直流電源である。
なお図中同一符号は同一又は相当部分を示す。FIG. 1(a) is a diagram showing the cross-sectional structure of a charge coupled device according to an embodiment of the present invention, FIGS. 1(b) and (C) are diagrams showing the potential distribution for electrons of the present invention, and FIG. a
) is a diagram showing the cross-sectional structure of a conventional charge-coupled device, and Figure 2 (
b) and (C) are diagrams showing the potential distribution for electrons in the charge coupled device of FIG. 1 is a semiconductor substrate, 2 is an insulating film, 3,456 is an electrode group, 9
1 is an insulating film, IO is an upper layer electrode, and 11 is a DC power source. Note that the same reference numerals in the figures indicate the same or equivalent parts.
Claims (1)
互いに重なり合わない電極群と、該電極群の上層に上記
電極群から絶縁されて設けられ、上記半導体基板中の上
記電極群間の領域に形成されるポテンシャルバリアを打
ち消すように上記半導体基板中のポテンシャルを制御す
るための直流電圧が印加される上層電極とを備えたこと
を特徴とする電荷結合素子。(1) A plurality of non-overlapping electrode groups provided on a semiconductor substrate via an insulating film, and a plurality of electrode groups provided in an upper layer of the electrode group to be insulated from the electrode group, and between the electrode groups in the semiconductor substrate. and an upper layer electrode to which a DC voltage is applied for controlling the potential in the semiconductor substrate so as to cancel a potential barrier formed in the region.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1303897A JPH03163836A (en) | 1989-11-21 | 1989-11-21 | Charge coupled device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1303897A JPH03163836A (en) | 1989-11-21 | 1989-11-21 | Charge coupled device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH03163836A true JPH03163836A (en) | 1991-07-15 |
Family
ID=17926581
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1303897A Pending JPH03163836A (en) | 1989-11-21 | 1989-11-21 | Charge coupled device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH03163836A (en) |
-
1989
- 1989-11-21 JP JP1303897A patent/JPH03163836A/en active Pending
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