JPS62242363A - Charge transfer device - Google Patents

Abstract

PURPOSE:To enable high speed driving of a charge transfer device by obtaining electric potential distribution necessary for transfer to the next stage of signal charge according to drift action of an electric field by an extremely simple construction by a method wherein the shape of width of a channel region to be formed to a semiconductor substrate is so formed as to be narrowed gradu ally toward the rear of the charge transfer direction. CONSTITUTION:The shape of width of the channel region 1 of a charge transfer device is so formed as to be narrowed gradually toward the rear of the charge transfer direction. When a positive voltage (VH) to make potential to be deep in regard to signal charge (electron) is applied to a terminal phi1, and moreover a positive voltage (VL) to make potential to be shallow is applied to terminals phi2 and phi3, a potential well is generated under a gate electrode 5a. When signal charge is injected to the lower part of the gate electrode 5a in this condition, and the voltage VH is applied to the terminal phi2 in succession, and moreover the voltage VL is applied to the terminals phi1 and phi3, signal charge is transferred rapidly according to drift action receiving force from an electric field according to the gradient of inside potential, and high speed driving of the charge transfer device can be attained.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a charge transfer device, and particularly to an improved structure of a charge transfer device used in, for example, a solid-state imaging device.

[Conventional technology]

As a conventional example of this type of charge transfer device, the general structure of the charge transfer device is shown in Figure 3 ( Shown in a), and (b) to d). FIG. 3(a) is a sectional view showing the main part configuration of the charge transfer device,
Figures (b) to d) are explanatory diagrams showing the potential distribution of the above device.

First, the general structure of the conventional charge transfer device shown in FIG. 3(a) will be described.

That is, in FIG. 3(a), on the gate insulating film 4 of the semiconductor substrate 3, there are 9 layers for applying a voltage necessary to accumulate charge in the substrate 3 and form a potential well.
For example, a first layer gate electrode 5 and a second layer gate electrode 6 are formed of aluminum, polycrystalline silicon, etc. An interlayer insulating film 7 for separating these two electrodes is formed between the gate electrode 6 of the second layer and the second gate electrode 6.
Both ends of the gate electrode 8 of the first layer are overlapped with the ends of the gate electrode 5 of the first layer via the interlayer insulating film 7 in order to prevent an uncontrollable potential barrier from occurring between the electrodes. It is.

Next, the conventional charge transfer device shown in FIG.
The operation when driven by phase will be described. In this case, the semiconductor substrate 3 is a p-type semiconductor.

First, a positive voltage (vH) that makes the potential deeper with respect to the signal charge (electron) is applied to the terminal φ1, and a positive voltage that makes the potential shallower is sequentially applied to the adjacent terminals φ2 and φ3. (VL) is applied,
In this state, the gate electrode 5a to which the voltage VH is applied
A signal charge 8 is injected below. The state in which the signal charge 8 is injected is shown in FIG. 3(b).

Subsequently, voltage VH is applied to terminal φ2, and terminal φ1
When voltage vLt- is applied to φ3 and φ3, Fig. 3(c)
As shown in FIG. 3, when the signal charge 8 is transferred to the bottom of the gate electrode 6a and the voltage vH is applied to the terminal φ3 and the voltage V is applied to the terminals φ1 and φ2, as shown in FIG.
As shown in d), the signal charge 8 is transferred below the gate electrode 5b, and by repeating this operation, the signal charge 8 is transferred in the direction shown by the arrow (A) in FIG. 3(a). They can be transferred sequentially.

[Problem that the invention seeks to solve]

Conventional charge transfer devices are configured and operated as described above, and the movement of signal charges from one potential well to the next stage well is achieved by diffusion of the signal charges. Another problem is that when this is driven by high-speed clock pulses, the signal charges cannot be transferred completely and the transfer efficiency decreases.

The present invention was made to solve these conventional problems, and its purpose is to transfer signal charges by the drift effect caused by an electric field. The object of the present invention is to provide a charge transfer device of this type.

[Means for solving problems]

In order to achieve the above object, the charge transfer device according to the present invention is such that the width of the channel region formed in the semiconductor substrate is gradually narrowed toward the rear in the charge transfer direction. .

[For production]

That is, in this invention, a change in the width of the channel region causes a difference in the influence of impurities diffused from the element isolation region into the channel region on the potential distribution of the channel region, and as a result, the drift effect of the electric field is reduced. This makes it possible to generate the potential distribution necessary to transfer the signal charge to the next stage.

〔Example〕

Hereinafter, an embodiment of the charge transfer device according to the present invention will be described.
This will be explained in detail with reference to FIGS. 1 and 2.

FIGS. 1(a) and (b) are a plan view and a cross-sectional view showing an outline of the device of this embodiment, FIG. 2(a) is a cross-sectional view showing the main structure of the charge transfer device, and FIG. ) to d) are explanatory diagrams showing the potential distribution of the same device.

In the embodiment device shown in FIGS. 1(a) and 2(b) and FIG. 2(a), the same reference numerals as in the conventional device shown in FIG. 3(a) indicate the same or corresponding parts, and the reference numeral 1 is The n-type channel region 2 is an element isolation region doped with p-type impurities, and the p-type impurities are sufficiently diffused by high-temperature treatment. As described above, the width of the channel region 1 is formed so as to gradually become narrower toward the rear in the charge transfer direction.

Now, considering electrons as signal charges, the diffusion of p-type impurities from the element isolation region 2 acts to lower the potential for electrons. Therefore, as described above, by forming the width of the channel region 1 so that it gradually narrows toward the rear in the charge transfer direction, the width of the channel region 1 can be reduced. The potential becomes low in the narrow portion, resulting in a potential distribution as shown in FIG. 2(b).

FIGS. 2(b) to 2d) show changes in potential when the charge transfer device in this embodiment is driven in three phases.

In this case, first, a positive voltage (V) is applied to the terminal φ1 so that the potential becomes deep with respect to the signal charge (electron), and a positive voltage (V) is applied to the terminals φ and φ3 so that the potential becomes shallow with respect to the signal charge (electron). When a voltage (VL) is applied, a potential well as shown in FIG. 2(c) is created under the gate electrode 5a, and in this state, the signal charges 8 are injected under the gate electrode 5a.

Subsequently, voltage VH is applied to terminal φ, and terminal φ
When voltage VL is applied to φ and φ, the potential distribution changes from the state shown in FIG. 2(c) to the state shown in FIG. In other words, the signal charge 8 receives a force from the electric field due to the gradient of the internal potential and is quickly transferred by the drift effect, making high-speed driving possible. By repeating this operation, the signal charge 8 is transferred as shown in FIG. Sequentially in the direction shown by arrow (B) in a).

This allows for efficient transfer.

Note that in the device of the above embodiment, the change in the potential of the channel region due to the diffusion of impurities from the element isolation region is utilized when forming the channel region. This may be done separately using .

Furthermore, in the case of the device of the embodiment, the shape of the channel region is as follows:
Although this is changed linearly, it is also possible to change it curvedly, and it is clear that various potential distributions can be realized by selecting an appropriate shape.

Further, in the above-mentioned embodiment, the case where the device is driven by a three-phase clock pulse signal has been described, but it may also be driven by a two-phase or four-phase or more clock pulse signal, and similar effects and effects can be obtained. It is.

〔Effect of the invention〕

As described in detail above, according to the present invention, the width of the channel region formed in the semiconductor substrate is formed to be gradually narrower toward the rear in the charge transfer direction, which is an extremely simple structure. , the potential distribution necessary to transfer the signal charge to the next stage is obtained by the drift effect of the electric field, high-speed driving is possible, transfer efficiency is high, and a device configuration with a simple structure can be easily provided. It has excellent features.

[Brief explanation of drawings]

FIGS. 1(a) and 1(b) are plan configuration diagrams showing an outline of an embodiment of a charge transfer device according to the present invention. 2(a) is a sectional view showing the main part configuration of the charge transfer device, FIGS. 2(b) to 2d) are explanatory diagrams showing the potential distribution of the above device, and FIG. (a) is a sectional view showing the main part configuration of a conventional charge transfer device;
b) to d) are explanatory diagrams showing the potential distribution of the same device. 1... Channel region, 2... Element isolation region, 3
...Semiconductor substrate, 4...Gate insulating film, 5...
...Gate electrode of the first layer, 6...Gate electrode of the second layer, 7...Interlayer insulating film, 8...Signal charge, B...
...Charge transfer direction. Agent Masuo Oiwa Fig. 1 (0) □B 7: Interlayer kerin Ren Fig. 2 (0) □B B: Charge transfer direction (b) 8; ) (d) Procedural amendment (voluntary)

Claims (1)

[Claims] (1) Charge transfer comprising a semiconductor substrate having a channel region and an impurity region for separating the channel region, and a plurality of gate electrodes for charge transfer formed successively adjacent to each other on the semiconductor substrate. A charge transfer device characterized in that the width of the channel region under each of the gate electrodes is gradually narrowed toward the rear in the charge transfer direction.