JPS60136258A - Charge coupled device - Google Patents
Charge coupled deviceInfo
- Publication number
- JPS60136258A JPS60136258A JP24334183A JP24334183A JPS60136258A JP S60136258 A JPS60136258 A JP S60136258A JP 24334183 A JP24334183 A JP 24334183A JP 24334183 A JP24334183 A JP 24334183A JP S60136258 A JPS60136258 A JP S60136258A
- Authority
- JP
- Japan
- Prior art keywords
- transfer
- length
- electrodes
- charge
- stage
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 238000005036 potential barrier Methods 0.000 claims abstract description 11
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 238000003860 storage Methods 0.000 claims description 15
- 239000012535 impurity Substances 0.000 claims description 12
- 239000002131 composite material Substances 0.000 claims 1
- 238000009825 accumulation Methods 0.000 abstract 2
- 238000009413 insulation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 238000009826 distribution Methods 0.000 description 4
- 230000004888 barrier function Effects 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- 238000003384 imaging method Methods 0.000 description 2
- 244000089486 Phragmites australis subsp australis Species 0.000 description 1
- 235000014676 Phragmites communis Nutrition 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 238000005468 ion implantation Methods 0.000 description 1
- 150000002500 ions Chemical class 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/762—Charge transfer devices
- H01L29/765—Charge-coupled devices
- H01L29/768—Charge-coupled devices with field effect produced by an insulated gate
- H01L29/76833—Buried channel CCD
- H01L29/76841—Two-Phase CCD
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Solid State Image Pick-Up Elements (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野〕
本発明は、固体撮像装置とか遅延装置などに用いられ名
電荷結合装置(以下、CCDと略記する。)に係シ、特
に単相駆動形および2相駆動形のCCDに関する。Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to charge coupled devices (hereinafter abbreviated as CCD) used in solid-state imaging devices, delay devices, etc., and particularly relates to single-phase drive type and CCD devices. This invention relates to a two-phase drive type CCD.
この種の従来のCODの一例としてN型埋め込みチャン
ネル型CODを第1図に示している。即ち、1はたとえ
ばP型の半導体基板、2は上記基板1の表面に形成され
たN型の不純物領域からなる埋め込みチャンネル、3は
前記基板1上に形成された薄い絶縁膜、4l・・・およ
び42・・・は上記絶縁膜3上で順次隣接するように交
互に配量されて形成された第1,第2の転送電極であっ
て、隣接する2個の転送電極41+’2がそれぞれ1組
の転送電極となるように共通接続されている。5は前記
埋め込みチャンネル20表面上で各転送段の第2の転送
電極42下に形成されたN型不純物を低濃度に含むN−
型の不純物領域でオシ、これは前記第1の転送電極41
−形成後にセルファジインで前記埋め込みチャンネル(
N型)2にP型不純物のイオン打ち込みが行まわれるこ
とによって形成される。なお、第2の転送電極42はそ
の両端部が第1の転送電極41との間に絶縁膜を介して
オーバーラツプするように形成されている。An N-type buried channel type COD is shown in FIG. 1 as an example of this type of conventional COD. That is, 1 is, for example, a P-type semiconductor substrate, 2 is a buried channel formed of an N-type impurity region formed on the surface of the substrate 1, 3 is a thin insulating film formed on the substrate 1, 4l... and 42... are first and second transfer electrodes which are alternately arranged so as to be adjacent to each other on the insulating film 3, and the two adjacent transfer electrodes 41+'2 are respectively They are commonly connected to form one set of transfer electrodes. 5 is an N- type impurity containing a low concentration of N type formed on the surface of the buried channel 20 and below the second transfer electrode 42 of each transfer stage.
In the type impurity region, this is the first transfer electrode 41.
- the buried channel (with cellufadiin after formation);
It is formed by ion implantation of P-type impurities into N-type) 2. The second transfer electrode 42 is formed such that both ends thereof overlap with the first transfer electrode 41 with an insulating film interposed therebetween.
上記CODがたとえば2相駆動される場合、即ち、奇数
番目の各段の転送電極所定の正電圧と0Vとの間で変化
するクロックツ平ルスφが印加され、偶数番目の各段の
転送電極に上記φとは逆相のクロックパルスTが印加さ
れる場合には、基板断面内の電位分布および信号電荷Q
の流れは第2図(、) 、 (b)に示すように々る。When the COD is driven in two phases, for example, a clock pulse pulse φ varying between a predetermined positive voltage and 0 V is applied to the transfer electrodes of each odd-numbered stage, and the transfer electrode of each even-numbered stage is When a clock pulse T having the opposite phase to φ is applied, the potential distribution in the cross section of the substrate and the signal charge Q
The flow is as shown in Figures 2(,) and (b).
即ち、各転送段の転送電極下には、前記不純物領域5に
よυ形成された電位障壁部Bと、との障壁部Bよシも電
位が深い電位井戸となって電荷を蓄積可能な電荷蓄積部
Sとが形成される。この場合、上記障壁部Bおよび蓄積
部Sの各電位は、転送電極の印加パルスφまたはφがロ
ウレベルφ、。That is, under the transfer electrode of each transfer stage, there is a potential barrier portion B formed by the impurity region 5, and a potential well that is deeper in potential than the barrier portion B between the impurity region 5 and the charge that can accumulate charges. A storage section S is formed. In this case, the respective potentials of the barrier section B and the storage section S are such that the applied pulse φ or φ of the transfer electrode is at a low level φ.
φ、のときに比べてハイレベルφ8.φ□のときの方が
大きく(深く)なる。したがって、第2図(a) +
(b)に示すように隣接する2段の転送電極下に電位井
戸の段差が生じて信号電荷Qの蓄積番転送が制約される
ようになる。The high level φ8. It becomes larger (deeper) when φ□. Therefore, Fig. 2(a) +
As shown in (b), a step difference in potential wells occurs under two adjacent transfer electrodes, and the storage number transfer of the signal charge Q is restricted.
このようなCODにおける電荷転送量は、電荷蓄積部S
の大きさにより定まるものである。そして、従来は、信
号電荷転送チャンネルの幅を狭くすることを重要視する
ことが多く、電荷蓄積部Sの長さし2として所望の電荷
転送量を確保するのに必要なだけ設定していた。これに
よって通常は電荷蓄積部Sの長さL2が電荷蓄積部相互
間隔、つまシミ位障壁部Bの長さLlよりもかなシ大き
い。The amount of charge transferred in such a COD is the charge storage part S
It is determined by the size of Conventionally, it has often been important to narrow the width of the signal charge transfer channel, and the length of the charge storage section S has been set as long as necessary to ensure the desired amount of charge transfer. . As a result, the length L2 of the charge storage section S is usually slightly larger than the distance L1 between the charge storage sections and the length L1 of the barrier section B at the smear level.
ところで、電位障壁部Bの長さLlと電荷蓄積部Sの長
さL2との和L(−Lx +L2 )に制約がある場合
、特に各転送段の長さく LL、+L2 )をある一定
の長さよシ小さくできない場合、第1図に示した構造の
CODでは電荷転送速度が遅くなるという問題がある。By the way, if there is a restriction on the sum L (-Lx +L2) of the length Ll of the potential barrier section B and the length L2 of the charge storage section S, in particular, the length of each transfer stage (LL, +L2) must be set to a certain length. If the width cannot be made small, there is a problem in that the charge transfer speed becomes slow in the COD having the structure shown in FIG.
即ち、クロックパルス周波数が一定および各転送段の長
さしが一定である場合、転送速度はL1+L2に比例す
るものであり、前述したようにLlとL2とが大きく違
うと転送速度が遅くなる。That is, when the clock pulse frequency is constant and the length of each transfer stage is constant, the transfer rate is proportional to L1+L2, and as described above, if L1 and L2 are significantly different, the transfer rate becomes slow.
本発明は上記の事情に鑑みてなされたもので、各転送段
の電位障壁部の長さと電荷蓄積部の長さとの和が一定、
クロック周波数が一定である場合において、電荷転送速
度を最大に設定し得る電荷結合装置を提供するものであ
る。The present invention has been made in view of the above-mentioned circumstances, and has a structure in which the sum of the length of the potential barrier section and the length of the charge storage section of each transfer stage is constant.
The object of the present invention is to provide a charge-coupled device in which the charge transfer rate can be set to the maximum when the clock frequency is constant.
即ち、本発明の電荷結合装置は、各転送段の転送電極下
に形成される電位障壁部、電荷蓄積部それぞれの長さを
略等しく設定してなることを特徴とするものでちる。That is, the charge coupled device of the present invention is characterized in that the lengths of the potential barrier section and the charge storage section formed under the transfer electrode of each transfer stage are set to be approximately equal.
以下、図面を参照して本発明の一実施例を詳細に説明す
る。第3図に示すCCDは、第1図を参照して前述した
従来のCODに比べて、各転送段における電位障壁部B
の長さく第1の転送電極41′・・・の相互間隔。)L
r と電荷蓄積部Sの長さく第1の転送電極41′・・
・の長さ。)Lx とが相等しい(略等しければよい。Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Compared to the conventional COD described above with reference to FIG. 1, the CCD shown in FIG. 3 has a potential barrier section B at each transfer stage.
The mutual distance between the first transfer electrodes 41' is long. )L
r and the long first transfer electrode 41' of the charge storage section S...
・Length. ) Lx are equal (substantially equal).
)点が異々るだけでアシ、その他は同じであるので第1
図中と同一部分には同一符号を付してその説明を省略す
る。) The only difference is the reeds, and the rest are the same, so the first
The same parts as those in the drawings are given the same reference numerals, and the explanation thereof will be omitted.
上記構成のCODにおいては、クロックパルスφ、φの
周波数が一定、各転送段の長さL(−Ll +L2 )
が一定である場合に、電荷転送速度がL!+L2に比例
するが、本例ではL1キL2(理想的にはLl”L2)
となっているので最大転送速度が得られる。この場合、
ccDの製造方法は従来通9で良く、製造が困難になる
ことはない。In the COD with the above configuration, the frequencies of clock pulses φ and φ are constant, and the length of each transfer stage is L(-Ll +L2)
is constant, the charge transfer rate is L! It is proportional to +L2, but in this example it is L1 x L2 (ideally Ll”L2)
Therefore, the maximum transfer speed can be obtained. in this case,
The ccD can be manufactured by the conventional method 9, and the manufacturing is not difficult.
第4図は、上記CODにおける基板内の電位分布および
信号電荷Q転送の様子を示している。FIG. 4 shows the potential distribution in the substrate and the state of signal charge Q transfer in the above COD.
なお、第2の転送電極42′・・・下の不純物領域とし
て、上記実施例とは逆にN型不純物のイオンを打ち込ん
でN型不純物を高濃度に含むN+領領域形成した場合に
は、各転送段において第2の転送電極42′下が第1の
転送電極41′下よシも電位が深くなるので、第2の転
送電極42′下が−電荷蓄積部となシ、第1の転送電極
41′下が電位障壁部となシ、第4図に示した信号電荷
Qの転送方向とは逆方向に電荷転送が行なわれるように
なる。In addition, when an N+ region containing a high concentration of N-type impurity is formed by implanting N-type impurity ions as the impurity region under the second transfer electrode 42', contrary to the above embodiment, In each transfer stage, the potential under the second transfer electrode 42' is deeper than that under the first transfer electrode 41', so that the area under the second transfer electrode 42' becomes a negative charge storage area. Since the lower part of the transfer electrode 41' serves as a potential barrier section, charge transfer is performed in a direction opposite to the transfer direction of the signal charge Q shown in FIG.
また、各転送段のうち1段間隔を有する各段の転送電極
にクロックパルス(たとえばφ)を印加し、残シの各段
の転送電極には上記クロックパルスのハイレベルのたと
えば1/2の電圧値を有する直流電圧を印加しておく単
相駆動の場合にも、前記実施例と同様の効果が得られる
。In addition, a clock pulse (for example, φ) is applied to the transfer electrodes of each transfer stage with a one-stage interval, and a clock pulse (for example, φ) of the high level of the clock pulse is applied to the transfer electrodes of the remaining stages. Even in the case of single-phase drive in which a DC voltage having a voltage value is applied, the same effects as in the embodiment described above can be obtained.
また、本発明は表面チャンネル型CODにも適用可能で
ある。Further, the present invention is also applicable to a surface channel type COD.
上述したように本発明の電荷結合装置によれば、各転送
段の電位障壁部の長さLlと電荷蓄積部の長さL2とを
略等しくなるように設定しているので、Ll +L2が
一定、クロック周波数が一定の場合に最大転送速度を得
ることができ、固体撮像装置に適用してその動作速度を
向上させることができるなどその応用によシ多大な効果
が得られる。As described above, according to the charge coupled device of the present invention, the length Ll of the potential barrier section of each transfer stage and the length L2 of the charge storage section are set to be approximately equal, so that Ll + L2 is constant. When the clock frequency is constant, the maximum transfer rate can be obtained, and when applied to a solid-state imaging device, its operating speed can be improved.
第1図は従来のCODの一例を示す構成説明図、第2図
(tL)、(b)は第1図のCCDにおける基板内の電
位分布および信号電荷転送の様子を示す図、第3図は本
発明に係るCODの一実施例を示す構成説明図、第4図
(、) 、 (b)は第3図のCCDにおける基板内の
電位分布および信号電荷転送の様子を示す図でちる。
1・・・半導体基板、3・・・絶縁膜、41r42・・
・転送電極、B・・・電位障壁部、S・・・電荷蓄積部
。
出願人代理人 弁理士 鈴 江 武 豚箱1図
(a)
第3図
(a)FIG. 1 is a configuration explanatory diagram showing an example of a conventional COD, FIGS. 2 (tL) and (b) are diagrams showing the potential distribution in the substrate and signal charge transfer in the CCD of FIG. 1, and FIG. 4(a) and 4(b) are diagrams showing the potential distribution in the substrate and the state of signal charge transfer in the CCD of FIG. 3. FIG. 1... Semiconductor substrate, 3... Insulating film, 41r42...
- Transfer electrode, B... potential barrier section, S... charge storage section. Applicant's representative Patent attorney Takeshi Suzue Pig box Figure 1 (a) Figure 3 (a)
Claims (2)
て並べられて形成された複数の転送電極と、各転送段の
転送電極下に形成されそれぞれの長さが略等しい電位障
壁部および電荷蓄積部とを具備することを%徴とする電
荷結合装置。(1) A semiconductor substrate, a plurality of transfer electrodes formed on the semiconductor substrate side by side with an insulating film interposed therebetween, a potential barrier portion formed under the transfer electrodes of each transfer stage and having substantially equal lengths, and A charge coupled device characterized by comprising a charge storage section.
よび第2の転送電極からなシ、この第2の転送電極下の
半導体基板表面には第1の転送電極下とは不純物濃度が
異なる不純物領域が形成されておシ、第1の転送電極の
電極長さと第1の転送電極相互間隔とが略等しいことを
特徴とする特許 合装置。(2) The transfer electrodes of each transfer stage are composed of a first transfer electrode and a second transfer electrode, and the semiconductor substrate surface under the second transfer electrode has an impurity concentration different from that under the first transfer electrode. A patented composite device characterized in that impurity regions are formed with different impurity regions, and the electrode length of the first transfer electrode and the interval between the first transfer electrodes are substantially equal.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24334183A JPS60136258A (en) | 1983-12-23 | 1983-12-23 | Charge coupled device |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP24334183A JPS60136258A (en) | 1983-12-23 | 1983-12-23 | Charge coupled device |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS60136258A true JPS60136258A (en) | 1985-07-19 |
Family
ID=17102381
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP24334183A Pending JPS60136258A (en) | 1983-12-23 | 1983-12-23 | Charge coupled device |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS60136258A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6346770A (en) * | 1986-08-14 | 1988-02-27 | Nec Corp | Change coupled device |
JPH08222725A (en) * | 1995-02-17 | 1996-08-30 | Nec Corp | Charge-coupled element and manufacture thereof |
-
1983
- 1983-12-23 JP JP24334183A patent/JPS60136258A/en active Pending
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6346770A (en) * | 1986-08-14 | 1988-02-27 | Nec Corp | Change coupled device |
JPH08222725A (en) * | 1995-02-17 | 1996-08-30 | Nec Corp | Charge-coupled element and manufacture thereof |
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