JPS60136258A - Charge coupled device - Google Patents

Abstract

PURPOSE:To enable the change transfer speed to be set at maximum by a method wherein the length of each of the potential barrier part and the charge accumulation part of each transfer stage is set almost equal with each other. CONSTITUTION:The first and second transfer electrodes 41 and 42 successively formed by arrangement in adjacency on a thin insulation film 3 on a P type semiconductor substrate 1 are connected in common so as to be a pair of transfer electrodes, respectively. In case the frequency of clock pulses phi and phi' almost equalizing the length (the mutual interval of the first electrodes 41'...) L1 of the potential barrier part in each transfer stage and the length (the length of the first transfer electrodes 41'...) L2 of the change accumulation part is constant, and the length L (=L1+L2) of each transfer stage is constant, the charge transfer speed is proportion to L<2>1+L<2>2, and L1 L2; therefore, the maximum transfer speed can be obtained.

Description

Detailed Description of the Invention [Technical Field of the Invention] The present invention relates to charge coupled devices (hereinafter abbreviated as CCD) used in solid-state imaging devices, delay devices, etc., and particularly relates to single-phase drive type and CCD devices. This invention relates to a two-phase drive type CCD.

[Technical background of the invention]

An N-type buried channel type COD is shown in FIG. 1 as an example of this type of conventional COD. That is, 1 is, for example, a P-type semiconductor substrate, 2 is a buried channel formed of an N-type impurity region formed on the surface of the substrate 1, 3 is a thin insulating film formed on the substrate 1, 4l... and 42... are first and second transfer electrodes which are alternately arranged so as to be adjacent to each other on the insulating film 3, and the two adjacent transfer electrodes 41+'2 are respectively They are commonly connected to form one set of transfer electrodes. 5 is an N- type impurity containing a low concentration of N type formed on the surface of the buried channel 20 and below the second transfer electrode 42 of each transfer stage.
In the type impurity region, this is the first transfer electrode 41.
- the buried channel (with cellufadiin after formation);
It is formed by ion implantation of P-type impurities into N-type) 2. The second transfer electrode 42 is formed such that both ends thereof overlap with the first transfer electrode 41 with an insulating film interposed therebetween.

When the COD is driven in two phases, for example, a clock pulse pulse φ varying between a predetermined positive voltage and 0 V is applied to the transfer electrodes of each odd-numbered stage, and the transfer electrode of each even-numbered stage is When a clock pulse T having the opposite phase to φ is applied, the potential distribution in the cross section of the substrate and the signal charge Q
The flow is as shown in Figures 2(,) and (b).

That is, under the transfer electrode of each transfer stage, there is a potential barrier portion B formed by the impurity region 5, and a potential well that is deeper in potential than the barrier portion B between the impurity region 5 and the charge that can accumulate charges. A storage section S is formed. In this case, the respective potentials of the barrier section B and the storage section S are such that the applied pulse φ or φ of the transfer electrode is at a low level φ.

The high level φ8. It becomes larger (deeper) when φ□. Therefore, Fig. 2(a) +
As shown in (b), a step difference in potential wells occurs under two adjacent transfer electrodes, and the storage number transfer of the signal charge Q is restricted.

The amount of charge transferred in such a COD is the charge storage part S
It is determined by the size of Conventionally, it has often been important to narrow the width of the signal charge transfer channel, and the length of the charge storage section S has been set as long as necessary to ensure the desired amount of charge transfer. . As a result, the length L2 of the charge storage section S is usually slightly larger than the distance L1 between the charge storage sections and the length L1 of the barrier section B at the smear level.

[Problems with background technology]

By the way, if there is a restriction on the sum L (-Lx +L2) of the length Ll of the potential barrier section B and the length L2 of the charge storage section S, in particular, the length of each transfer stage (LL, +L2) must be set to a certain length. If the width cannot be made small, there is a problem in that the charge transfer speed becomes slow in the COD having the structure shown in FIG.

That is, when the clock pulse frequency is constant and the length of each transfer stage is constant, the transfer rate is proportional to L1+L2, and as described above, if L1 and L2 are significantly different, the transfer rate becomes slow.

[Purpose of the invention]

The present invention has been made in view of the above-mentioned circumstances, and has a structure in which the sum of the length of the potential barrier section and the length of the charge storage section of each transfer stage is constant.
The object of the present invention is to provide a charge-coupled device in which the charge transfer rate can be set to the maximum when the clock frequency is constant.

[Summary of the invention]

That is, the charge coupled device of the present invention is characterized in that the lengths of the potential barrier section and the charge storage section formed under the transfer electrode of each transfer stage are set to be approximately equal.

[Embodiments of the invention]

Hereinafter, one embodiment of the present invention will be described in detail with reference to the drawings. Compared to the conventional COD described above with reference to FIG. 1, the CCD shown in FIG. 3 has a potential barrier section B at each transfer stage.
The mutual distance between the first transfer electrodes 41' is long. )L
r and the long first transfer electrode 41' of the charge storage section S...
・Length. ) Lx are equal (substantially equal).

) The only difference is the reeds, and the rest are the same, so the first
The same parts as those in the drawings are given the same reference numerals, and the explanation thereof will be omitted.

In the COD with the above configuration, the frequencies of clock pulses φ and φ are constant, and the length of each transfer stage is L(-Ll +L2)
is constant, the charge transfer rate is L! It is proportional to +L2, but in this example it is L1 x L2 (ideally Ll”L2)
Therefore, the maximum transfer speed can be obtained. in this case,
The ccD can be manufactured by the conventional method 9, and the manufacturing is not difficult.

FIG. 4 shows the potential distribution in the substrate and the state of signal charge Q transfer in the above COD.

In addition, when an N+ region containing a high concentration of N-type impurity is formed by implanting N-type impurity ions as the impurity region under the second transfer electrode 42', contrary to the above embodiment, In each transfer stage, the potential under the second transfer electrode 42' is deeper than that under the first transfer electrode 41', so that the area under the second transfer electrode 42' becomes a negative charge storage area. Since the lower part of the transfer electrode 41' serves as a potential barrier section, charge transfer is performed in a direction opposite to the transfer direction of the signal charge Q shown in FIG.

In addition, a clock pulse (for example, φ) is applied to the transfer electrodes of each transfer stage with a one-stage interval, and a clock pulse (for example, φ) of the high level of the clock pulse is applied to the transfer electrodes of the remaining stages. Even in the case of single-phase drive in which a DC voltage having a voltage value is applied, the same effects as in the embodiment described above can be obtained.

Further, the present invention is also applicable to a surface channel type COD.

〔Effect of the invention〕

As described above, according to the charge coupled device of the present invention, the length Ll of the potential barrier section of each transfer stage and the length L2 of the charge storage section are set to be approximately equal, so that Ll + L2 is constant. When the clock frequency is constant, the maximum transfer rate can be obtained, and when applied to a solid-state imaging device, its operating speed can be improved.

[Brief explanation of the drawing]

FIG. 1 is a configuration explanatory diagram showing an example of a conventional COD, FIGS. 2 (tL) and (b) are diagrams showing the potential distribution in the substrate and signal charge transfer in the CCD of FIG. 1, and FIG. 4(a) and 4(b) are diagrams showing the potential distribution in the substrate and the state of signal charge transfer in the CCD of FIG. 3. FIG. 1... Semiconductor substrate, 3... Insulating film, 41r42...
- Transfer electrode, B... potential barrier section, S... charge storage section. Applicant's representative Patent attorney Takeshi Suzue Pig box Figure 1 (a) Figure 3 (a)

Claims (2)

[Claims] (1) A semiconductor substrate, a plurality of transfer electrodes formed on the semiconductor substrate side by side with an insulating film interposed therebetween, a potential barrier portion formed under the transfer electrodes of each transfer stage and having substantially equal lengths, and A charge coupled device characterized by comprising a charge storage section. (2) The transfer electrodes of each transfer stage are composed of a first transfer electrode and a second transfer electrode, and the semiconductor substrate surface under the second transfer electrode has an impurity concentration different from that under the first transfer electrode. A patented composite device characterized in that impurity regions are formed with different impurity regions, and the electrode length of the first transfer electrode and the interval between the first transfer electrodes are substantially equal.