JPS60210084A - Digital signal processing circuit - Google Patents

Abstract

PURPOSE:To keep constant dynamic range of a receiver by replacing the output signal of an adder or subtractor for two TV input signals with the maximum or minimum value of the dynamic range in case said output signal has an overflow or underflow. CONSTITUTION:An overflow produced at an arithmetic circuit 18 is detected by a discriminating circuit 19, Then a gate circuit 20 is controlled by an overflow control signal O. As a result, the output C' of the circuit 20 delivers the maximum value of a dynamic range of an original signal regardless of the result of the output C of the circuit 18. In this case, a gate circuit 21 works as a mere buffer by an underflow control signal U. Then the output C' of the circuit 20 is transmitted as it is to the output C' of the circuit 21 and delivered. When the output C of the circuit 18 has an underflow, this underflow is detected by the circuit 19. Then the circuit 21 is controlled by the signal U. Therefore the minimum value of the dynamic range of an original signal is delivered to the output C'' of the circuit 21 regardless of the output result of the circuit 18.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Application of the Invention] The present invention relates to a television apparatus, and particularly to a digital signal processing circuit for television signals.

[Background of the invention]

In television signals, time division multiplexing, which divides and multiplexes brightness signals, color signals, and additional signals (audio signals, etc.) on the time axis, eliminates image quality deterioration such as cross color that occurs in frequency multiplexing systems such as NTSC and PAL. The cause is resolved. However, there is a drawback that the required transmission band is wide.

Therefore, a time division multiplexing method can be considered that utilizes the strong correlation between image signals of adjacent scanning lines to perform band compression and enable relatively narrow band transmission. This means that two adjacent
911 calculate the sum and difference for the luminance signals of two horizontal scanning periods.
The configuration is such that the band is limited and the time axis is compressed, and a color difference signal is multiplexed in the idle time created by this time axis compression. However, when reproducing a television signal using this time division multiplexing method, the signal may not be demodulated correctly due to noise or the like, resulting in deterioration of image quality.

FIG. 1 shows a luminance signal modulation section of the time division multiplexing transmitter. 1 is input terminal, 2 is A/D converter, 3 is IH
(H indicates one horizontal scanning period) Delay line, 4 is adder, 5
is a subtracter, 7 is a band limit filter, 8 is a time axis compressor,
9 is a D/A converter. As mentioned above, the luminance signals are adjacent to each other.

The luminance signals Yn and Y+1 (n is an odd or even number) of the two horizontal scanning periods are added to an adder 4. The signal is applied to a subtracter 5, where addition and subtraction processing is performed. As a result, the signal is band-limited by the brightness 1 filter 7, and then converted into a time axis log signal and sent out.

FIG. 2 shows a demodulation section of the time division multiplex receiver.

11 is an A/D converter, 12 is a time axis expander, 16 is an adder, 14 is a subtracter, 15 is a 1H delay line, and 16 is a D/A converter. The luminance signal Y' modulated by the transmitter of FIG. 1 passes through the transmission line 10 and is demodulated into the original luminance signal by the receiver of FIG. The modulated luminance signal Y' is A/D
It is converted into a digital signal by the converter 11, and the difference component (Y
n-Xn+ + )' is returned to the original time axis by the time axis extender 12, and then the sum component (Yrj, Yn+ +
) at the same time as adder 13. The adder 13 calculates (sum component) + (difference component), and the subtracter calculates (sum component) - (configuration t), and the original luminance signals Yn, Yn 10+ is played. On this occasion,
When brightness information such as white and black is transmitted despite noise, etc.
Due to the error occurring in the modulated luminance signal Y', the adder 13. Significant errors occur in the luminance signal reproduced by the subtracter 14. Here, consider the case where the luminance signal is quantized using 4 bits. At this time, assuming that the entire screen is white, the luminance signals YnYn++ are each (1111)2. The sum component (cow) and difference component (乎) are each (111
1)2(0000)2. The sum component (i i 1
i)2. When the difference component (o o o o ) 2 is transmitted without any error without being affected by noise, the luminance signal Yn.

YIL+1 is correctly reproduced on the receiving side. However, due to the influence of noise etc., for example, an error occurs in the difference component, and (0
001)2, an overflow occurs in the output of the adder 16, and as a result, Yn becomes (oooo),'
Therefore, the output of the subtracter 14, that is, Yn++ is (1
110) becomes 2. Here, Yn is white information (1111)
The error caused in the difference component results in black information (0000) 2 being reproduced even though 2 should be reproduced. As described above, errors in the modulated luminance signal caused by noise and the like cause black and white inversion on the receiver side, resulting in deterioration of image quality.

That is, the black and white inversion occurs because a signal level exceeding the dynamic range of the luminance signal occurs as a result of demodulation.

Therefore, in order to prevent black-and-white inversion, the dynamic range of conventional receivers was originally reduced to two times the dynamic range of the luminance signal.
I had to double it.

Expansion of the dynamic range in a digital circuit involves an increase in the number of bits, which increases the circuit scale and also leads to an increase in cost.

[Object of the Invention] The object of the present invention is to provide a signal processing circuit that allows a receiver to be constructed using the dynamic range that a luminance signal originally has, without expanding the dynamic range of the receiver, and that does not cause deterioration in image quality due to black and white inversion. It is about providing.

[Summary of the invention]

In order to achieve the above-mentioned object, the present invention uses black and white inversion that affects image quality when it exceeds the upper limit of the dynamic range (hereinafter referred to as over 70-) or exceeds the lower limit of the dynamic range (hereinafter referred to as underflow). If overflow occurs, the maximum value of the dynamic range (for example, (i i i
1)2), and if there is an underflow, the minimum value of the dynamic range (for example, (000
By replacing the value with 0) and 2), the inversion of black and white is removed. If the value exceeds the dynamic range,
This is caused by the influence of noise, etc., and it is clear that the reproduced signal is not the true value, and it is also clear that the true value at that time is at the white level or near the black level. Therefore, as described above, when an overflow or underflow occurs, there is almost no problem in replacing the value with the maximum value or minimum value of the dynamic range, that is, clipping it.

[Embodiments of the invention]

The present invention will be explained in detail below. First, FIG. 6 shows a diagram of the principle configuration of the present invention. 18 is an arithmetic circuit, 19 is an over 70-/under 70-discrimination circuit, and 20 and 21 are gate circuits. Overflow or underflow occurring in the output result C of the arithmetic circuit 18 is detected by an overflow/underflow discrimination circuit (hereinafter referred to as discrimination circuit) 19. Therefore, when an overflow occurs in the arithmetic circuit 18, the overflow is detected by the discrimination circuit 19, and the overflow control signal O causes the first
gate circuit 20 is controlled.

Therefore, the output C' of the first gate circuit 20 is the maximum value (111...1)2 of the dynamic range of the original signal, regardless of the result of the output C of the arithmetic circuit 18.
Output. At this time, the second gate circuit 21 operates as a buffer for the underflow control signal U, and the output C' of the first gate circuit is directly transferred to the second gate circuit.
The signal is transmitted to the output C' of the gate circuit 121 and is output. Further, when an underflow occurs in the output result C of the arithmetic circuit 18, it is detected by the discrimination circuit 19, and the second gate 21 is controlled by the under 70-control signal U. As a result, the output C' of the second gate 21 has the minimum value (00...
...0)2 is output. Further, when no overflow or underflow occurs, the gate circuit 20,
21 operates as a mere buffer, and the output signal C of the arithmetic circuit becomes the output signal C' of the second gate circuit 21 without any effect on the arithmetic result. Therefore, according to the present invention, when an error occurs in the input signal due to noise or the like and a calculation result that exceeds the dynamic range of the input signal is generated, the error is removed, and the signal is kept within the dynamic range. is played correctly.

Next, specific embodiments of the gate circuits 20 and 21 according to the present invention will be described. FIG. 4 shows a first embodiment.

G1 is an AND circuit, and G2 is an OR circuit. Overflow control signal O is applied to OR circuit G2, and underflow control signal U is applied to AND circuit G1. The gate circuit of this embodiment performs the operation shown by Marie in Table 1. In this case, the overflow control signal O of the discrimination circuit 19
1 at the time of overflow. 0 when otherwise. Also, the underflow control signal U is 0.0 when the underflow occurs. A discriminating circuit that becomes 1 when this is not the case is required. Therefore, when an underflow occurs, both the under 70-control signal U and the overflow control signal 0 become 0. As a result, the output of the AND circuit G1 is (0
0...0)2. On the other hand, the OR circuit G2 operates as a buffer, and its output (C sound C-in-1...(-o
)2 is also output as (00...0)2. Also,
In the case of overflow, both the overflow control signal O and the underflow control signal U become 1. Thereby, the AND circuit q1 operates as a buffer. On the other hand, the output of the OR circuit G2 (CA C4-'1・
...C;) outputs (11...1)2. Therefore, the output result of the arithmetic circuit 18 (CmCm-+...
...Co)2, its output is (11...
...1) 2. When neither overflow nor underflow occurs, the overflow control signal O becomes o1, the underflow control signal U becomes 1, and the AND circuit G1. The OR circuit G2 operates as a buffer, and the output results of the arithmetic circuit 18 (Cm, Cm-+, . . . C
o) is the output of the gate circuit (Crn, CA-1,
・・・・・・□Cchi) is output.

Note that overflow and underflow cannot occur at the same time. Therefore, in Mari in Table 1, U
There is no state where =o Q=i. The gate circuit in this embodiment makes it possible to eliminate overflow and underflow, thereby eliminating the generation of erroneous signals.

In this embodiment, the AND circuit G1, the O
No problem will occur even if the order of the R circuits G2 is changed.

Furthermore, a second specific embodiment of the gate circuits 20 and 21 according to the present invention is shown in FIG. Gl, G2 are NAN
This is the D circuit. The gate circuit of this embodiment performs the operation shown by Marie in Table 2. In this case, the discrimination circuit 190
The overflow control signal O is 1 overflow and 0 at the same time.
, otherwise 1, and underflow control signal U
However, a discriminating circuit is required that becomes 0 when there is underflow and 1 when it is not. Therefore, at the time of underflow, the underflow control signal U becomes 0 and the overflow control signal O becomes 1. Accordingly, the first ONAND circuit q6
The output becomes (11...1)2.

On the other hand, since the second NAND circuit G4 operates as a NOT circuit, its output (cm, c=-1...Co
)2 outputs (00...o)2. Over 70 o'clock.

, the overflow control signal 0 is 01 under 70-
The control signal U becomes 1. Accordingly, the first NAN
D circuit G6 operates as a NOT circuit. On the other hand, the output of the second ONAND circuit q4 (Cm Crn −+−=
-Co )2 outputs (11--1)2. Also, when there is no overflow or underflow, the first. Second NAND circuit Gs.

All G4s operate as NOT circuits. Therefore, the output of the arithmetic circuit 18 (Cm, Cm-1...C
o) 2 remains as it is, and the gate circuit (CA, am-+ ・
...Co)2. Note that the first gate circuit
Similarly to the embodiment, in this embodiment as well, overflow and underflow cannot occur at the same time. In this embodiment as well, overflows and underflows can be removed (overflows and underflows can be removed), eliminating the generation of erroneous signals.

FIG. 6 shows the sixth gate circuit 20, 21 according to the present invention.
A specific example is shown below. Gs and G6 are NOR circuits. The gate circuit of this embodiment performs the operation shown by Marie in Table 3. When using the gate circuit of this embodiment, the overflow control signal O, which is the output of the discrimination circuit 19, is
1 at the time of overflow. otherwise, o, - yet another underflow control signal U is 1. Otherwise, the overflow control signal O needs to be 0. Therefore, when an overflow occurs, the overflow control signal O should be 1. The underflow control signal U becomes 0, and the first O
The output of the NOR circuit G5 becomes (00...0)2 regardless of the output of the arithmetic circuit 18. On the other hand, the second
The NOR circuit G6 operates as one NOT circuit, and its output becomes (11...1)2.

Further, at the time of underflow, the underflow control signal U becomes 1 and the overflow control signal O becomes 0. Accordingly, the first NOR circuit G5 operates as a NOT circuit. On the other hand, the output of the second 1° NOR circuit G6 (
CA, CA-1...c,) includes the first half arithmetic circuit 1.
(00...0)2 is output regardless of the output (Cm, Cm-1...Co) of 8. Further, when there is neither overflow nor underflow, the first
．． The second N0I (circuits G5 and G6 both operate as NOT circuits. Therefore, the output of the arithmetic circuit 1B (C
mCm-+...C0)2 is directly output to the output of the gate circuit (C4-1...C). Therefore, in this embodiment as well, effects similar to those of the second embodiment of the gate circuits 20 and 21 can be obtained. Note that in this embodiment as well, overflow and underflow cannot occur at the same time.

FIG. 7 shows the fourth gate circuit 20, 21 according to the present invention.
A specific example is shown below. G7 is D-7 lip-flop (
(hereinafter referred to as D-FF). According to this embodiment, the gate circuits 20 and 21 can be composed of one DF'F. The operation of this embodiment will be clear from the truth table in Table 4. It is also clear that the same effects as in the other embodiments of the gate circuits 20 and 21 can be obtained in this embodiment as well. In this embodiment, the clear (CLR) terminal and preset (pn) terminal of D-'FFG7 have negative logic, but there is no problem even if they have positive logic. Also, D-F
It is also possible to use JK-Flip 7p knob instead of F'.

Next, a specific embodiment of the arithmetic circuit 181 and the discriminating circuit 19 of the present invention is shown in FIG. 22 is an adder, which corresponds to the arithmetic circuit 18 in FIG. 3; 26 is a NOT circuit; 24 is an AND circuit; and 25 is a NO circuit;
Configure. Adder 220 input signal A is encoded with a unipolar natural binary code, and input signal B is encoded with a two's complement code. Further, the adder output signal C is encoded with a single-polarity natural binary code. This corresponds to the adder 16 in the luminance signal demodulation section of the time division multiplex receiver 1.

That is, since the input signal A has a negative luminance polarity, the adder 22 has an addition mode and a subtraction mode. Therefore, an overflow occurs in the addition mode, and an underflow occurs in the subtraction mode. The most significant bit AM of the input signals A and H to the first adder 22 determines whether this overflow or underflow occurs.

BM and the most significant bit CM of the output signal C of the adder 22
Use. That is, the most significant pitch of the input signal B)
If HM is 1, the value of the input signal B indicates a negative value, and it is determined that the subtraction mode is in effect. Also,
If the most significant bit of the input signal A at that time is 0 and the most significant bit of the output signal C of the adder 22 is 1, the output signal C of the adder 22 is obviously a negative value based on the two's complement code. It is possible to distinguish what is shown. The output signal C of the adder 22 in this case is a unipolar natural binary code, and there is no negative value. Therefore, this means that an underflow has occurred. From this, the underflow (AMA
EMA CM ), and the underflow determining circuit can be configured with multiple types of NOT circuits 26 and AND circuits 24 . Also, the most significant pitch of the input signal B)
If M is 0, it can be determined that the adder 22 is in the addition mode. At this time, the most significant bin of the input signal A)
If AM is 1 and the output signal CM is 0, it can be determined that it is over 70-.
Overflow can be determined by (AMAHMACM), and the overflow determination circuit can be composed of a NOT circuit 23 and a NOR circuit 25.

□ Also, the configuration of the underflow discrimination circuit and overflow discrimination circuit is changed according to the logic form of the gate circuits 20 and 21, and a NAND circuit R is substituted for the AND circuit.
It is obvious that this can be handled by using an OR circuit instead of a circuit. Therefore, it is clear that all the gate circuit embodiments described above can be applied to this embodiment as well.
It is also clear that similar effects can be obtained.

FIG. 9 shows another specific embodiment of the arithmetic circuit 18 and discrimination circuit 19 of the present invention. 26 is a subtracter, which corresponds to the arithmetic circuit 1 in Fig. 6.
8, 27 is a NOT circuit, 28 is an N01 (, circuit, and 29 is an AND circuit, which corresponds to the discriminator circuit 19. The input signal A of the subtracter 26 is a single-polarity natural The input signal B is encoded with a two's complement code.The output signal C of the subtracter 26 is encoded with a unipolar natural binary code. This corresponds to the subtracter 14 in the luminance signal demodulation section of the time-division multiplex receiver.That is, the input signal A is a sum component of luminance signals.This embodiment also has the same structure as that of the previous embodiment. Similarly, the input signal B has positive and negative polarities.Therefore, the subtracter 26 also has an addition mode and a subtraction mode.Therefore, in this embodiment as well,
Overflow and under 70- can be determined based on the most significant pins (AM and BM) of the input signals A and H and the most significant pin (CM) of the output signal C.

In this case, if the most significant bit (BM) of the input signal B is 0, the input signal B is a positive value, and therefore the subtraction mode is entered. At this time, the highest pitch of the input signal (AM) is 0.
and the highest pitch of the output signal C) CM is 1
If so, it can be determined that the output C of the subtracter 26 is clearly a negative value.

In this embodiment, as in the previous embodiment, the subtracter output signal C is a single-polarity natural binary code. Therefore,
In this embodiment as well, there is no negative value in the output signal of the subtracter 26, which means that an underflow has occurred. From this, underflow is determined by (AMABMACM), and the underflow determination circuit consists of NOT circuit 27 and N
It can be constructed from an OR circuit 28. Furthermore, if the most significant bit (BM) of the input signal B is 1, the input signal B indicates a negative value, and the subtracter 26 enters the addition mode. At this time, if the most significant pit AM to the input signal is 1 and the most significant pit CM of the output signal C is 0, overflow can be determined.

Therefore, the overflow is (AM A BM Ha CM)
The overflow determining circuit can be configured by a NOT circuit 27 and an AND circuit 29. Also in this embodiment, the overflow determination circuit.

The structure of the underflow determination circuit is the same as that of the gate circuit 20.
, 21, an OR circuit is used instead of the NOR circuit 28, and a NAND circuit is used instead of the AND circuit 29.
It is also clear that this can be handled by using an AND circuit. Therefore, it is clear that all of the above-mentioned Kate circuit embodiments can be applied to this embodiment as well as the previous embodiments, and the same effects can be obtained.

FIG. 10 shows still another specific embodiment of the arithmetic circuit 181 discriminating circuit 19 of the present invention. 3o is the arithmetic circuit 1 in Fig. 6.
Adder as 9, 31.34 as NOT circuit, 32.5
3 is an AND circuit, which constitutes the discrimination circuit 19. Similarly to the previous embodiments, the adder 300A output signals A and B in this embodiment are encoded using a unipolar natural binary code, B using a two's complement code, and the output C of the adder 60 is It is encoded using a unipolar natural binary code. Further, the adder 30 has a carry output. In this embodiment, overflow and under 70- are determined based on the most significant focus Bu of the input signal B and the carry output. As in the previous embodiment, the input signal B has positive and negative polarities. Therefore, the adder 30 also has an addition mode and a subtraction mode, and an overflow occurs in the addition mode, and an underflow occurs in the subtraction mode.

Therefore, to determine overflow and underflow,
This can be determined by determining the calculation mode and knowing the state of the carry output of the adder 60 at that time. That is,
When the most significant bit BM of the input signal B is 00, the input signal B is a positive value and is in addition mode. At this time, if the carry output is 1, this clearly means an overflow. Therefore, the overflow is (
BMAD), which can be determined by NOT circuit 31, A
It can be configured with an ND circuit 32. On the other hand, when the most significant bit BM of the input signal B is 1, the input signal B has a negative value, and it can be determined that the mode is the subtraction mode. In this case, when the adder output C shows a negative value, the carry output becomes O.

Therefore, underflow can be determined by (BMAD), and by NOT circuit sa and AND circuit 36,
.

Can be done. The logical formulas used to determine overflow and underflow are (BMVD).

It can be rewritten as (BMVD) and can be configured with a NOT circuit and a NOR circuit instead of a NOT circuit or an AND circuit. Further, the logical format of the gate circuits 20 and 21 can be changed to a NAND AND OR circuit such as the AND circuit and the NOR circuit. It is clear that all the gate circuit embodiments described above can be applied to this embodiment as well as the previous embodiments, and similar effects can be obtained.

FIG. 11 shows still another specific embodiment of the arithmetic circuit 181 discriminating circuit 19 of the present invention. 35 is an AND circuit, 66 is a NOR circuit, which constitute a discrimination circuit, and 37 is a subtracter as an arithmetic circuit. Subtractor 6 in this first embodiment
Similarly to the previous embodiment, the input signals A and B of 7 are encoded using a unipolar natural binary code, and B using a two's complement code.
The output C of the subtracter 67 is a unipolar natural binary code which is subtracted by the sign. The subtracter 67 also has a carry output, and this carry output and the most significant bit BM of the input signal B are used to determine whether an auto-kuichi flow or an underflow occurs. In this embodiment, as in the previous embodiment, since the input signal B has positive and negative polarities, the subtracter 67 has an addition mode and a subtraction mode. Therefore, since an oat(-flow occurs in the addition mode and an underflow occurs in the subtraction mode), the determination can be made by determining the arithmetic mode and the carry output of the subtractor 37, as in the previous embodiment. When the most significant bit BM of input signal B is 1,
The input signal B shows a negative value, indicating that the mode is addition mode. At this time, if the carry output of the subtracter 57 is 1, it is obvious that the output Ch of the subtracter 37 is
This means that it has flowed. Therefore, the automatic flow can be determined by (BMAD), which can be configured by the AND circuit 35. On the other hand, if the most significant bit BM of the input signal B is 0, the input signal B indicates a positive value and enters the subtraction mode. In this case, when the output C of the subtracter 67 has a negative value, that is, underflows, the carry output of the subtracter 67 is 0. Therefore, (BMA
Underflow can be determined in D), jl;+, NO
It can be configured by R circuit B6. In addition, the gate circuit 20
, 21, the AND circuit 65 and the NOR circuit 66 can be replaced by a NAND circuit or an OR circuit. It is clear that all the gate circuit embodiments described above can be applied to this embodiment as well as the previous embodiments, and the same effects can be obtained. Furthermore, the embodiments of the present invention described above are , an adder in the time division multiplex receiver.

In addition to being applicable to the subtracter, the present invention can also be applied to a luminance signal processing unit in a receiver using other time division multiplexing systems. 12 and 13 show the luminance signal processing portion of the receiver. In FIG. 12, 38 is an input terminal, 69 is an A/D converter, 40 is a time axis expander 41 is an interpolation circuit, and 42 is a no.
Innox filter, 43 is a 1H delay line, 44 is an adder,
45 is a D/A converter, and 46 is an output terminal. The time division multiplexing method described here consists of a line that sends only the low-frequency component (Ln) of the luminance signal, the average value of the nth and 1st luminance signals, and the sum of the low-frequency components of the nth and 1st luminance signals (LrL+Hn).
+, Hn++) are transmitted alternately.

In this time-division multiplex receiver shown in FIG. 12, the average value (Hn+, , Hn+) of the high-frequency components of the n-th and R+1-th luminance signals is used to calculate the low-frequency components of the luminance signal. This is intended to interpolate and reproduce the high frequency range of the Ln-only line. Therefore, in FIG.
+) is extracted, and the luminance signal of the nth line (
Ln) in an adder 44, and interpolation of the high frequency component of the n-th luminance signal is performed. The present invention can be applied to the adder 44 at this time. The low frequency component Ln of the luminance signal, which is one input signal of the adder 44, is encoded with a unipolar natural binary code. On the other hand, since the output signal of the bypass filter 42, which is the other input signal of the adder 44, has positive and negative polarities, it is encoded in two's complement. Furthermore, since the output of the adder 44 is encoded into a single-polarity natural binary code, it is obvious that the present invention can be applied thereto.

Next, the time-division multiplexing method shown in Fig. 13 alternately transmits a line (Ln + Hn) containing low-frequency components and high-frequency components of the luminance signal and a line (Ln + +) containing only low-frequency components. . In FIG. 12, 47 is an input terminal, 48
is an A/D converter, 49 is a time axis expander, 5° is a 1H delay line, 51 is a low-pass filter, 52 is a subtracter, 53 is an adder, 54 is a D/A converter, and 55 is an output terminal. . In this time-division multiplexing method, the receiver interpolates the high-frequency components of the line containing only the low-frequency components of the luminance signal (L → 1) with the high-frequency components of the previous line (HrL). In other words, the line (Ln + HrL) containing the low-frequency components and high-frequency components of the luminance signal is subtracted from the signal (LrL) from which only the low-frequency components are extracted by the low-pass filter 51. 52, extracts only the high-frequency component (Hs), and adds it to the next line's luminance signal (LrL+1) consisting only of the low-frequency component in the adder 53. At this time, the adder 56
A luminance signal (Ln+ + ) consisting of only low-frequency components, which is one of the input signals, is encoded with a unipolar natural binary code. The output signal 14FL of the subtracter 52, which is the other input signal, has positive and negative polarities.
is encoded as the complement of . In addition, the adder 5
Since the output signal (Ln++ + Hn) of No. 6 is encoded into a single-polarity natural binary code, it is clear that the present invention can be applied thereto.

In general, there are signal processing systems that transmit arithmetic processing using two signals and regenerate the two signals on the receiver side. It is clear that the present invention is also applicable to a signal processing system in which information from one signal is interpolated and reproduced using information from another signal.

〔Effect of the invention〕

According to the present invention, even if signal processing is performed within the dynamic range of the original signal, image quality deterioration due to overflow and underthrow can be removed. Further, it is no longer necessary to make the dynamic range of the receiver wider than necessary, which leads to a reduction in the circuit scale of the receiver, which also makes it possible to reduce costs.

[Brief explanation of the drawing]

1 and 2 are diagrams showing the main parts of a time division multiplexing transmitter and receiver, which are the premise of the present invention, and FIG.
4 to 7 are diagrams showing specific examples of the gate circuit in FIG. 6, FIG. 8 is a diagram showing a second embodiment of the present invention, and FIG. 9 is a diagram showing a second embodiment of the present invention. FIG. 10 is a diagram showing a fourth embodiment of the invention, FIG. 11 is a diagram showing a fifth embodiment of the invention, and FIG. 12 is a diagram showing a third embodiment of the invention. FIG. 13 is a diagram showing another example of application of the present invention. 18... Arithmetic circuit, 19... Overflow/under 70-discrimination circuit, 2
0, 21... Gate circuit, 22, 30... Adder, 26, 37... Subtractor, 25, 27, 31, 34... NOT circuit, 24
, 29 , 52 , 33 , 35...AND circuit, 2
5, 28, 36...NOR circuit. Patent Attorney Akira Takahashi Me No. 3 En No. 4 Eup No. Sm 蝬 口口 No. 7 n No. 9 Day 16 2ρ 2/ No. 1 O Gu No. I Do σ7 2ψ zl No. 7211 n 3 13th Prisoner

Claims (1)

[Claims] 1. In a digital signal processing circuit for television signals, an adder or subtracter that calculates two input signals and an output signal of the adder or subtracter over 7 days.
and a discrimination circuit for detecting underflow, and a gate circuit whose input signals are an output signal of the adder or subtracter and an output signal of the discrimination circuit. 2. Encoding the first input signal of the adder or subtracter with a unipolar natural binary code, and encoding the second input signal with a two's complement code, and the output signal of the adder or subtracter; 2. The digital signal processing circuit according to claim 1, wherein the digital signal processing circuit encodes the signal using a unipolar natural binary code. 3. The first .3 of the adder or subtracter. the most significant Z of the second input signal and the addition signal; Claim 1 or 2 further comprises a discrimination circuit that detects the overflow and underflow based on the most significant bit of the output signal of the subtractor.
The digital signal processing circuit described in Section 1. 4. Claim 1 or 4, further comprising a discrimination circuit that detects the overflow and underflow based on the carry bit of the adder or subtracter and the most significant bit of the second input signal. 1. Digital signal processing circuit according to item 2. 5. A first gate circuit that receives as input the first output signal of the discrimination circuit and the output signal of the adder or subtracter, and the output signal of the first gate circuit and the second output of the discrimination circuit. 2. The digital signal processing circuit according to claim 1, further comprising a second gate circuit that receives a signal as an input. 6. Said No. 1. The digital signal processing circuit according to claim 1, characterized in that the second gate circuit is constituted by a NAND circuit. Z 1st above. 2. The digital signal processing circuit according to claim 1, wherein the second gate circuit is constituted by a NOR circuit.