CA1171958A - Data rate reduction for digital video signals by subsampling and adaptive reconstruction - Google Patents
Data rate reduction for digital video signals by subsampling and adaptive reconstructionInfo
- Publication number
- CA1171958A CA1171958A CA000369971A CA369971A CA1171958A CA 1171958 A CA1171958 A CA 1171958A CA 000369971 A CA000369971 A CA 000369971A CA 369971 A CA369971 A CA 369971A CA 1171958 A CA1171958 A CA 1171958A
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- CA
- Canada
- Prior art keywords
- signal
- samples
- average
- sample
- data rate
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
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Classifications
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/587—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving temporal sub-sampling or interpolation, e.g. decimation or subsequent interpolation of pictures in a video sequence
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04N—PICTORIAL COMMUNICATION, e.g. TELEVISION
- H04N19/00—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals
- H04N19/50—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding
- H04N19/59—Methods or arrangements for coding, decoding, compressing or decompressing digital video signals using predictive coding involving spatial sub-sampling or interpolation, e.g. alteration of picture size or resolution
Abstract
-14- RCA 74,547A
ABSTRACT OF THE DISCLOSURE
A digital TV system reduces the data rate by transmitting or recording only bytes representing half of the sampled pixels. Steering bits are also transmitted that tell which of the transmitted bytes are the closest match to the untransmitted bytes so the pixels represented by the later can be reconstructed.
ABSTRACT OF THE DISCLOSURE
A digital TV system reduces the data rate by transmitting or recording only bytes representing half of the sampled pixels. Steering bits are also transmitted that tell which of the transmitted bytes are the closest match to the untransmitted bytes so the pixels represented by the later can be reconstructed.
Description
1 -1- RCA 74,547A
DATA RATE REDUCTION FOR DIGITAL VIDEO SIGNALS
BY SUBS~IPLING A~D ADAPTIVE RECONSTRUCTION
-The present invention relates to digital video systems, and more particularly, to systems for reducing the required data rate without sacrificing picture quality.
In digital broadcast systems, the effective use of the data rate is of primary importance. A
reduction in data rate reduces both vide~ tape usage and the necessary transmission bandwidth; however, this must be accomplished while maintaining broadcast quality 15 pictures.
One method of data reduction which is presently under consideration is the process of sub-Nyquist sampling, such as is disclosed in the paper "Sub-Nyquist Encoded PCM NTSC Color Television" by John P. Rossi in the book 20 "Digital Video", a review of SrlPTE papers, and in the article by Leonard S. Golding, "Frequency Interleaved Sampling of a Color Television Signal", IEEE Transactions on Communication Technology, Volume COM-l9, page 972, December, 1971. These sub-Nyquist type systems have 25 samples that lie along diagonals with the distance between the diagonals being greater than the horizontal distance between samples. Since the smaller the distance between samples the greater the resolution, these systems are capable of increasing the horizontal resolution which is 30 available at a given data rate, but at the expense of the diagonal resolution.
It is therefore desired to have a data rate reduction arrangement ~or digital television signals that does not cause any sacrifice in picture quality.
In accordance with the principles of the invention, data rate reduction comprises -dividing a signal into first and second time portions, transmitting the first portion, and transmitting a control signal adapted to control the reconstruction of said second 40 portion from the transmitted first portion.
li7i958 1 -2- RCA 74,547A
In the Drawings:
FIGURE 1 illustrates a raster produced by 5 simultaneous vertical and horizontal scanning of an election beam with sample points thereon;
FIGURE 2 illustrates a sub-sampled version of the same raster;
FIGURE 3 illustrates a block diagram of an 10 encoder for encoding samples of a video signal and control signals in accordance with an embodiment of the invention;
FIGURE 4 illustrates a block diagram of a decoder for decoding information encoded by the apparatus of FIGURE 3;
FIGURE 5 shows a block diagram of a minimum-error logic circuit used in FIGURE 3;
FIGURES 6, 7, 8 and 9 illustrate block diagrams of filters used in FIGURES 3 and 4; and FIGURE 10 shows a block diagram of a digital 20 delay line used in FIGURES 6, 7, 8 and 9.
FIGURE 1 shows a video raster 10 comprising a plurality of horizontal scanning lines 12. Each of the letters "X" represents a sampling point, which typically 25 is 8-bit or byte sampled for a total of 256 gray levels.
These sampling points occur in a preferred embodiment at 14.32~Hz, which is four times the NTSC color subcarrier frequency. This sampling rate results in horizontally adjacent samples occurring at about 70 nanosecond 30 intervals.
FIGURE 2 is a similar drawing wherein corresponding elements have been given corresponding reference numerals. Here each circled "X" represents samples which will not be transmitted or recorded. For 35 each sample that is not so transmitted or recorded, various combinations of the spatially surrounding samples are computed and compared to the sample not transmitted.
For example, the sample representing point 14 is compared with the average of the sampled points above 40 and below it, namely points 16 and 18. It is also li'7~L958 1 -3- RCA 74,547A
compared to the average of points to its left and right, namely points 20 and 22. The sample representing point 14 ls also compared to the average of the transmitted points 24 and 5 26 which are in one diagonal relationship to it, and also to the average of transmitted points 28 and 30 which are in another diagonal relationship to it. Whichever comparison provides the closest match is indicated by "steering" or control bits. These control bits are transmitted as addition-10 al bits along with the samples that represent the uncircledpoints in FIGURE 2, and together with those samples, are used by a decoder to reconstruct a high resolution picture from reduced data rate information.
FIGURE 3 illustrates an encoder for achieving the 15 above-described transmission. An input 32 receives the digitàl video signal having samples occurring, in a particu-lar embodiment, at 14.32~z with 8 bits per sample. The 8 bits of each sample are applied to a delay line 41 and to filters 34, 36, 38 and 40. These filte~s are used to provide 20 the average of the surrounding samples. By "average" is meant adding two signals together and then dividing the re-sulting sum by two. As can be determined by inspection of FIGURE 2, sample points 28 and 30 are spaced in time by two horizontal lines and four signal sampling intervals. This 25 corresponds to approximately 127 microseconds, in the NTSC
system, plus 280 nanoseconds. FIGURE 6 illustrates the details of filter 34 and comprises a digital delay line 600 having a delay of 127 microseconds plus 280 nanoseconds coupled between input terminal 32 and an input terminal of a 30 digital adder 602. Undelayed signals from terminal 32 also are coupled to a second input terminal of adder 602. The digital sum of these signals, corresponding to the video signals at sample points 28 and 30, is obtained at the output terminal of adder 602 and coupled to an input terminal of 35 a digital divider 604. Divider 604 divides this summed signal by two to provide at its output terminal an 8-bit parallel signal representing the average signal of sample points 28 and 30. This averaged signal is coupled to an input terminal of a comparator 42 in FIGURE 3. Delay line 40 41 also comprises an 8-bit digital delay line and has a i:i719S8 delay of about 63.5 microseconds plus 140 nanoseconds. This time is equal to one-half of the total delay of delay line 600 of filter 34, and delays the video at sample point 14 of 5 FIGURE 2 that is not to be transmitted so it will be in time coincidence with the averaged signal from filter 34 so the two signals can be compared by comparator 42. Thus, delay line 41 delayed sample point 14 back to sample point 28 and delay line 600 delayed sample point 30 back to sample ~oint 10 28. Filter 36 supplies the average of points 20 and 22 (a "horizontal" average). It comprises an 8-bit wide digital delay line 702 in EIGURE 7 having delay of about 140 nano-seconds. The input (undelayed) and output (delayed) signals of this delay line are averaged by adder 704 and divider 706.
15 An additional equalizing delay of one line plus 70nanoseconds to compensate for the delay line 41 is provided by delay line 700 within filter 36. The output signal of filter 36 from divider 706 is supplied to a comparator 44 in FIGURE 3.Filter 38 supplies the average of diagonal points 24 and 26(a"second 20 diagonal" average).It comprises an 8-bit digital delay line 802 in FIGURE 8 having a delay of two horizontal lines minus 280 nanoseconds. The delayed and undelayed signals are averaged by adder 804 and divider 806, while the digital signal from input 32 is first delay equalized by a 280 25 nanosecond delay line 800. The output signal from divider 806 is applied to a comparator 46 in FIGURE 3.
Lastly, filter 40 supplies the average of points 16 and 18 (a "vertical" average). It comprises an 8-bit digital delay line 902 in FIGURE 9 having a delay of two horizontal 30 lines. The delayed and undelayed signals are averaged by adder 904 and divider 906, while the digital signal from input 32 is first delay equalized by a 140 nanosecond delay line 900. The output signal from divider 906 is applied to a comparator 48 in FIGURE 3.
FIGURE 10 shows an 8-bit wide delay line for use in the filters 34, 36 38 and 40 and delay 41. It comprises eight shift registers 1002, 1004, 1006, 1008, 1010, 1012, 1014 and 1016, each of which receives one bit of the 8-bits simultaneously present at input 1000. The 40 bits are shifted within the registers under the control of 195~
1 -5- RCA 74,547A
a clock signal from clock 1038 coupled to shift inputs 1018, 1020, 1022, 1024, 1026, 1028, 1030, and 1034. The 5 number of stages of the shift registers are chosen to achieve the desired delay. The outputs of the shift registers are coupled to 8-bit parallel output 1036.
Comparators 42, 44, 46 and 48 each comprise an 8-bit subtractor that also receives the original 8-bit samples 10 through delay line 41 in addition to the outputs of filter 34, 36, 38 and 40 respectively. The respective two signals in each comparator are subtracted and then th~
absolute value is taken of the resulting difference. The comparators apply absolute value signals to a minimum 15 error logic circuit 50.
As shown in FIGURE 5, minimum error logic circuit 50 comprises 6 magnitude comparators 82, 84, 86, 88, 90 and 92, each of which receives two 8-bit numbers from different pairs of the output signals of comparators 42, 20 44, 46 and 48 and supplies at its respective output a one-bit logic level indication to indicate which of the two respective input numbers is smaller. It should be noted that there are only six possible combinations of four numbers taken in pairs, thus giving rise to the six 25 magnitude comparators. It is only necessary to look at three of the magnitude comparator outputs to determine if a specific magnitude comparator input is the lowest.
Thus NOR gates 94, 96, and 98 are used to detect if the output signal from comparators 42, 44, and 46 respectively 30 are the lowest. If none are the lowest, the output signal from 48 is assumed to be the lowest which will be true, or none will be lowest, i.e. they are all equal, in which later case the output signal from any comparator will do.
The output signals from gates 94, 96, and 98 are coded by 35 OR gates 100 and 102 into the 2 bit control signal on bus 104 in accordance with the following truth table~
Line No. ~ Lowest Signal 104a 1 0 1 0 104b 0 1 1 0 li7~958 1 -6- RCA 74,547A
The output of logic circuit 50 comprises two bits in accordance with the above table which indicate which of 5 the pairs of samples of adjacent points is the closest match, i.e. represents which direction has the least change of the video signal around the sample point 14.
This two-bit signal makes up the control signal indicating which of the transmitted video sample signals most closely 10 represents the untransmitted video signal so that complete video information can be obtained upon decoding. The two central bits are applied to a switch 52 in FIGURE 3, which is a two-bit switch operated in synchronization with an 8-bit switch 54 in FIGURE 3 at a 7.16~z switching rate.
lS This switching rate, since it is 14.32~Hz divided by 2, causes switch 54 to pass or transmit only every other 8-bit sample. The 2 control bits from logic circuit 50, that indicate which of the adjacent samples are to be used in reconstructing the untransmitted points, are passed 20 by switch 52, and together with the 8 bits simultaneously passed by switch 54 representing a transmitted point, form a 10-bit parallel word at 10-bit parallel output 55.
FIGURE 4 shows the decoder for use in the present invention. The 10-bit parallel signal is received at 25 input 60. The 8 bits representing a sample of a picture point are applied by 8-bit bus 61 to filters 62, 64, 66 and 68, the internal construction of which is the same as filters 34, 36, 38 and 40 respectively. The same 8 bits are also applied to contact 69a of 8-bit switch 70 30 through delay line 106 that has the same delay as delay line 41 and which compensates for the delay through filters 62, 64, 66, and 68. The two control bits are brought out on 2-bit bus 71 and applied to control decoder 72 for control of switches 74, 76, 78, and 80. This decoder 35 comprises a one-of-four decoder, such as integrated circuit No. SN 74S139, manufactured by Texas Instruments, that takes the two control bits and gives a 4-bit parallel output, only one of which will be high. The 4 parallel bits are applied to the switches 74, 76, 78 and 80 40 respectively. Since only one of the outputs of control 1 -7- RCA 74,547A
decoder 72 will be high, only one of the switches 74, 76, 78 and 80 will be closed at any one time at a 7.16MHz rate.
5 This applies the signal from that one of the filters 62, 64, 66, and 68 which is the closest match for a missing sample to contact 69b of switch 70. Switch 70 is switched at a 14.32MHz rate between its two inputs 69a and 69b, and thus alternately supplies a sample point of the 10 original picture and a reconstructed 8-bit signal to its output 69c. Since each of the signals occurs at a 7.16MHz rate, the resulting signal from output 69c of switch 70 is at 14.32~Hz.
It will be appreciated that the above-described 15 invention may also be implemented as a sample analog system. Further, a single tapped delay line can be used instead of the separate delay lines of filters 34~ 36, 38, and 40. These filters will then just comprise averagers.
The same construction applies with respect to filters 20 62, 64, 66, and 68.
DATA RATE REDUCTION FOR DIGITAL VIDEO SIGNALS
BY SUBS~IPLING A~D ADAPTIVE RECONSTRUCTION
-The present invention relates to digital video systems, and more particularly, to systems for reducing the required data rate without sacrificing picture quality.
In digital broadcast systems, the effective use of the data rate is of primary importance. A
reduction in data rate reduces both vide~ tape usage and the necessary transmission bandwidth; however, this must be accomplished while maintaining broadcast quality 15 pictures.
One method of data reduction which is presently under consideration is the process of sub-Nyquist sampling, such as is disclosed in the paper "Sub-Nyquist Encoded PCM NTSC Color Television" by John P. Rossi in the book 20 "Digital Video", a review of SrlPTE papers, and in the article by Leonard S. Golding, "Frequency Interleaved Sampling of a Color Television Signal", IEEE Transactions on Communication Technology, Volume COM-l9, page 972, December, 1971. These sub-Nyquist type systems have 25 samples that lie along diagonals with the distance between the diagonals being greater than the horizontal distance between samples. Since the smaller the distance between samples the greater the resolution, these systems are capable of increasing the horizontal resolution which is 30 available at a given data rate, but at the expense of the diagonal resolution.
It is therefore desired to have a data rate reduction arrangement ~or digital television signals that does not cause any sacrifice in picture quality.
In accordance with the principles of the invention, data rate reduction comprises -dividing a signal into first and second time portions, transmitting the first portion, and transmitting a control signal adapted to control the reconstruction of said second 40 portion from the transmitted first portion.
li7i958 1 -2- RCA 74,547A
In the Drawings:
FIGURE 1 illustrates a raster produced by 5 simultaneous vertical and horizontal scanning of an election beam with sample points thereon;
FIGURE 2 illustrates a sub-sampled version of the same raster;
FIGURE 3 illustrates a block diagram of an 10 encoder for encoding samples of a video signal and control signals in accordance with an embodiment of the invention;
FIGURE 4 illustrates a block diagram of a decoder for decoding information encoded by the apparatus of FIGURE 3;
FIGURE 5 shows a block diagram of a minimum-error logic circuit used in FIGURE 3;
FIGURES 6, 7, 8 and 9 illustrate block diagrams of filters used in FIGURES 3 and 4; and FIGURE 10 shows a block diagram of a digital 20 delay line used in FIGURES 6, 7, 8 and 9.
FIGURE 1 shows a video raster 10 comprising a plurality of horizontal scanning lines 12. Each of the letters "X" represents a sampling point, which typically 25 is 8-bit or byte sampled for a total of 256 gray levels.
These sampling points occur in a preferred embodiment at 14.32~Hz, which is four times the NTSC color subcarrier frequency. This sampling rate results in horizontally adjacent samples occurring at about 70 nanosecond 30 intervals.
FIGURE 2 is a similar drawing wherein corresponding elements have been given corresponding reference numerals. Here each circled "X" represents samples which will not be transmitted or recorded. For 35 each sample that is not so transmitted or recorded, various combinations of the spatially surrounding samples are computed and compared to the sample not transmitted.
For example, the sample representing point 14 is compared with the average of the sampled points above 40 and below it, namely points 16 and 18. It is also li'7~L958 1 -3- RCA 74,547A
compared to the average of points to its left and right, namely points 20 and 22. The sample representing point 14 ls also compared to the average of the transmitted points 24 and 5 26 which are in one diagonal relationship to it, and also to the average of transmitted points 28 and 30 which are in another diagonal relationship to it. Whichever comparison provides the closest match is indicated by "steering" or control bits. These control bits are transmitted as addition-10 al bits along with the samples that represent the uncircledpoints in FIGURE 2, and together with those samples, are used by a decoder to reconstruct a high resolution picture from reduced data rate information.
FIGURE 3 illustrates an encoder for achieving the 15 above-described transmission. An input 32 receives the digitàl video signal having samples occurring, in a particu-lar embodiment, at 14.32~z with 8 bits per sample. The 8 bits of each sample are applied to a delay line 41 and to filters 34, 36, 38 and 40. These filte~s are used to provide 20 the average of the surrounding samples. By "average" is meant adding two signals together and then dividing the re-sulting sum by two. As can be determined by inspection of FIGURE 2, sample points 28 and 30 are spaced in time by two horizontal lines and four signal sampling intervals. This 25 corresponds to approximately 127 microseconds, in the NTSC
system, plus 280 nanoseconds. FIGURE 6 illustrates the details of filter 34 and comprises a digital delay line 600 having a delay of 127 microseconds plus 280 nanoseconds coupled between input terminal 32 and an input terminal of a 30 digital adder 602. Undelayed signals from terminal 32 also are coupled to a second input terminal of adder 602. The digital sum of these signals, corresponding to the video signals at sample points 28 and 30, is obtained at the output terminal of adder 602 and coupled to an input terminal of 35 a digital divider 604. Divider 604 divides this summed signal by two to provide at its output terminal an 8-bit parallel signal representing the average signal of sample points 28 and 30. This averaged signal is coupled to an input terminal of a comparator 42 in FIGURE 3. Delay line 40 41 also comprises an 8-bit digital delay line and has a i:i719S8 delay of about 63.5 microseconds plus 140 nanoseconds. This time is equal to one-half of the total delay of delay line 600 of filter 34, and delays the video at sample point 14 of 5 FIGURE 2 that is not to be transmitted so it will be in time coincidence with the averaged signal from filter 34 so the two signals can be compared by comparator 42. Thus, delay line 41 delayed sample point 14 back to sample point 28 and delay line 600 delayed sample point 30 back to sample ~oint 10 28. Filter 36 supplies the average of points 20 and 22 (a "horizontal" average). It comprises an 8-bit wide digital delay line 702 in EIGURE 7 having delay of about 140 nano-seconds. The input (undelayed) and output (delayed) signals of this delay line are averaged by adder 704 and divider 706.
15 An additional equalizing delay of one line plus 70nanoseconds to compensate for the delay line 41 is provided by delay line 700 within filter 36. The output signal of filter 36 from divider 706 is supplied to a comparator 44 in FIGURE 3.Filter 38 supplies the average of diagonal points 24 and 26(a"second 20 diagonal" average).It comprises an 8-bit digital delay line 802 in FIGURE 8 having a delay of two horizontal lines minus 280 nanoseconds. The delayed and undelayed signals are averaged by adder 804 and divider 806, while the digital signal from input 32 is first delay equalized by a 280 25 nanosecond delay line 800. The output signal from divider 806 is applied to a comparator 46 in FIGURE 3.
Lastly, filter 40 supplies the average of points 16 and 18 (a "vertical" average). It comprises an 8-bit digital delay line 902 in FIGURE 9 having a delay of two horizontal 30 lines. The delayed and undelayed signals are averaged by adder 904 and divider 906, while the digital signal from input 32 is first delay equalized by a 140 nanosecond delay line 900. The output signal from divider 906 is applied to a comparator 48 in FIGURE 3.
FIGURE 10 shows an 8-bit wide delay line for use in the filters 34, 36 38 and 40 and delay 41. It comprises eight shift registers 1002, 1004, 1006, 1008, 1010, 1012, 1014 and 1016, each of which receives one bit of the 8-bits simultaneously present at input 1000. The 40 bits are shifted within the registers under the control of 195~
1 -5- RCA 74,547A
a clock signal from clock 1038 coupled to shift inputs 1018, 1020, 1022, 1024, 1026, 1028, 1030, and 1034. The 5 number of stages of the shift registers are chosen to achieve the desired delay. The outputs of the shift registers are coupled to 8-bit parallel output 1036.
Comparators 42, 44, 46 and 48 each comprise an 8-bit subtractor that also receives the original 8-bit samples 10 through delay line 41 in addition to the outputs of filter 34, 36, 38 and 40 respectively. The respective two signals in each comparator are subtracted and then th~
absolute value is taken of the resulting difference. The comparators apply absolute value signals to a minimum 15 error logic circuit 50.
As shown in FIGURE 5, minimum error logic circuit 50 comprises 6 magnitude comparators 82, 84, 86, 88, 90 and 92, each of which receives two 8-bit numbers from different pairs of the output signals of comparators 42, 20 44, 46 and 48 and supplies at its respective output a one-bit logic level indication to indicate which of the two respective input numbers is smaller. It should be noted that there are only six possible combinations of four numbers taken in pairs, thus giving rise to the six 25 magnitude comparators. It is only necessary to look at three of the magnitude comparator outputs to determine if a specific magnitude comparator input is the lowest.
Thus NOR gates 94, 96, and 98 are used to detect if the output signal from comparators 42, 44, and 46 respectively 30 are the lowest. If none are the lowest, the output signal from 48 is assumed to be the lowest which will be true, or none will be lowest, i.e. they are all equal, in which later case the output signal from any comparator will do.
The output signals from gates 94, 96, and 98 are coded by 35 OR gates 100 and 102 into the 2 bit control signal on bus 104 in accordance with the following truth table~
Line No. ~ Lowest Signal 104a 1 0 1 0 104b 0 1 1 0 li7~958 1 -6- RCA 74,547A
The output of logic circuit 50 comprises two bits in accordance with the above table which indicate which of 5 the pairs of samples of adjacent points is the closest match, i.e. represents which direction has the least change of the video signal around the sample point 14.
This two-bit signal makes up the control signal indicating which of the transmitted video sample signals most closely 10 represents the untransmitted video signal so that complete video information can be obtained upon decoding. The two central bits are applied to a switch 52 in FIGURE 3, which is a two-bit switch operated in synchronization with an 8-bit switch 54 in FIGURE 3 at a 7.16~z switching rate.
lS This switching rate, since it is 14.32~Hz divided by 2, causes switch 54 to pass or transmit only every other 8-bit sample. The 2 control bits from logic circuit 50, that indicate which of the adjacent samples are to be used in reconstructing the untransmitted points, are passed 20 by switch 52, and together with the 8 bits simultaneously passed by switch 54 representing a transmitted point, form a 10-bit parallel word at 10-bit parallel output 55.
FIGURE 4 shows the decoder for use in the present invention. The 10-bit parallel signal is received at 25 input 60. The 8 bits representing a sample of a picture point are applied by 8-bit bus 61 to filters 62, 64, 66 and 68, the internal construction of which is the same as filters 34, 36, 38 and 40 respectively. The same 8 bits are also applied to contact 69a of 8-bit switch 70 30 through delay line 106 that has the same delay as delay line 41 and which compensates for the delay through filters 62, 64, 66, and 68. The two control bits are brought out on 2-bit bus 71 and applied to control decoder 72 for control of switches 74, 76, 78, and 80. This decoder 35 comprises a one-of-four decoder, such as integrated circuit No. SN 74S139, manufactured by Texas Instruments, that takes the two control bits and gives a 4-bit parallel output, only one of which will be high. The 4 parallel bits are applied to the switches 74, 76, 78 and 80 40 respectively. Since only one of the outputs of control 1 -7- RCA 74,547A
decoder 72 will be high, only one of the switches 74, 76, 78 and 80 will be closed at any one time at a 7.16MHz rate.
5 This applies the signal from that one of the filters 62, 64, 66, and 68 which is the closest match for a missing sample to contact 69b of switch 70. Switch 70 is switched at a 14.32MHz rate between its two inputs 69a and 69b, and thus alternately supplies a sample point of the 10 original picture and a reconstructed 8-bit signal to its output 69c. Since each of the signals occurs at a 7.16MHz rate, the resulting signal from output 69c of switch 70 is at 14.32~Hz.
It will be appreciated that the above-described 15 invention may also be implemented as a sample analog system. Further, a single tapped delay line can be used instead of the separate delay lines of filters 34~ 36, 38, and 40. These filters will then just comprise averagers.
The same construction applies with respect to filters 20 62, 64, 66, and 68.
Claims (7)
1. A method of reducing the data rate of a digital color video signal comprising signal samples-representing successive picture samples in successive scan lines by taking only alternately occurring signal samples, the points represented by the taken samples in one line being staggered relatively to those in adjacent lines, and by providing,instead of each omitted signal sample, a digital control signal for controlling reconstruction of the omitted sample from adjacent taken samples, wherein said control signal is indicative of which one of the following represents a closest match to the omitted sample, namely the average of the taken samples which represent points above and below the point represented by the omitted sample in adjacent lines (vertical average), the average of the taken samples which represent points immediately to the right and left of that point (horizontal average), the average of taken samples which represent points diagonally adjacent that same point in one diagonal direction (first diagonal average), and the average of taken samples which represent points diagonally adjacent that point in another diagonal direction (second diagonal average).
2. A method according to claim 1 wherein the signal samples are 8-bit bytes and the control signals are 2-bit bytes.
3. Apparatus for performing data rate reduction by the method of claim 1 comprising four averaging circuits responsive to said digital signal for providing,to respective comparison circuits, signals representing said vertical, horizontal and diagonal averages respectively, said comparison circuits also receiving from said digital signal the samples to be omitted and providing respective output signals representative of the difference between each omitted sample and the respective one of said averages, and a circuit responsive to the output signals from the comparison circuits for determining which one of them represents the smallest difference.
4. Apparatus as claimed in claim 3 wherein said averaging circuits are averaging filters.
5. Apparatus as claimed in claim 3 or claim 4 wherein said circuit is a minimum error logic circuit.
6. Apparatus for receiving a digital color video signal which has had its data rate reduced by a method according to claim 1, said apparatus including means for passing the signal samples in said signal to an output , four averaging circuits responsive to said samples for providing respective reconstruction signals representing said vertical, horizontal and diagonal averages, and switching means controlled by the control signals in the received signal for selectively passing to said output, at times between signal samples passed thereto, the reconstruction signal indicated by said control signal as being the closest match to the signal originally omitted between said samples.
7. Apparatus according to claim 6 characte-rised in that said averaging circuits are averaging filters.
Applications Claiming Priority (6)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| GB8004195 | 1980-02-07 | ||
| GB8004195 | 1980-02-07 | ||
| US13213780A | 1980-03-20 | 1980-03-20 | |
| US132137 | 1980-03-20 | ||
| US168077 | 1980-07-14 | ||
| US06/168,077 US4323916A (en) | 1980-02-07 | 1980-07-14 | Data rate reduction for digital video signals by subsampling and adaptive reconstruction |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1171958A true CA1171958A (en) | 1984-07-31 |
Family
ID=27260857
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000369971A Expired CA1171958A (en) | 1980-02-07 | 1981-02-03 | Data rate reduction for digital video signals by subsampling and adaptive reconstruction |
Country Status (3)
| Country | Link |
|---|---|
| CA (1) | CA1171958A (en) |
| DE (1) | DE3104439A1 (en) |
| FR (1) | FR2475833B1 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4340940A (en) * | 1980-08-26 | 1982-07-20 | Rca Corporation | Hardware reduction by truncation of selected number of most significant bits for digital video system using subsampling and adaptive reconstruction |
| US4320416A (en) * | 1980-10-15 | 1982-03-16 | Rca Corporation | Technique for optimally encoding digitally encoded video signals |
| US4376948A (en) * | 1981-01-26 | 1983-03-15 | Rca Corporation | TDM Scheme for digital video processing |
| DE3400908A1 (en) | 1984-01-12 | 1985-09-26 | Siemens AG, 1000 Berlin und 8000 München | METHOD FOR DETERMINING THE ERROR BAND LENGTH |
Family Cites Families (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| FR2320017A1 (en) * | 1975-07-29 | 1977-02-25 | Telecommunications Sa | Reduction of information for image coding - uses transmission of every other point with correlation bit describing untransmitted point |
| DE2701649C2 (en) * | 1977-01-17 | 1985-09-19 | Robert Bosch Gmbh, 7000 Stuttgart | Method for the digital transmission of the luminance signal of a separately coded color video signal |
| FR2489061A1 (en) * | 1980-08-20 | 1982-02-26 | France Etat | Image digital transmission circuit - samples image and transmits selected samples with restoration of omitted samples in receiver |
-
1981
- 1981-02-03 CA CA000369971A patent/CA1171958A/en not_active Expired
- 1981-02-06 FR FR8102388A patent/FR2475833B1/en not_active Expired
- 1981-02-09 DE DE19813104439 patent/DE3104439A1/en active Granted
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| Publication number | Publication date |
|---|---|
| FR2475833A1 (en) | 1981-08-14 |
| FR2475833B1 (en) | 1986-10-31 |
| DE3104439C2 (en) | 1988-10-06 |
| DE3104439A1 (en) | 1982-01-07 |
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