JPH06334981A - Picture encoder - Google Patents

Abstract

PURPOSE:To provide the picture encoder which does not require the control of the generated information volume or the like and performs the real-time processing with a simple configuration. CONSTITUTION:In this picture encoding device, the difference between the present frame of a digital picture signal and the preceding frame obtained by a delay circuit 7 is taken by a difference device, and the extent of the difference is classified to plural stages, and the stage which the extent of difference corresponds to is discriminated by a frame discriminating circuit 9 with respect to each frame of the picture signal, and the frame signal is selectively led to a corresponding system in a certain proportion, and frame signals selectively led by the frame discriminating circuit 9 are subjected to band compression at encoding speeds different from one another by encoding circuits 101 to 10x provided in respective systems, and these compressed signals have frames synchronized by plural frame synchronizing circuits 111 to 11x and are multiplexed in accordance with a prescribed frame format by a different speed multiplexing circuit 12.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an image coding apparatus for multiplexing a plurality of image compression signals band-compressed by a plurality of coding circuits at different speeds for transmission.

[0002]

2. Description of the Related Art A conventional image coding apparatus is constructed as shown in FIG. In FIG. 3, when a digital image signal a output from an image signal processing unit (not shown) is supplied to the input terminal 1, this digital image signal a is distributed and supplied to the x-system predictive coding circuits 21 to 2x. To be done.

The predictive coding circuits 21 to 2x perform predictive coding processing on one frame of each input image signal on a pixel-by-pixel basis to obtain prediction error signals b1 to bx. The prediction error signals b1 to bx are respectively provided in the variable length coding circuit 31.
~ 3x.

The variable length coding circuits 31 to 3x perform variable length coding of the prediction error signals b1 to bx, and the coded signals c1 to cx obtained here are supplied to the buffer memories 41 to 4x, respectively. To be done.

Each of the buffer memories 41 to 4x has 1
Data is smoothed by accumulating data for each frame. The accumulated signals d1 to dx are supplied to the encoding control circuits 51 to 5x, respectively, and the smoothed data signals f1 to fx are multiplexed. It is supplied to the circuit 6.

The encoding control circuits 51 to 5x store the accumulated signals d1 to dx in the corresponding predictive encoding circuits 31 to 3x, respectively.
Based on the control signals e1 to ex to control the quantization levels of the predictive coding circuits 21 to 2x and the number of pixels to be coded, thereby smoothing the data generation amount. The multiplexing circuit 6 multiplexes the data signals f1 to fx of each system, and the generated multiplexed signal 1 is sent to a transmission line interface unit (not shown).

However, since the conventional image coding apparatus performs predictive coding and the like, when the amount of generated information fluctuates over time, the buffer memory overflows and the real-time processing is performed. Therefore, a circuit for controlling the amount of generated information is required, and the circuit is complicated.

[0008]

As described above, in the conventional image coding apparatus, the buffer memory does not overflow and the real-time processing is realized when the amount of generated information varies greatly with time. Requires a circuit for controlling the amount of generated information, and the circuit is complicated.

The present invention has been made to solve the above problems, and an object of the present invention is to provide an image coding apparatus which does not require control of the amount of generated information and which can be processed in real time with a simple structure. And

[0010]

In order to achieve the above object, an image coding apparatus according to the present invention comprises a one-frame delay circuit for delaying a digital image signal by one frame, a current frame and one frame of the digital image signal. The difference device that takes the difference from the previous frame obtained by the delay circuit and the difference amount output from the difference device are divided into a plurality of stages, and it is determined at which stage the difference amount is for each frame of the digital image signal. , A frame determination circuit for selectively deriving a digital image signal of the frame to a corresponding system at a fixed ratio,
A plurality of encoding circuits, which are provided in respective systems corresponding to the stages of the difference amounts, and which band-compress digital image signals for one frame selectively derived by the frame determination circuit at mutually different encoding speeds, A plurality of frame synchronization circuits that respectively synchronize the frames of the plurality of compressed signals output from the plurality of encoding circuits, and a plurality of frame-synchronized compressed signals output from the plurality of frame synchronization circuits into a predetermined frame format. And a multiplexing circuit for multiplexing.

[0011]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

FIG. 1 shows the configuration of an image coding apparatus according to the present invention. A digital image signal a supplied from an image signal processing section (not shown) to an input terminal 1 is delayed by one frame for each frame. It is supplied as an input signal to the circuit 7 and the differentiator 8.

The 1-frame delay circuit 7 outputs the input signal a to 1
The delay signal g is delayed by the frame, and the delay signal g
Is supplied to. The differentiator 8 takes the difference between the current frame which is the input signal a and the previous frame which is the delayed signal g,
The difference amount h obtained here is supplied to the frame determination circuit 9.

The frame determination circuit 9 receives the input signal a, divides the difference amount h into x stages, determines which stage each frame of the input signal a corresponds to the difference amount, and outputs the difference to the corresponding system. The digital image signal i of the frame is selectively derived at a constant rate.

That is, the frame determination circuit 9 derives the digital image signal i of a frame having a very large difference amount to the first encoding circuit 101 at a constant ratio, and the digital image of the frame having a second largest difference amount. The signal i is derived at a constant rate to the second encoding circuit 102, and similarly, the digital image signal i of a frame having a very small difference amount is derived at a constant rate to the xth encoding circuit 10x. For example, the destination of the digital image signal i to the encoding circuits 101 to 10x is determined according to the difference amount.

The first to xth encoding circuits 101 to 10x
Is to multiplex a control signal, a frame pulse, etc. with respect to each input digital image signal, band-compress them with different compression rates, and encode them into a predetermined format. However, each has a different encoding speed, the first encoding circuit 101 has the highest encoding speed, and the xth encoding circuit 10x has the lowest encoding speed.

Here, the first to xth encoding circuits 1 are
01 to 10x code the digital image signal i at different speeds, but the coding speeds are always constant. The compressed signals j1 to jx obtained by these encoding circuits 101 to 10x are independent frame synchronizing circuits 111, respectively.
~ 11x.

The frame synchronizing circuits 111 to 11x respectively compress the band-compressed signals j1 to j at different compression rates.
A frame signal is detected for x to perform frame synchronization, and the frame synchronization signals k1 to kx are both supplied to the different speed multiplexing circuit 12.

In the different speed multiplexing circuit 12, allocation of bit rates of different frames is determined in advance for each input system, and the frame synchronization signals k1 to k1.
Frame multiplexing is performed at a bit rate assigned based on kx. This multiplexed signal 1 is led from the output terminal 13 to a transmission system (not shown).

In the receiving section, the control signal multiplexed into the multiplexed signal l performs the operation reverse to the encoding processing of the transmitting section to perform decoding.

The operation of the above configuration will be described below with reference to FIG.

FIG. 2 shows a frame structure in each part when the number x of encoding circuits is 7, a fixed ratio is 1/7, and an allocation cycle is 7 frames.

FIG. 2A shows frame synchronization signals k1 to k7.
The frame configuration of FIG. 4 is shown, and data bits such as the frame pulse F, the image data V, and the control signal P are assigned to each frame. By multiplexing these signals, the multiplexed signal 1 shown in FIG. 2B is obtained.

In FIG. 2, as an example, k1 = 1.536.
[Mbps], k2 = 768 [Kbps], k3 = 38
4 [Kbps], k4 = 192 [Kbps], k5 + k
The case of 6 + k7 = 64 [Kbps] is shown.

FIG. 2B shows an example of a multiframe structure of the multiplexed signal l. Let us assume that the transmission rate of multi-frame data is 3.072 [Mbps]. The allocation of the frame signals k1 to k7 of the frame data of FIG. 2B does not change for each multiframe. The different speed multiplexer 12 uses the multi-frame pulse MF, the multi-control signal MP, and the frame synchronization signal k1 that form a multi-frame.
~ K7 different speed multiplexing is performed.

The value of x, the period of allocation, and the value of allocation to each coding circuit are used for practical coding such as the degree and delay of the movement of the image signal, the output data rate, and the limitation of the output data amount. It can be appropriately selected depending on the purpose of the circuit.

Therefore, the image coding apparatus having the above configuration has a plurality of coding circuits for coding at different transmission speeds, increases the coding speed of the moving part, and slows the coding speed of the static part. Then, after compressing each, the frames are synchronized and different speed multiplexing is performed according to the difference amount, so compared with the conventional encoding circuit,
Compared with the above, real-time processing can be performed with a simple circuit without requiring control of the amount of generated information.

It is needless to say that the present invention is not limited to the above-mentioned embodiments, and that various modifications can be made without departing from the scope of the present invention.

[0029]

As described above, according to the present invention, it is possible to provide an image coding apparatus which does not require control of the amount of generated information and which can be processed in real time with a simple structure.

[Brief description of drawings]

FIG. 1 is a block configuration diagram showing a configuration of an image encoding apparatus according to an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a frame structure of the same embodiment.

FIG. 3 is a block configuration diagram showing a configuration of a conventional image encoding device.

[Explanation of symbols]

 1 Input Terminals 21-2x Predictive Encoding Circuit 31-3x Variable Length Encoding Circuit 41-4x Buffer Memory 6 Multiplexing Circuit 7 1 Frame Delay Circuit (D) 8 Differentiator 9 Frame Judgment Circuit 101-10x Encoding Circuit 111- 11x frame synchronization circuit 12 different speed multiplexing circuit 13 output terminal a input signal (digital image signal) b1 to bx prediction error signal c1 to cx coded signal d1 to dx accumulated signal e1 to ex control signal f1 to fx data signal g delay Signal h Difference amount i Digital image signal j1 to jx Compressed signal k1 to kx Frame synchronization signal l Multiplex signal F Frame pulse V Image data P Control signal MF Multi frame pulse MP Multi control signal

Claims (1)

[Claims] 1. A one-frame delay circuit for delaying a digital image signal by one frame, a differentiator for calculating a difference between a current frame of the digital image signal and a previous frame obtained by the one-frame delay circuit, and the differentiator. The difference amount output from is divided into multiple stages,
A frame determination circuit that determines at which stage the difference amount is present for each frame of the image signal, and selectively derives the digital image signal of the frame to the corresponding system at a fixed ratio, and the difference amount of each of the difference amounts. A plurality of encoding circuits which are provided in each system corresponding to the stages and which band-compress digital image signals for one frame selectively derived by the frame determining circuit at encoding rates different from each other; A plurality of frame synchronization circuits for respectively synchronizing the frames of the plurality of compressed signals output from the multiplexing circuit and the plurality of frame-synchronized compressed signals output from the plurality of frame synchronization circuits are multiplexed in a predetermined frame format. An image coding apparatus, comprising: