JPH0813139B2 - Encoder - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an apparatus for sampling and quantizing an information signal to be transmitted in the time axis direction, converting the information signal into a digital signal and transmitting the signal, and particularly to a device for decoding. The present invention relates to an encoding device that prevents the inversion phenomenon of an information signal.

[Conventional technology]

In a device that converts an image signal into a digital signal as a transmission signal and transmits the signal, the number of quantization bits per one sample value (hereinafter, referred to as a pixel) is usually 7 to 8 bits in the case of linear quantization. is required. If the image signal is digitized as it is by this linear quantization, the transmission rate of the digital signal is required to be about 100 Mbit / sec in the case of the standard TV system, which leads to the high-definition TV system proposed by some. 2 of the above standard method
Transmission rate more than double is required.

In a device that magnetically records and reproduces this image signal with a digital signal (hereinafter referred to as a digital VTR), since the transmission rate is extremely high as described above, the recording density of the tape is higher than that of the conventional analog recording system VTR. Since the recording time is substantially reduced, a sufficient recording time cannot be obtained, and the signal to be handled becomes a very wide band, the operation speed of the digital signal processing circuit becomes a problem, and technically difficult.
This is a major obstacle to the widespread use of R for home use.

In order to improve such a problem, so-called high-efficiency coding has been studied in the past, and an example thereof is described in detail in the literature (Takahiko Fukibe, "Digital Signal Processing of Images", Nikkan Kogyo Shimbun). As described in this document (Chapter 9), as a method of reducing the number of bits per sampled value, the current value is predicted from the already coded pixel value, and the error from that is predicted. The so-called predictive coding method (DPCM) for encoding is well known.

Hereinafter, a conventional technique will be described with reference to the drawings. FIG. 2 is a block diagram showing an example of a conventional encoder in a predictive coding system using a priori prediction, FIG. 4 is a block diagram showing an example of a decoder in the predictive coding system, and FIG. FIG. 6 is a characteristic diagram showing an example of the coding characteristic / decoding characteristic in FIGS. 2 and 4.

In FIG. 2, an image signal converted into a digital signal A having a quantization bit number n bits by an A / D converter is supplied from a terminal 50.

Here, the number of quantization bits n is a large value such that the quantization error can be ignored, and in this example in which an image signal is handled, for example, n = 7 is set.

This n = 7-bit digital signal A is one sample (one pixel) obtained by the subtracter 51 by the subtractor 51, the adder 52 and the delay device 53 having a delay time equal to the pixel interval.
The previous digital signal is subtracted, the 8-bit differential signal C from the subtractor 51 is converted by the read-only memory ROM 54 having the conversion characteristic shown in FIG. 6, and the m = 4 bit compressed differential signal E is output. . The 4-bit compressed differential signal E is transmitted or recorded via the terminal 55.

Then, at the time of reception or reproduction, in FIG. 4, a compression differential signal I ′ of m = 4 bits equivalent to the compression differential signal E is input through the terminal 32 and has the conversion characteristic shown in FIG.
The 8-bit difference signal C ″ is output after being converted by the ROM 33.

The difference signal C ″ is added by the adder 34 to the digital signal of one sample (one pixel) before from the delay device 35 having a delay time equal to the pixel interval, and the digital signal A ′ similar to the digital signal A is added. The digital signal A'is output through the terminal 36, converted into an analog signal by the D / A converter, and then output as an image signal.

According to the predictive coding method as described above, the number of bits per pixel can be reduced to about 4 bits, and the number of bits can be reduced to 4/7 as compared with the linear quantization method described above. .

[Problems to be solved by the invention]

The range of the quantization level of the input / output signal in the predictive coding and decoding apparatus using the previous value prediction is -64 to +63 by setting the quantization bit number to 7 bits.

At this time, if the input digital signal A of n = 7 bits changes, for example, −31 → 62 → 25 → 10 →→ 35 ..., the 8-bit difference signal C from the subtractor 51 is −31 → 93 → −37
→ −15 → 25 ... and the compression difference signal E from the ROM 54 is
-5 → 7 → -5 → -4 → 4 ... m = 4 corresponding to each
It is transmitted or recorded as bit data. At the time of reception or reproduction, a 4-bit compressed differential signal I ′ equivalent to the compressed differential signal E is input via the terminal 32 and the ROM3
The 8-bit difference signal C ″ from 3 is −31 → 110 → −31 →
-17 → 31 ... And the output digital signal A ′ from the adder 34 becomes −31 → 79 (−49) → 48 → 31 → 62 ...
Due to the data 79 having a level exceeding the quantization level range (-64 to +63) of the bit number n = 7, the data -49 inverted to the opposite polarity level is output.

 Therefore, the inversion phenomenon of the information signal occurs.

As described above, in the conventional predictive coding apparatus, the data inverted to the opposite polarity level is output due to the data of the level exceeding the quantization level range of the bit number n at the time of decoding, and the information signal is inverted. There was a problem such as the phenomenon.

In view of the above-mentioned conventional technique, it is an object of the present invention to provide an encoding device in which an inversion phenomenon of an information signal does not occur during decoding.

[Means for solving problems]

In order to achieve the above object, the present invention encodes an information signal to be transmitted with a sufficient number of quantization bits n such that its quantization error can be ignored, and calculates a prediction value corresponding to the encoded sample. , The n-bit sample value is converted into the data of the bit number m smaller than n based on the data of the bit number n excluding the most significant bit of the difference data from the predicted value. Then, one bit is added to the data of the bit number n obtained by the conversion means equivalent to that at the time of decoding based on the data of the bit number m as the most significant bit as the most significant bit. The data of the number of bits n + 1 with added bits and the data showing the quantization level of the above-mentioned prediction value of the number of bits n expressed by the number of bits n + 1 are added, and the number of bits n + 1 excluding the most significant bit of the added data is added. According to the level comparison result of the data and the data indicating the maximum or minimum quantization level of the bit number n expressed by the bit number n + 1, the data of the bit number m is discriminated with the same polarity and an absolute value one step lower. The data is configured to be switched and transmitted to the data having the number of bits m.

[Action]

The inversion phenomenon at the time of decoding can be detected at the time of encoding based on the comparison result.

As a result, the data of the bit m to be transmitted is switched to the data of another bit number m having the same polarity and an absolute value one step lower, and the data is transmitted. The level does not exceed the range, and the inversion phenomenon does not occur.

〔Example〕

In general, the predictive coding method is a method of converting difference data having a bit number n + 1 by subtracting data having a bit number n into data having a bit number m smaller than n, and the error due to the conversion is large.

Therefore, a method is conceivable in which the data of the bit number n excluding the most significant bit of the difference data, that is, the data corresponding to the absolute value of the difference data is converted into the data of the bit number m.

According to this method, compared with the case of converting the data of the number of bits n + 1, the error due to the conversion is about 1/2.
Can be

In the following, the method of converting the data of the bit number n excluding the above-mentioned most significant bit into the data of the bit number m is taken as an example,
Embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment in which the present invention is applied to a magnetic recording / reproducing apparatus such as a VTR, and FIG. 3 is a block diagram showing an embodiment of an encoder 3 according to the present invention.
FIG. 6 is a block diagram showing an embodiment of the decoder 12 according to the present invention, FIG. 5 is a waveform diagram of each part for explaining the operation of the encoder / decoder in FIGS. 3 and 4, and FIG. It is a characteristic view which shows one Example of a characteristic and a decoding characteristic.

In FIG. 1, 1 is an input terminal of an image signal to be recorded, 2 is an A / D converter, 3 is an encoder, 4 is a PCM processor,
5 is a memory, 6 is a modulator, 7 is a recording amplifier, 8 is a magnetic head, 9 is a magnetic tape, 10 is a reproduction equalizer, 11 is a demodulator, 12 is a decoder, 13 is a D / A converter, and 14 is reproduced. It is an output terminal for the image signal.

The image signal V from the terminal 1 is converted by the A / D converter 2 into the digital signal A with the quantization bit number n bits. This n-bit digital signal A is the encoder 3 according to the present invention.
Bit compression is appropriately performed as described later.

The output I of the encoder 3 (hereinafter, abbreviated as data I) is sequentially written in the memory 5 via the PCM processor 4. At the time of writing to the memory 5, an address code indicating the address and a so-called parity code for code correction are added to each block having a predetermined number of bits of the data I and sequentially written to the memory 5.

After the writing to the memory 5 is completed, the data I, the address code, and the parity code that are read subsequently are converted by the PCM processor 4 from parallel data to serial data, and an error for locating the block is found. A start code and the like are appropriately added before and after the detection code or these data strings and output.

The output data string L from the PCM processor 4 is modulated by the modulator 6 into a code suitable for magnetic recording.
The output is sequentially recorded on the magnetic tape 9 by the magnetic head 8 via the recording amplifier 7.

Next, in the reproducing system, from the magnetic tape 9 to the magnetic head 8
The signal reproduced by is reproduced and equalized by the reproduction equalizer 10 as appropriate, and then demodulated by the demodulator 11 to output a signal L ′ similar to the data string L input to the modulator 6.
The output data string L'from the demodulator 11 is subjected to data cueing for each block in the PCM processor 4 based on the synchronization code, and code error detection based on the error detection code. The serial data is converted into parallel data and then sequentially written in the memory 5.

The data written in the memory 5 is the PCM processor 4
After that, the redundant code is sequentially canceled based on the parity code, the redundant code is sequentially canceled, and the same data I ′ as the output data I from the encoder 3 is output to the decoder.
Supplied to 12.

The n-bit digital signal A'is decoded by the decoder 12 and this digital signal A'is output by the D / A converter 1.
The original image signal V'is converted into an analog signal at 3 and is restored to the terminal 14 for output.

Next, the operation of the encoder 3 according to the present invention will be described with reference to the waveform diagram of FIG. 5 according to an embodiment shown in FIG.

In FIG. 3, reference numeral 15 is an input terminal for the n-bit digital signal A output from the A / D converter 2. Fifth
As shown in (1) of the figure, the image signal V input from the terminal 1 is sequentially sampled by the A / D converter 2 at every sampling period τ, and an n-bit digital signal Ai corresponding to the level of each sample value is obtained. Are sequentially converted to and output.

Here, the number of quantization bits n is a large value such that the quantization error can be ignored, and in the present embodiment that handles image signals, for example, n = 8 is set.

According to the present invention, an image signal to be recorded is encoded with a sufficient number of quantization bits n so that its quantization error can be ignored, a predicted value corresponding to the encoded sample value is obtained, and the sample value is predicted. The difference data associated with the value is encoded with the number of bits m smaller than the value n based on the n-bit data excluding the most significant bit.

FIGS. 3 and 5 show an embodiment in which n = 8 bits, m = 4 bits, and the predicted value corresponding to the sample value is the sample value one sample before.

Then, data indicating the maximum quantization level (for example, +127) of the bit number n expressed by the bit number n + 1, and the minimum quantization level (for example, −128) of the bit number n expressed by the bit number n + 1. , The data having the bit number n (= 8) obtained by bit-expanding the data having the bit number m (= 4) by the bit expanding means equivalent to that at the time of decoding is assigned the same code as the most significant bit of the difference data. It is determined whether or not the inversion phenomenon of the image signal occurs at the time of decoding by level comparison with the data of the number n + 1 of bits added by 1 bit as the upper bit.

Then, based on this determination result, the bit number m
The data of (= 4) is switched to the data of the same polarity with the absolute value one step lower and the number of bits m (= 4) is changed to the encoder 3
It is possible to prevent the inversion phenomenon of the image signal from occurring at the time of decoding by outputting as the output signal I from the.

The encoding method based on the above principle is performed as follows.

In FIG. 3, an n (= 8) -bit digital signal A (a in FIG. 5 (2)) input from the terminal 15 is supplied to the subtractor 16 and the predicted value B (fifth value) from the delay circuit 18 is input. B) of FIG. 2B is subtracted.

The predicted value B from the delay circuit 18 is the output signal C2 from the subtracter 16 (c in FIG. 5 (2)) and 1 from the delay circuit 18.
The output signal B before the step (1 pixel) is added by the adder 17, and the output signal D (d in FIG. 5 (2)) from the adder 17 is output by the delay circuit 18 for 1 sample (1 This signal is delayed by a time τ equal to the (pixel) interval and is a signal corresponding to the digital signal A one sample before the digital signal A.

Therefore, the output signals C1 and C2 from the subtractor 16 are difference signals (c in FIG. 5 (2)) between the digital signal A and the digital signal A one sample before. This output signal C1
Is a 1-bit signal indicating the sign of the most significant bit of the difference signal, and the output signal C2 is n (=
8) Bit difference signal, read-only memory ROM1
Supplied as 9 address signals.

ROM 19 is the difference signal C of n (= 8) bits from the subtracter 16.
It has a function of converting 2 into m (= 4) bits.

FIG. 6 shows an example of conversion characteristics in the ROM 19 when n = 8 and m = 4. In ROM19, -8 ~ shown in FIG.
A total of 16 (ie 4 bit equivalents) data corresponding to +7 has been written and these data are addressed and read according to the n (= 8) bit difference signal C2 from the subtractor 16.

As an example, as shown in FIG. 6, when the value of the difference signal C2 is 77, the signal E of m (= 4) bits corresponding to 6 is obtained.
(E in FIG. 5 (2)) is output from the ROM 19. Thus, in the ROM 19, the n (= 8) -bit difference signal C2 from the subtractor 16 is converted into m (= 4) bits.

The output signal E from the ROM 19 converted into m (= 4) bits is supplied to one of the adder 23, the subtractor 24 and the data selector 29, and is also supplied to the read-only memory ROM 20. ROM20 is the ROM for decryption (ROM33 in Figure 4)
The output signal E of the m (= 4) bits from the ROM 19 has the same function as that of the n (=
8) It has the function of converting to bits.

As an example, as shown in FIG. 6, when the output signal E of m (= 4) bits is data corresponding to 6,
31 when the data with the value of is the data corresponding to 4
The data having the value of is output from the ROM 20 as the signal C2 '. The output signal C2 'from the ROM 20 converted into n (= 8) bits is a 1-bit signal C1 indicating the sign of the most significant bit of the difference data from the subtracter 16 in the data synthesizer 21.
Is added as the most significant bit, and the number of bits n +
Data C'of 1 (= 9) (c 'in FIG. 5 (2)) is output. The output data C'from this data synthesizer 21 is
In the adder 22, the predicted value B from the delay device 18 is added.
Here, the prediction value B is data indicating the quantization level of the prediction value of the bit number n expressed by the bit number n + 1.
(For example, the same sign as the most significant bit of the prediction value of the number of bits n is obtained by adding 1 bit as the most significant bit to the prediction value of the number of bits n). The addition data from the adder 22 is the most significant bit. , Then the number of bits n + 1
The added signal F (= 9) (f in FIG. 5 (2)) is supplied to one of the comparators 27 and 28. Here, the addition signal F corresponds to the data corresponding to the original sample value A obtained by decoding. The other level of the comparator 27 is output from the maximum level generation circuit 25 that outputs data indicating the maximum quantization level of the bit number n expressed by the bit number n + 1 (for example, +127 when n = 8). Output signal MA
X is the minimum level that outputs the data indicating the minimum quantization level of the number of bits n expressed by the number of bits n + 1 (eg, −128 when n = 8) to the other side of the comparator 28. The output signal MIN from the generating circuit 26 is supplied.

On the other hand, the other one of the data selectors 29 has 1 (1) from the m (= 4) -bit output signal E from the ROM 19 obtained by the subtractor 24.
Data is supplied in steps, that is, by subtracting 1 LSB. For example, when the output signal E is data corresponding to 6, the adder 24 outputs data corresponding to 5 and when the output signal E is data corresponding to 3, data corresponding to 2 is output. At this time, in the present embodiment in which n = 8 and m = 4, the output signal E of m (= 4) bits from the ROM 19 is the data selector.
It is recorded as it is via 29,30, and at the time of decoding, the reproduced n (= 4) -bit data is converted into n (=
8) The level when the predicted value obtained by the calculating means described later is added to the bit data exceeds the maximum quantization level (+127) of the number of bits n (= 8), and the minimum quantization level. Even when the data inverted in the direction is output, the difference data obtained by subtracting one step (1 LSB) from the output signal E from the ROM 19 obtained by the subtractor 24 is added to the ROM 19
In the case of recording in place of the output signal E from, the level of the data obtained by adding the prediction value to the n (= 8) -bit data obtained by converting the reproduction signal at the time of decoding is the maximum quantization. It does not exceed the level (+127).

Therefore, in the data selector 29, the output signal E from the ROM 19 and the difference data from the subtractor 24 are
It is selectively output according to the output signal. That is, when (the output signal MAX from the maximum level generating circuit 25)> (the output signal F from the adder 22), the output signal E from the ROM 19 is selectively output, and conversely (from the maximum level generating circuit 25 Output signal
When MAX) <(output signal F from the adder 22), the difference data from the subtractor 24 is selectively output.

The output signal from the data selector 29 is supplied to one side of the data selector 30, and the other side has an adder 23
Data obtained by adding 1 step, that is, 1 LSB, is supplied to the m (= 4) -bit output signal E from the ROM 19 obtained in. For example, when the output signal E is the data corresponding to -7, the data corresponding to -6 is, and when the output signal E is the data corresponding to -5, the data corresponding to -4 is the adder 23.
Will be output.

At this time, in the present embodiment in which n = 8 and m = 4, the output signal E of m (= 4) bits from the ROM 19 is the data selector 29,3.
M directly recorded via 0 and replayed during decoding
The level obtained by adding the prediction value obtained by the calculating means described later to the n (= 8) -bit data obtained by converting the (= 4) -bit data is the minimum of the number of bits n (= 8). Even when the data becomes less than the quantization level (-128) and the data inverted in the maximum quantization level direction is output, the output signal E from the ROM 19 obtained by the adder 23 has one step (1
Output signal E from ROM19
In the case of recording instead of, the data level obtained by adding the predicted value to the n (= 8) -bit data obtained by converting the reproduction signal at the time of decoding is the minimum quantization level (-12
8) Not less than

Therefore, the data selector 30
The output signal from 29 and the addition data from the adder 23 are selectively output by the output signal from the comparator 28. That is,
If (the output signal MIN from the minimum level generation circuit 26) <(the output signal F from the adder 22), the data selector 29
If the output signal from the adder 23 is selectively output and conversely (the output signal MIN from the minimum level generating circuit 26)> (the output signal F from the adder 22), the addition data from the adder 23 is selectively output. .

Thus, the output I obtained by encoding with the encoder shown in FIG. 3 is written from the terminal 31 to the memory 5 via the PCM processor 4 of FIG.

Then, the data bit-compressed and written in the memory 5 is read through the PCM processor 4 as described above, and the read parallel data is serially converted word by word and output. , Serial data L is output from the PCM processor 4.

The serial data output L is recorded on the magnetic tape 9 by the magnetic head 8 via the modulator 6 and the recording amplifier 7.

Next, one embodiment of the decoder 12 according to the present invention is shown in FIG.
FIG. 5 shows a waveform chart of each part for explaining the operation.

During playback, the data recorded above is
The data is reproduced from the magnetic tape 9 by the magnetic head 8 and appropriately reproduced and equalized and demodulated by the reproduction equalizer 10 and the demodulator 11, and the demodulator 11 obtains a serial data output L ′ equivalent to the above data output L. To be

This serial data output L'is converted into parallel data word by word via the PCM processor 4 and then written to the memory 5 sequentially. Then, from the PCM processor 4, an output I ′ similar to the output I from the encoder 3 (see FIG. 5 (2)).
I) is obtained, and this output I'is the decoder 12 shown in FIG.
Is supplied to the terminal 32 of. The decoder 12 shown in FIG. 4 has the same structure as that of the conventional predictive predictive coding system.

That is, in FIG. 4, the PC input from the terminal 32
The output I'from the M processor 4 is supplied to the ROM 33 as an address signal of m (= 4) bits. In the ROM 33, the m (= 4) -bit data I ′ is converted into the n (= 8) -bit data C ″ (c ″ in FIG. 5 (2)) according to the characteristics shown in FIG. To be done.

As an example thereof, as shown in FIG. 6, when m (= 4) -bit data I is data corresponding to 6, data having a value of 77 and data corresponding to 4 are values of 31. The possessed data is output from the ROM 33 as a signal C ″ (c ″ in FIG. 5 (2)).

The signal C ″ converted into n (= 8) bits by the ROM 33 is added to the predicted value K (fifth value) from the delay circuit 35 by the adder 34.
K) in FIG. 2B is added. The predicted value K from the delay circuit 35 is a signal obtained by delaying the output signal A ′ from the adder 34 by the delay circuit 35 by a time τ equal to one sample (one pixel) interval.

Therefore, the adder 34 restores the data A '(a' in FIG. 5 (2)) corresponding to the original sample value A and outputs it to the terminal 36.

As described above, the present invention is characterized by detecting the reversal phenomenon at the time of reproduction at the time of recording and changing the level of the signal of m (= 4) bits to be recorded by one step and recording. The inversion phenomenon of the image signal does not occur during reproduction.

The above embodiment shows the case where the present invention is applied to a magnetic recording / reproducing apparatus such as a VTR, but the present invention is not limited to this, and an arbitrary information signal such as an audio signal other than an image signal is recorded / reproduced. It is applicable not only when transmitting as a digital signal to any transmission medium,
It does not deviate from the gist of the present invention.

Further, although the above-mentioned embodiment shows the case of the predictive predictive coding method, the present invention is not limited to this, and in general, N
It is obvious that the present invention can be applied to the following curve predictive coding system and further to other differential coding systems in which the difference between the predicted value and the reference value is bit-compressed and coded.

In addition, in the above embodiment, the adder 23 and the subtractor 24
Another bit number m (= the same polarity as the output data E of the bit number m (= 4) from the ROM 19 and an absolute value one step lower
Although the case where the data of 4) is obtained is shown, the present invention is not limited to this, and the magnitude relation when the data of the bit number n (= 8) is displayed in binary and the bit number m (= The number of bits m (=
Even when a ROM having a conversion characteristic such that the magnitude relation in the case of binary display in the data of 4) is different is used as ROM19, when supplied as an address signal of ROM20 or ROM33, m from ROM19 (= 4)
The bit number m (= 4) of data that outputs n (= 8) bit data one step higher than when the predetermined bit data is supplied is the bit number m (=
When supplied as the address signal of the ROM and ROM20 or ROM33 which is output when the predetermined data of 4) is supplied, it is one step lower than when the predetermined data of m (= 4) bits from the ROM19 is supplied. The data of bit number m (= 4) that outputs n (= 8) bit data is RO
It can be obtained by the ROM output when the predetermined number of bits m (= 4) of data from M19 is supplied, and does not deviate from the gist of the present invention.

Further, in the above embodiments, the means for detecting and preventing the inversion phenomenon of the image signal in the case of converting the n-bit data excluding the most significant bit of the differential data of the bit number n + 1 into the data of the bit number m is shown. However, the present invention is not limited to this, and it is obvious that the present invention can be applied to the case where the differential data of the bit number n + 1 is directly converted to the data of the bit number m.

〔The invention's effect〕

As described above, according to the present invention, the information signal can be transmitted without causing the inversion phenomenon of the information signal at the time of reproduction, that is, at the time of decoding, so that the image quality is deteriorated in the magnetic recording / reproducing apparatus such as a digital VTR. There is an effect that can be suppressed.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing an example of a conventional encoder, and FIG.
FIG. 4 is a block diagram showing an embodiment of an encoder according to the present invention, FIG. 4 is a block diagram showing an embodiment of a decoder according to the present invention, FIG. 5 is an encoder of FIG. 3 and FIG. Waveform diagrams of respective parts for explaining the operation of the decoder, and FIG. 6 is a characteristic diagram showing an embodiment of the code characteristics and decoding characteristics thereof. 3 …… Encoder, 12 …… Decoder, 16,24,51 …… Subtractor, 17,22,23,34,52 …… Adder, 27,28 …… Comparator, 29,30 …… Data Selector, 18, 35, 53 …… Delay circuit, 19, 20, 33, 54 …… ROM.

Claims (3)

[Claims] 1. An apparatus for sampling and quantizing an information signal to convert it into a digital signal for transmission or recording, and means for sequentially sampling the information signal, and quantizing the sampled sample value with a bit number n. Means, means for calculating a prediction value of a predetermined number of bits n corresponding to at least some of the samples of the number of bits n, and a difference between the sample value and the prediction value And the data of the bit number n excluding the most significant bit of the difference data of the bit number n + 1, which is the result of the calculation means,
A first converting means for converting the sampled value into data having a bit number m smaller than the bit number n and a converting means equivalent to that at the time of decoding are performed at the time of encoding, and as a result of the converting means, a quantum having a bit number of n is obtained. Means for detecting whether data inverted to a reverse polarity level is output by the data exceeding the range of the conversion level, and based on the result of the detecting means, the first converting means The encoding device is characterized in that the data of the number of bits m is switched to another data of the number of bits m which is not inverted and transmitted. 2. The detecting means includes a second converting means equivalent to a means for converting the data of the bit number m at the time of decoding into the data of the bit number n based on the data, and the second converting means. Means for adding 1 bit to the data of the bit number n from the converting means, the same code as the most significant bit of the difference data of the bit number n + 1 as the most significant bit, and data of the bit number n + 1 from the adding means, Means for adding data indicating the quantization level of the predicted value of the number of bits n expressed by the number of bits N + 1, and addition data of the number of bits n + 1 excluding the most significant bit of the addition data from the adding means , Means for comparing the level with data indicating the maximum quantization level of the bit number n expressed by the bit number n + 1, and the addition data of the bit number n + 1 and the data expressed by the bit number n + 1. The minimum unit for comparing the level of the data indicating the quantization level, city by being configured by the coding apparatus of Claim 1 wherein the appended claims, wherein the number of bits n have. 3. The data of another bit number m which is not inverted has the same polarity as the data of the bit number m from the first conversion means, and the absolute value is data of the bit number m which is at least one step lower. The encoding device according to claim 1, wherein the encoding device is configured as described above.