JPH073954B2 - Encoder - Google Patents

Description

The present invention relates to an apparatus for digitally transmitting or recording / reproducing an analog information signal by sampling / quantizing the analog information signal in the time axis direction, and particularly to an analog information signal at the time of decoding. The present invention relates to an encoder suitable for preventing the occurrence of a level inversion phenomenon.

[Conventional technology]

In a device for digitally transmitting an image signal, the number of quantization bits per one sampled value (hereinafter, referred to as a pixel) is normally required to be 7 to 8 bits in the case of linear quantization.
If the signal of the standard TV system is digitalized by linear quantization, the transmission route of the digital signal requires about 100 Mbps (megabit per second), and for the high-definition TV system proposed by some, Higher transmission rates are required.

In the digital VTR that magnetically records and reproduces such a digital image signal, since the transmission rate is extremely high as described above, the tape consumption is larger than that of the conventional analog recording VTR, and sufficient recording time can be obtained. In addition, the signal to be handled becomes extremely wide band, and the operation speed of the digital signal processing circuit also becomes a problem, which is technically difficult, which is a major obstacle to widespread use of the digital VTR for home use.

In order to improve such a problem, so-called high-efficiency coding has been studied in the past, and is described in detail, for example, in "Digital signal processing of images" by Takahiko Fukibe (Nikkan Kogyo Shimbun). As described in Chapter 9 of this document, 1
As a method of reducing the number of bits per pixel, there is known a so-called predictive coding (DPCM) method in which a current value is predicted from the already coded pixel value and an error from the current value is predicted.

Hereinafter, a conventional technique will be described with reference to the drawings.

First, before describing the conventional encoder, the configuration and operation of a digital VTR, which is one of the devices using the encoder, will be described.

FIG. 4 is a block diagram showing the structure of a general digital VTR.

In FIG. 4, 1 is an image signal input terminal, 2 is an A / D converter, 3 is an encoder, 4 is a PCM processor, 5 is a memory, and 6
Is a modulator, 7 is a recording amplifier, 8 is a magnetic head, 9 is a magnetic tape, 10 is a reproduction equalizer, 11 is a demodulator, 12 is a decoder, 13 is a D / A converter, and 14 is a reproduced image signal output terminal. is there.

A general digital VTR which is a kind of magnetic recording / reproducing device
In FIG. 4, first, as shown in FIG. 4, the image signal V input from the terminal 1 is converted by the A / D converter 2 into a digital signal A having a quantization bit number n bits. The n-bit digital signal A is bit-compressed by the encoder 3 as described later.

The output I of this encoder 3 (hereinafter abbreviated as data I)
Are sequentially written to the memory 5 via the PCM processor 4, and when writing to the memory 5, an address signal, an error correction code, etc. are added to each predetermined block of the data I as necessary. Then, through the memory 5, interleave (rearrangement of data for error correction)
And shuffling (sorting data to make corrections)
The data I read out from the memory 5 is further processed by the PCM processor 4 with error detection and correction codes, a sync signal for finding the beginning of a block, and a start / stop code used for clock reproduction. Therefore, it is added and output.

An output data string L from the PCM processor 4 is modulated by a modulator 6 into a code having a configuration suitable for magnetic recording, and its output is sequentially recorded on a magnetic tape 9 by a magnetic head 8 via a recording amplifier 7. To be done.

Next, on the reproducing side, the signal reproduced from the magnetic head 9 by the magnetic tape 9 is subjected to amplitude equalization, phase equalization, etc. by the reproduction equalizer 10 as required, and then is performed at the time of recording by the demodulator 11. The modulated signal is demodulated to the original code, and a signal L ′ equivalent to the data string L input to the modulator 6 during recording is output. The output data string L'from this demodulator 11 is PC
The M processor 4 detects a sync signal, finds a data block, detects and corrects a code error, or a memory 5
Deinterleaving and deshuffling are performed via.

The data read from the memory 5 and error-corrected by the PCM processor 4 are supplied to the decoder 12 as bit-compressed data I'which is equivalent to the output data I from the encoder 3 at the time of recording. The decoder 12 decodes the data I ', and outputs the expanded n-bit digital signal A'. This digital signal A'is D /
It is converted into an analog signal by the A converter 13, and the image signal V ′ is restored and output to the terminal 14. The above is the description of the operation of a general digital VTR.

In the past, the encoder and decoder shown in FIGS. 5 and 6 were used as the encoder 3 and decoder 4 shown in FIG.

FIG. 5 is a block diagram showing a conventional example of a DPCM encoder using a priori prediction, and FIG. 6 is a block diagram showing a conventional example of the same decoder.

In FIG. 5, 50 is an input terminal, 51 is a subtractor, 52 is a compression ROM, 53 is a decompression ROM, 64 is an adder, 55 is a delay circuit, and 56
Is an output terminal.

Further, in FIG. 6, 40 is an input terminal and 41 is an extension RO.
M and 42 are adders, 43 is a delay circuit, and 44 is an output terminal.

FIG. 7 is a graph showing the conversion characteristics of the compression ROM and the expansion ROM shown in FIGS. 5 and 6, and FIG. 7A is an explanatory diagram for explaining the way of viewing the conversion characteristics of FIG. is there.

The horizontal and vertical axes in FIG. 7 represent the input a of the compression ROM when the compression ROM and the expansion ROM shown in FIGS. 5 and 6 are connected as shown in FIG. 7A. The level and the level of the output c of the decompression ROM are shown.
The numbers from -8 to +7 near the diagonal line (dashed line) in the graph of FIG. 7 are the compression RO shown in FIG. 7A.
The level of the output b of M or the input b of the decompression ROM is shown. Therefore, it can be said that FIG. 7 shows the input / output characteristics of the compression ROM and the expansion ROM at the same time.

First, the operation of the encoder 3 shown in FIG. 5 will be described.

In FIG. 5, the input terminal 50 of the encoder 3 is supplied with the digital image signal A having the quantization bit number n bits which is A / D converted by the A / D converter 2 as described above. Here, the number of quantization bits n is a large value so that the quantization error can be ignored, and in this example, n = 7 is determined.

This 7-bit / pixel digital signal A is subtracted by a subtracter 51 from the signal (7-bit signal) one pixel before as a predicted value obtained from the delay circuit 55, and an 8-bit difference signal C is obtained. . Here, the delay time τ of the delay circuit 55 is the pixel interval. 8-bit difference signal C obtained by the subtracter 51
Is m by the compression ROM 52 having the conversion characteristic shown in FIG.
= 4 bit compressed differential signal E is converted. Then, the 4-bit / pixel compression difference signal E is output as the above-mentioned data I through the output terminal 56.

In addition, the 4-bit compression difference signal E from the compression ROM 52
By the decompression ROM 53 having the conversion characteristics shown in FIG.
It is converted into a bit expansion signal C'and input to one input of the adder 54. Here, the signal from the delay circuit 55 is input to the other input of the adder 54, and the adder 54 adds this signal and the expanded signal C'to the delay circuit.
You are typing in 55.

The above is the description of the operation of the encoder 3 shown in FIG.

Next, the operation of the decoder 12 shown in FIG. 6 will be described.

In FIG. 6, an input terminal 40 of the decoder 12 is supplied with the equivalent 4-bit signal I'of the compressed differential signal E, and then the ROM 41 for expansion having the conversion characteristic shown in FIG.
It is converted into a bit difference signal C ″. This difference signal C ″
Is added by the adder 42 to the signal one pixel before from the delay circuit 43 having a delay time τ equal to the pixel interval, and output as a 7-bit digital image signal A ′ equivalent to the digital signal A. . This digital image signal A '
Is output via the output terminal 44, and then D / A converted by the D / A converter 13 as described above to become an analog image signal.

The above is the description of the operation of the decoder 12 shown in FIG.

As described above, the number of bits per pixel can be reduced to about 4 bits by using the DPCM encoder, and the transmission rate is 4/7 compared to the linear quantization method described above.
Can be reduced to

[Problems to be solved by the invention]

The input signal in the conventional encoder 3 shown in FIG. 5 and the output signal in the conventional decoder 12 shown in FIG. The range of quantization levels is -64 to +63. The correspondence between the decimal representation and the binary representation in 7 bits is as shown in FIG.

Now, the input digital signal A of n = 7 bits to the encoder 3 shown in FIG. 5 is, for example, -31 → 62 → 25 → 10 → 35 ...
, The 8-bit difference signal C from the subtractor 51 becomes −31 → 93 → 74 → −18 → 24 ...
The compressed differential signal E from M52 is -5 → 7 → 6 → -4 → 4
Is output from the output terminal 56 as m = 4 bit data respectively corresponding to. On the other hand, the decoder 12 shown in FIG.
Is inputted through the input terminal 40, and the 8-bit difference signal C ″ output from the decompression ROM 41 is −31 → 110 → 77 → −17 → 3.
1 ……, and the output digital signal A ′ from the adder 42
Becomes −31 → 79 (−49) → 28 → 11 → 42 .... here,
Since the data = 79 exceeds the quantization level range (−64 to +63) of the bit number n = 7 described above, the level is inverted to the opposite polarity and the data = −49 is output.

That is, since the number of quantization bits is 7 bits as described above,
The output of the adder 42 is only 7 bits (the same is true of the adder 54). Even if the addition result is 79, that is, the 8-bit data of 01001111, the most significant bit is obtained. Since 0 is deleted and output as 7-bit data, 1001111, that is, -49 is output.

As described above, when the conventional encoder is used, depending on the level of the input signal and its level change, the data of the level exceeding the quantization level range of the bit number n at the time of decoding by the decoder. However, there is a problem that the level inversion phenomenon of the information signal occurs.

When such a level inversion phenomenon occurs in the image information signal, the image quality deteriorates, for example, a white spot suddenly appears in a black-painted portion on the screen.

The object of the present invention is to solve the above-mentioned problems of the prior art,
An object of the present invention is to provide an encoder capable of encoding without causing a level inversion phenomenon of an information signal at the time of decoding.

[Means for solving problems]

In order to achieve the above-mentioned object, in the present invention, a calculating means for calculating a predetermined prediction value of the bit number n corresponding to at least a part of the sample values inputted, and the prediction means. First computing means for obtaining a first difference value by obtaining a difference between the value and the corresponding sample value,
First compression conversion means for compressing and converting the first difference value to obtain a first value of a bit number m smaller than the bit number n; and for compressing and converting the first difference value to a bit number m. Second
Second compression and conversion means for obtaining the value of, and the third value and the fourth value of the bit number equivalent to the first difference value by expanding and converting the first value and the second value, respectively. And a decompression conversion means for respectively obtaining a value and the second compression conversion means,
The second value is compressed and converted so as to obtain a value such that the absolute value of the fourth value after the expansion conversion by the expansion conversion means is smaller than the absolute value of the third value. Addition (or subtraction) is performed between the third value and the predicted value obtained by the expansion conversion means and between the fourth value and the predicted value, and the fifth value of the bit number n is obtained. Second computing means for obtaining a value and a sixth value, respectively, and a difference between the fifth value and the sample value corresponding to the predicted value,
And a third calculating means for obtaining a difference between the sixth value and the sample value to obtain a second difference value and a third difference value, an absolute value of the second difference value, and Comparing means for comparing the absolute value of the third difference value, and as a result of the comparison by the comparing means, the absolute value of the second difference value is smaller than the absolute value of the third difference value. When the absolute value of the second difference value is larger than the absolute value of the third difference value, the first value obtained by the first compression conversion means is output as an encoded value. Is to output the second value obtained by the second compression conversion means instead of the first value as an encoded value.

[Action]

When the first value and the second value are respectively subjected to the decoding process, the error between the decoded output and the sample value is usually smaller when the first value is decoded.
However, if the level inversion phenomenon occurs, the first
When the decoding is carried out by the value of, the error of the decoded output with respect to the sample value becomes large, but the error when the decoding is carried out by the second value of one is not so large.

Therefore, if the absolute values of the errors generated by both decodings are compared and the smaller of the comparison results of the first value and the second value is output, the decoding output will be a bit at the time of decoding. The level does not exceed the quantization level range of several n, and the level inversion phenomenon can be prevented.

In the present invention, the second difference value corresponds to an error generated by decoding the first value, and the third difference value corresponds to an error generated by decoding the second value.

〔Example〕

 Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention, and FIGS. 2 (1) and 2 (2) are explanatory views for explaining the operation of FIG. 1, respectively. Note that in FIG. 2, the horizontal axis represents time.

Hereinafter, the encoder in this embodiment will be described as being used as the encoder 3 of the digital VTR shown in FIG.

In FIG. 1, reference numeral 15 is an input terminal for an n-bit digital signal A output from the A / D converter 2 in FIG. As shown in FIG. 2 (1), in the A / D converter 2, the image signal V input from the terminal 1 is sequentially sampled every period τ, and an n-bit digital signal is obtained according to each sample value.
Converted to Ai. Here, the number n of quantization bits is set to n = 7 in this embodiment as a value at which a quantization error can be ignored in handling an image signal.

7-bit digital signal A input from input terminal 15
In FIG. 2 (2) a, the predicted value B (FIG. 2 (2) b) from the delay circuit 18 is subtracted by the subtractor 16.

Based on the conversion characteristics shown in FIG. 7, the predicted value B from the delay circuit 18 is the output of the decompression ROM 32, which is the transmission signal I (4 bits) decompressed to 8 bits, and the one pixel before the output from the delay circuit 18. The output signal B and the output signal B are added by the adder 17, and the 7-bit output signal D (FIG. 2 (2) d) from the adder 17 is added to the delay circuit.
It is a signal delayed by a time τ equal to one pixel interval by 18 and is a signal corresponding to the decoded value one sample before the input digital signal A. Therefore, the output signal C ((2) c in FIG. 2) of the subtractor 16 becomes a difference signal between the digital signal A and the decoded value one sample before. Since the output difference signal C is the difference between 7-bit signals, the number of bits is 8 bits. The 8-bit difference signal C is converted into 4-bit compressed signals E and E'by the compression ROM 19 and the compression ROM 24, respectively.

In the compression ROM 19, the 8-bit output signal C of the subtractor 16 is converted into the 4-bit signal E (second signal) according to the conversion characteristic shown in FIG.
It is converted into FIG. As an example, when the difference signal C is +77, a 4-bit signal E corresponding to 6 is output from the compression ROM 19, as shown in FIG. Four
The bit-converted output signal E of the compression ROM 19 is supplied to one input of the data selector 30 and also input to the decompression ROM 20.

On the other hand, the compression ROM 24 inputs the 8-bit signal C of the subtractor 16 which is the input thereof, into a 4-bit signal E '(the absolute value of which is one step smaller than the conversion characteristic shown in FIG. 2) It is converted into e '). In an example similar to the above, when the output C of the subtractor 16 is +77, the compression ROM 19
4 bit signal E'corresponding to 5 which is one step smaller than the output E of Eq.
A 4-bit signal E'corresponding to -7 with a small step is output. The output signal of the compression ROM 24 converted into 4 bits is supplied to the other input of the data selector 30 and also input to the expansion ROM 25.

By the way, generally, when the level inversion phenomenon as described above occurs, the difference signal C is the compression ROM1.
Decompression ROM of the decoder shown in FIG. 6 after being compressed by 9
It may occur at least when the differential signal C ″ obtained by the expansion becomes larger in absolute value than the original differential signal C when expanded at 41.

Therefore, in this embodiment, the compression ROM 24 is used to compress and convert the differential signal C into the signal E'one step lower as described above, so that when the expansion ROM 41 of the decoder expands,
The difference signal C ″ obtained by the expansion is the original difference signal C.
Its absolute value is not larger than that.

That is, the signal E'obtained from the compression ROM 24 is the compression ROM
The decoded output (digital signal A ′ shown in FIG. 6) and the original value (that is,
The error with the digital signal A) may be large, but at least it does not cause the level inversion phenomenon.

Next, the decompression ROM 20 is equivalent to the decompression ROM (decompression ROM 41 in FIG. 6) used in the decoder 12, and is for compression.
A 4-bit signal E from the ROM 19 is converted into an 8-bit expanded signal C '(FIG. 2 (2) c') according to the conversion characteristic of FIG. As in the above example, when the 4-bit signal E is 6, the value corresponding to +77 is shown in FIG. 7, and when it is 4, the value corresponding to +31 is the 8-bit signal C. Is output as'. Thus, the output signal C'of the ROM 20 is a signal obtained by compressing the 8-bit difference signal C output from the subtractor 16 into 4 bits and expanding it to 8 bits again.

The decompression ROM 25 is exactly the same as the decompression ROM 20,
The 4-bit signal E'from the compression ROM 24 is expanded by 8-bit according to the conversion characteristic of FIG. 7 to obtain a signal C (FIG. 2 (2)).
c). In the same example as above, when the 4-bit signal E'is 5, the value corresponding to +52 as shown in FIG. 7 and when it is -7, the value corresponding to -77 is 8-bit signal. Is output as.

The output signal C'of the decompression ROM 20 and the output signal C of the decompression ROM 25, which have been decompressed to 8 bits, are used by the adder 21 and the adder 26, respectively. And the predicted value B from each are added to obtain an output of 7 bits each. Here, as is clear from comparison with the configuration of the decoder shown in FIG.
The output of 21 is the same as the decoded output obtained when the signal E from the compression ROM 19 is input to the decoder shown in FIG. 6, and the output of the adder 26 is from the compression ROM 24. The signal E'is also the same as the decoded output obtained when it is input to the decoder.

Therefore, hereinafter, the output from the adder 21 is the temporary decoded signal F ((2) f in FIG. 2), and the output from the adder 26 is the temporary decoded signal F '.
((2) f 'in FIG. 2).

Therefore, the errors between these provisional decoded signals F and F'and the input digital signal A will be examined and examined. Normally, the temporary decoded signal F should have a smaller error from the digital signal A, but when the level inversion phenomenon as described above occurs, the polarity is inverted at the time of decoding. The error between the decoded output, that is, the temporary decoded signal F and the digital signal A becomes very large. However, since the level inversion phenomenon does not occur in the temporary decoded signal F ′ as described above, the polarity inversion does not occur and the error with the digital signal A is larger than that in the temporary decoded signal F at the time of level inversion. Will never grow larger.

Therefore, the level inversion phenomenon can be detected by comparing the errors between the temporary decoded signals F and F ′ and the input digital signal A, respectively.

Then, these provisional decoded signals F and F'are subtracted from the input digital signal A by the subtracter 22 and the subtractor 27, respectively, and the error signal G ((2) g in FIG. 2) and the error signal G'down one step. ((2) g 'in FIG. 2) is obtained. Then, the absolute values of these error signals G and G'are obtained by absolute value converters 23 and 28, respectively, and are input to a comparator 29.

The output of the comparator 29 is input to the select terminal of the data selector 30, and when the absolute value of the error signal G is larger than the absolute value of the error signal G'one step lower, the data selector 30
Is switched to the compressed signal E'side of 4 bits whose absolute value output from the compression ROM 24 is one step smaller, and conversely, when the absolute value of the error signal G'one step below is larger, the compression ROM 19 To the 4-bit compressed signal E side. The output from the data selector 30 is output as the transmission signal I via the output terminal 30.

For example, the input digital signal A of 7 bits is -31 → 62 →
If it changes from 25 → 10 → 35 …… 8 of subtractor 16 output
The bit difference signal C changes in the order of −31 → 93 → −21 → −19 → 23 .... Therefore, the 4-bit compression difference signal E of the compression ROM 19 becomes -5 → 7 → -4 → -4 → 4 ...
The 4-bit output signal E'of the compression ROM 24 is -4 → 6 → -3
→ -3 → 3 ... The output C'of the decompression ROM 20 is -31 → 110 → -17 → -17 → 31 ..
The output C of the OM25 is -17 → 77 → -8 → -8 → 17 ... Further, a 7-bit tentative decoded signal obtained by adding these signals and the predicted value B output from the delay circuit 18, that is, an adder The output F of 21 is −31 → −48 → 29 → 12 → 43 ... And the output F ′ of the adder 26 changes as -17 → 46 → 38 → 21 → 29.
Therefore, the error value between these provisional decoded values F and F'and the input digital signal A, that is, the output G of the subtractor 22 is 0 → 110.
→ -4 → -2 → -8 ..., the output G'of the subtractor 27 is -14 →
16 → -13 → -11 → 6 ... And these subtractors
With the output of the comparator 29 that compares the absolute values of the output G of 22 and the output G ′ of the subtractor 27, the data selector 30
E-> E '->E->E->E' ...
In FIG. 2 (2) i, a 4-bit signal of -5 → 6 → -4 → -4 → 3 ... Is selected and output from the output terminal 31.

As described above, in this embodiment, as in the case of the second data (A = 62, C = 93, E = 7) in the above example, the value at the time of temporary decoding (F =
When -48) causes level inversion, a 4-bit compressed signal is output by switching from E to E '(E' = 6).
It is possible to prevent the level inversion at the time of decoding. Even if the level inversion does not occur as in the case of the fifth data (A = 35, C = 23, E = 4) in the above example, decoding is performed even when the difference value is on the boundary of the quantization step. Switch to the E'side with less error.

The above is the description of the operation of the encoder shown in FIG.

Thus, the output I obtained by encoding by the encoder shown in FIG. 1 is written as data compressed into 4 bits / pixel in the memory 5 through the PCM processor 4 of FIG. 4 as described above. . Thereafter, the data written in the memory 5 is read out via the PCM processor 4 and recorded on the magnetic tape 9 by the magnetic head 8 via the modulator 6 and the recording amplifier 7.

At the time of reproduction, a signal is reproduced from the magnetic tape 9 by the magnetic head 8 and is reproduced and equalized and demodulated by the reproduction equalizer 10 and the demodulator 11 as appropriate, and then the above-mentioned encoder is transmitted through the PCM processor 4 and the memory 5. The output I from 3 is supplied to the decoder 12 as a signal I '. The decoder 12 used here is the same as the decoder in the conventional predictive predictive coding system shown in FIG.

FIG. 2C is an explanatory diagram for explaining the operation of the decoder shown in FIG.

The signal I '((3) i' in FIG. 2) input from the PCM processor 4 inputted through the input terminal 40 is 4-bit compressed data, and the decompression ROM 41 produces 8 bits according to the conversion characteristic shown in FIG. Decompression data C ″ (Fig. 2 (3) c ″)
Is converted to. For example, as shown in FIG. 7, when the 4-bit signal I'is the data corresponding to 6, the 8-bit data corresponding to the value of 31 is the decompression ROM 41 as the signal C ".
Will be output. The predicted value K (k in FIG. 2 (3)) from the delay circuit 43 is added by the adder 42 to the signal C ″ expanded by the expansion ROM 41 to 8 bits.
The predicted value K of 43 is obtained by delaying the output signal A ′ of the adder 42 with the delay circuit 43.
Is a signal delayed by a time τ equal to one pixel interval. Therefore, the output of the adder 42 becomes the decoded data A '(a' in FIG. 2 (3) a) corresponding to the original sample value A, which is the sum of the prediction value K and the difference value C ", and is 7 bits / pixel. It is output to the terminal 44 as a signal.

As described above, in the present embodiment, the temporary compression is performed by the compression difference signal and the signal having a small one step absolute value at the time of recording, and the compression difference is determined by the magnitude of the error between both the temporary decoding values and the input signal. When a level inversion phenomenon that occurs when a signal is decoded is detected and level inversion occurs, a signal whose absolute value is one step smaller is transmitted instead of the compression differential signal. This can prevent the level inversion of the image signal from occurring during reproduction.

Next, FIG. 3 is a block diagram showing another embodiment of the present invention.

In the embodiment of FIG. 1, a 4-bit compressed differential signal E
The compression ROM 19 and the compression ROM 24 for obtaining the signal E'having a small one-step absolute value are used in parallel. However, as in the embodiment shown in FIG. 3, the signal E'having a small one-step absolute value is used. It is also possible to use the ROM 24 'for obtaining the above in series with the compression ROM 19 and input the 4-bit compression difference signal E to output the 4-bit signal E'having an absolute value smaller by 1 step. In this case, the ROM capacity can be reduced.

Further, in the embodiment of FIGS. 1 and 3, the decompression ROM 2
0 and the decompression ROM 25, the adder 21 and the adder 26, the subtractor 22 and the subtractor 27, and the absolute value converter 23 and the absolute value converter 28 are the same circuit. It is also possible to use by dividing.

Although the present invention is applied to the magnetic recording / reproducing apparatus such as a digital VTR in the above embodiment, the present invention is not limited to this, and any information signal other than the image signal such as an audio signal is recorded. It can also be applied to the case of reproduction or transmission via an arbitrary transmission medium. Further, although the above-mentioned embodiments show the case of the previous value predictive coding method, the present invention is not limited to this, and in general, the Nth order curve predictive coding method and further the difference between the predictive value or the reference value is bit-checked. It is obvious that the present invention can be applied to other differential encoding methods that compress and encode.

Also, depending on the characteristics of the transmission path, so-called weighted mapping may be applied to the 4-bit compressed differential data which is the transmission signal. In the above-mentioned example, the 4-bit compressed differential data is 7,6,5,4,3,2, from the larger of the 8-bit decompressed data.
1,0, −1, −2, −3, −4, −5, −6, −7, −8, but in the weighted mapping, from the larger 8-bit decompression data, for example, 0 , 1,2,4,7,3,6,5, −6, −7, −4, −8,
−5, −3, −2, −1 (when the value is 5, the value after decompression is 0). Therefore, in the above-described example, 5 is used as a value 1 step lower than the compression difference value 6 of 4 bits, whereas in this weighted mapping, 1 step lower than the compression difference value 1 of 4 bits. A value of 2 will be used. The present invention can also be applied to the case of weighted mapping as described above.

Further, in the above-described embodiment, the ROM is used to obtain the value one step lower than the compressed difference value of 4 bits, but when the weighted mapping as described above is not performed, the polarity of the difference value is determined. -1 or +1 depending on the subtractor or adder
The value of may be obtained.

〔The invention's effect〕

As described above, according to the present invention, information can be transmitted without causing the level inversion phenomenon of the information signal at the time of DPCM decoding, so that it is effective in preventing image quality deterioration in a magnetic recording / reproducing apparatus such as a digital VTR. There is.

Furthermore, even if level inversion does not occur, for the difference value near the boundary of each quantization step, the compressed data with the smaller quantization error after decoding is selected, so the quantization error of the overall Has the effect of reducing.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is an explanatory diagram for explaining the operation of FIGS. 1 and 6, and FIG.
FIG. 4 is a block diagram showing another embodiment of the present invention, FIG. 4 is a block diagram showing the configuration of a general digital VTR to which an encoder is applied, and FIG. 5 is a block diagram showing a conventional encoder.
FIG. 6 is a block diagram showing a general decoder, FIG. 7 is a graph showing conversion characteristics of compression ROM and decompression ROM, and FIG. 7A is an explanation for explaining the view of conversion characteristics of FIG. FIG. 8 and FIG. 8 are explanatory views for explaining the correspondence between the decimal representation and the binary representation in a 7-bit digital value. Code description 3 …… Encoder, 12 …… Decoder, 16,22,27,51 …… Subtractor, 17,21,26,42,54 …… Adder, 29 …… Comparator, 30 ……
Data selector, 18,43,55 …… Delay circuit, 19,24,52 ……
Compression ROM, 20,25,41,53 …… Decompression ROM, 24 ′ …… ROM

Claims (2)

[Claims] 1. A sample value of a bit number n obtained by sampling and quantizing an analog information signal is input, and the bit number n is input.
In an encoder that encodes and outputs a value of a bit number m that is smaller than the above, a calculation for calculating a predetermined prediction value of the bit number n corresponding to at least a part of the sample values of the input sample values Means, first calculation means for obtaining a difference between the predicted value and the corresponding sample value and obtaining a first difference value, and first compression means for converting the first difference value into a first bit number m. , A second compression conversion means for obtaining a second value of the bit number m by performing a compression conversion on the first difference value, the first value and the second value. And a third bit number equal to the first difference value.
And decompression conversion means for respectively obtaining the value and the fourth value, and the second compression conversion means, as the second value,
The compression conversion is performed so as to obtain a value such that the absolute value of the fourth value after the expansion conversion by the expansion conversion unit becomes smaller than the absolute value of the third value, and the compression conversion is performed by the expansion conversion unit. Addition (or subtraction) is performed between the third value and the predicted value and between the fourth value and the predicted value to obtain the fifth value and the sixth value of the bit number n. Second computing means for obtaining each and the fifth computing means
And a sample value corresponding to the predicted value, and a difference between the sixth value and the sample value, respectively, to obtain a second difference value and a third difference value, respectively. And a comparing means for comparing the absolute value of the second difference value with the absolute value of the third difference value, and the result of the comparison by the comparing means is the second difference value. Is smaller than the absolute value of the third difference value, the first value obtained by the first compression conversion means is output as an encoded value, and the second difference value of When the absolute value is larger than the absolute value of the third difference value, instead of the first value, the second value obtained by the second compression conversion means is output as an encoded value. An encoder characterized in that 2. The encoder according to claim 1, wherein the second compression conversion means uses the first value obtained in the first compression conversion means as the second value. An encoder characterized in that compression conversion is performed so as to obtain an m-bit value having the same polarity and an absolute value lower by at least one step.