JPH0553325B2 - - Google Patents

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a method of sampling and quantizing an information signal to be transmitted in the time axis direction, reducing the average number of bits per sample value, and encoding the signal. In particular, the present invention relates to a code conversion method suitable for suppressing DC components and reduced components of codes with a reduced number of bits.

[Background of the invention]

When converting an image signal into a digital signal and transmitting it, one sample value (hereinafter referred to as a pixel)
The number of quantization bits per unit is usually 7 to 8 bits in the case of linear quantization. The transmission rate when linearly quantizing an image signal is approximately 100 Mbit/sec in the case of standard television system.
Some high-definition television systems that have been proposed require a transmission rate that is more than twice that of the standard television system.

A device that magnetically records and reproduces this image signal as a digital signal (hereinafter referred to as a digital VTR)
However, as mentioned above, the transmission rate is extremely high, making it impossible to obtain sufficient recording time, and the high-speed operation of the digital signal processing circuit is also required, which is technically difficult. For this reason, digital VTRs have not yet become widely used for home use.

In order to improve these problems, so-called high-efficiency coding has been studied for some time, and the predictive coding method (DPCM) is well known. The predictive coding method is described in detail in "Digital Signal Processing of Images" by Takahiko Fukinuki, published by Nikkan Kogyo Shimbun, etc.

According to this predictive encoding method, it is possible to reduce the number of bits per pixel to about 4 to 5 bits, and it is possible to reduce the number of bits to about 1/2 compared to the linear quantization method described above. .

However, as mentioned in the above-mentioned literature, this predictive coding method has problems such as the accumulation of quantization noise caused by predictive coding, and the so-called so-called problem that the effects of code errors that occur in the transmission system propagate one after another. There are fundamental problems such as error propagation. These problems significantly degrade image quality, making it difficult to put this predictive coding method into practical use, especially in devices and devices that require high image quality.

Furthermore, methods have been conventionally studied for suppressing direct current components and low-frequency components of transmission signals by modulating digital signals to reduce transmission error rates. Regarding the modulation method, see Yonosuke Ito and Kazutoshi Nishimura, “Modulation and demodulation method for digital magnetic recording,” Nikkei Electronics pp. 126-164 (December 11, 1978).
(Japanese), etc.

However, for example, the digital FM modulation method has the characteristic that it does not have a DC component, but its transmission requires twice the baseband band, and when converted to the transmission band, the recording time is halved. Both require a wide transmission band depending on the degree of redundancy, making long-term recording difficult.

As described above, it has been difficult to increase the density of recording and transmission in terms of both high-efficiency encoding and modulation methods.

[Purpose of the invention]

The purpose of the present invention is to minimize the signal deterioration associated with encoding and reduce the average number of bits per sample value, as well as to suppress the DC component and low-frequency component of the code, thereby reducing code errors. An object of the present invention is to provide a code conversion method and a device thereof that can increase the amount of information that can be transmitted.

[Summary of the invention]

In order to achieve the above object, the present invention provides at least one reference sample value among N sample values (N is an integer of 2 or more) of an information signal to be transmitted, so that its quantization error can be ignored. The remaining sample values are encoded with a quantization bit number m (n>m) that is smaller than the above value n based on the difference related to the reference sample value. This prevents accumulation of quantization noise based on the differential encoding, prevents error propagation due to code errors over a long period of time, and reduces the average number of bits per sample value.

Furthermore, the fact that the difference amount is small due to the correlation of the information signals is utilized. That is, the number of quantization bits m
Among the codewords, codewords with a small absolute value of CDS (difference between the number of occurrences of "1" and "0" from the beginning to the end of one codeword) are coded so as to correspond to the level of the small difference amount. By converting the DC component,
and performs encoding with few low frequency components. In addition, for the reference sample value, code conversion is performed in descending order of the level of the reference sample value in order of increasing CDS of the n-bit code, and by alternately inverting the sign every n bits, the DC component is , suppresses low frequency components.

By suppressing the DC component and the low frequency component, the transmission code error rate can be reduced and the transmission effect can be enhanced.

[Embodiments of the invention]

Examples of the present invention will be described below. FIG. 1 is a block diagram showing an embodiment of the present invention applied to a magnetic recording/reproducing device such as a VTR, FIG. 2 is a diagram showing an embodiment of an encoder 20 according to the present invention, and FIG.
FIG. 4 is a waveform diagram for explaining its operation, FIG. 4 is a diagram showing an example of its code characteristics, and FIGS. 5 and 6 are diagrams showing an example of its code conversion characteristics.

In FIG. 1, 1 is an input terminal for an image signal V to be recorded, 2 is an output terminal for a reproduced image signal V', 3 is a magnetic head, 4 is a magnetic tape, 10 is an A/D converter, and 20 is an output terminal for a reproduced image signal V'. encoder, 30 is a PCM processor, 40 is a memory, 60 is a recording amplifier, 70
is a reproduction equalizer, 90 is a decoder, and 100 is a D/A converter.

A video signal V input from a terminal 1 is converted by an A/D converter 10 into a digital signal a quantized with n bits. This n-bit digital signal a is processed by the encoder 20 according to the present invention.
As described later, the data is bit-compressed and code-converted as appropriate. The output f of the encoder 20 (hereinafter referred to as data f) is sequentially written into the memory 40 via the PCM processor 30. And memory 4
When writing to 0, an address code indicating the address and a so-called parity code for code correction are added to each block of data f consisting of a predetermined number of bits, and are written into the memory 40.

After the writing to the memory 40 is completed, the data f, address code, and parity code that are subsequently read are as follows.
Parallel data is converted into serial data by the PCM processor 30, and synchronization codes are added to locate the beginning of blocks, and if necessary, error detection codes are added to detect code errors, or as appropriate before and after these data strings. Start/stop signs etc. are added and output.

The output data string g from the PCM processor 30 is sequentially recorded on the magnetic tape 4 by the magnetic head 3 via the recording amplifier 40.

Next, in the reproduction system, the signal reproduced from the magnetic tape 4 by the magnetic head 3 is sent to a reproduction equalizer 70.
A signal similar to the recorded data string g, which is appropriately reproduced and equalized by
It is output as g′. This data string g' is subjected to data cueing based on the synchronization code for each block and code error detection based on the error detection code in the PCM processor 30, and then converted from serial data to parallel data. then memory 40
are written sequentially.

The data written in the memory 40 is sequentially code-corrected by the PCM processor 30 based on the parity code, and then redundant codes are sequentially removed, resulting in data a' similar to the output data f from the encoder 20. is output and supplied to the decoder 90.

The decoder 90 decodes and outputs an n-bit digital signal f', which is converted into an analog signal by the D/A converter 100 to restore the original image signal V'. Output to terminal 2.

Next, the operation of the encoder 20 according to the present invention will be explained using an embodiment shown in FIG. 2 and a waveform diagram in FIG. 3.

In FIG. 2, 201 is the A/D converter 1
This is an input terminal for an n-bit digital signal a output from 0. As shown in FIG. 3, A/D
The converter 10 sequentially samples the image signal V input from the terminal 1 at every sampling period τ, and converts it successively into an n-bit digital signal Ai (i is an integer) according to the level of each sample value and outputs it. .

Here, the number n of quantization bits is such a large value that the quantization error can be ignored, and in this embodiment, which deals with image signals, n=8, for example.

In the present invention, at least one reference sample value out of N sample values (N is an integer of 2 or more) is encoded with a sufficient number of bits n so that its quantization error can be ignored, and the remaining sample values are The sample value is encoded with the number of bits m smaller than the value n based on the difference related to the reference sample value, thereby reducing the average number of bits per sample value.

2 and 3 show an example in which N=3. That is, as shown in 1 in Figure 3, among the three sample values represented by (A ₃ i-1, A ₃ i, A ₃ i+1), the sample value indicated by a circle
A ₃ i is encoded with n bits as a reference sample value.
Hereinafter, this reference data will be expressed by the same symbol A ₃ i. The remaining two sample values A ₃ i− are indicated by cross marks.
1, A ₃ i+1, the above reference sample value A ₃ i
Two difference data B ₃ i-1 and B ₃ i+1 given by the following equation according to the difference between

B ₃ i-1=A ₃ i-A ₃ i-1 B ₃ i+1=A ₃ i-A ₃ i+1 (1) As an example, if n=8 and m=4, the reference data is A ₃ i is 8 bits, differential data B ₃ i-1,
Both B ₃ i+1 are encoded with 4 bits, so the average number of bits per sample value is 16/3 = 5.33 bits, which is 2/3 compared to the conventional method in which all sample values are encoded with 8 bits. It becomes possible to compress bits into

Bit compression based on the above principle is performed as follows. In FIG. 2, an n-bit digital signal a (a in FIG. 3 2) inputted from a terminal 201 is supplied to a reference data sampler 230, while being passed through a delay device 210 with a sampling period τ
is delayed by a time corresponding to
(b) is input to one side of the subtraction circuit 240.

The reference data extractor 230 extracts the reference sample value (A ₃ i) from the signal a, holds the reference sample value for a period of 3τ, and outputs it.
The output c (c in FIG. 3) from the reference data extractor 230 is input to the other side of the subtracter 240 and also to the ROM 251.

Each of the above outputs a, b, and c is an n-bit signal. A subtracter 240 performs a difference calculation between the outputs c and b, and an n-bit output d (d in FIG. 3) corresponding to the difference between the two is obtained. Specifically, three sample values (A ₃ i−1, A ₃ i, A ₃ i+
1), the two difference data shown in equation (1) above
B ₃ i−1 and B ₃ i+1 are output d from the subtracter 240.
are output sequentially as . This output d is supplied as an address signal for the read-only memory ROM 250. The ROM 250 has a function of converting the n-bit output d from the subtracter 240 into m (<n) bits. Then, the DC component and low frequency component of the code after conversion in the ROM 250 are suppressed.
Code conversion data is written in the ROM 250.

FIG. 4 shows an example of conversion characteristics in the ROM 250 in the case of n=8 and m=4.

The ROM 250 contains a ₀ , a ₁ ,..., shown in FIG.
A total _{of 16} ( _{i.e. 4}
(corresponding to bits) are written, and these data are addressed and read according to the n (=8) bit output d from the subtracter 240.
More specifically, if the value of the output d from the subtracter 240 is positive or 0 (i.e., A ₃ i≧A ₃ i−1 or A ₃ i
≧A ₃ i+1), the data corresponding to the symbol a is read, and the value of d is negative (i.e., A ₃ i<A ₃ i
−1 or A ₃ i<A ₃ i+1), the symbol b
The data corresponding to is read. As an example, the value of d (i.e., the difference data
When the value of Bi) is 54, the data Ci corresponding to a ₅ is
Output from ROM250.

Thus, in the ROM 250, the n (=8) bit output d from the subtracter 240 is converted into m (=4) bits. That is, the n-bit data in equation (1) above
B ₃ i-1 is the code of m bits C ₃ i-1 and n
Bit data B ₃ i+1 is m-bit code C ₃ i
+1 respectively, and the output e (Fig. 3 2
e) is supplied to the terminal _Y1 of the data selector 260.

a ₀ , a ₁ , ..., a ₇ output from the ROM250
An example of codes assigned to each level of b ₀ , b ₁ , . . . , b ₇ is shown in FIG.

There are a total of 2 ^m (=16) m (= 4) bit codes, but the CDS of the m-bit code words is calculated, and the codes are arranged in order from the one with the smallest absolute value of the difference data to the one with the smallest absolute value of CDS. Assign. Specifically regarding the case where m=4, there are six code words with CDS=0, and they are assigned to a ₀ , a ₁ , a ₂ , b ₀ , b ₁ , and b ₂ . Next, there are 4 code words with CDS=+2, which are a ₃ , a ₄ , a ₅ , a ₆ , and 4 code words with CDS=-2, b ₃ , b ₄ , b ₅ , b ₆ , a code word with CDS=+4 is assigned to a ₇ , and a code word with CDS=-4 is assigned to b ₇ . An example of the code obtained in this way is shown in FIG. Note that when a plurality of code words are obtained for a certain CDS value, the order of the code words within the same CDS value is arbitrary and is not limited to the code conversion shown in FIG. 5.

In general, image signals have strong correlation in the time axis direction and large low-frequency components, so the difference signal between adjacent sample values
The level of Bi is small. Therefore, if the code conversion shown in FIG. 5 according to the present invention is applied to a general image signal, the absolute value of the CDS of the code Ci becomes small, and the DC component and low frequency component of the code can be suppressed.

On the other hand, the output c from the reference data extractor 230
is the ROM251 address signal.
1. The signal c consisting of the reference data A ₃ i is an n-bit signal, and the ROM 251 arranges n-bit codes for the reference data A _{3 i} in descending order of CDS. FIG. 6 shows an example of code conversion when n=8 bits.

Since a general image signal has a large correlation in the time axis direction and a large low frequency division, the level change of the signal c is small. Therefore, if the new code read from the ROM 251 is A' _{3 i using the code A 3 i} of the signal c as an address signal, the CDS of A' ₃ i3 and A' ₃ i+3 successively output from the ROM 251 match. The probability of doing so is extremely high, and even if there are differences, the differences are small.

Sign inversion circuit 2 converts the output signal from ROM251
52, and for each reference data (i.e., N(=
3) At every τ), the levels of “0” and “1” are inverted.
That is, if the sign obtained by inverting the "1" and "0" levels of the code A' ₃ i is expressed as ' ₃ , then the sign inverting circuit 25
2, the code string A ₃ i−′3, A′ ₃ i, A ₃ i
+'3, A ₃ i+'6, ... is a code string A ₃ i-'3,' ₃
i, A ₃ i+'3, ₃ +'6...
Hereinafter, the output data of the sign inversion circuit 252 will be expressed as D ₃ i.

Therefore, the CDS of two adjacent n-bit codewords
When you calculate the sum of the two, they cancel each other out, and the sum becomes 0 or a small value. That is, A ₃ i-'3 and
The sum of CDS of A ₃ i becomes 0 or a small value.

As described above, the CDS of the code created from the m-bit difference signal is small, and the n-bit code based on the reference data cancels the CDS of each adjacent reference data, thereby reducing the DC component of the code. , it is possible to reduce the low frequency components.

The output of the sign inversion circuit 252 obtained in this manner is supplied to the terminal Y ₂ of the data selector 260.

The data selector 260 alternately selects the output e from the ROM 250 and the output from the sign inversion circuit 252, selects and outputs m-bit data C ₃ i-1 and C ₃ i+1 from the output e from the ROM 250, and From the output from the sign inversion circuit 252, n-bit reference data D ₃ i is selectively output. Therefore, the output f (f in FIG. 3 2) from this data selector 260 is (C ₃ i-1, D ₃ i, C ₃ i+1)
The number of data bits is (m, n,
It can be expressed as a code corresponding to m).

Thereafter, the other sample values are bit-compressed in the same manner as codes of the number of bits (m, n, m) for each three sample values.

In this way, the output f obtained by bit compression and code conversion in the encoder shown in FIG.
The data is sequentially written into the memory 40 via the PCM processor 30 shown in FIG.

Here, one word is n bits, and n=2×m
Then, the code can be efficiently written into the memory 40.

That is, the memory 40 is configured to store in word units, n-bit data D ₃ i is written as is in word units, and m-bit data is written with the first data C ₃ i-1 as half of one word (for example, in the upper Subsequently, the next data C ₃ i+1 is written to the remaining half of the word (eg, the lower m bits).

By doing so, not only can data be written in the memory 40 densely without creating wasted space, but also the memory capacity can be reduced.
Since all data can be processed in fixed word units during both recording and reproduction, it is possible to prevent the processing in the PCM processor 30 from becoming complicated, and it is possible to achieve the effect of reducing the circuit scale.

In this way, the data is sequentially read word by word through the PCM processor 30, and the read n-bit parallel data is successively converted word by word into serial data and output. As a result, as shown in Fig. 3 2g, the above bit number (m, n, m)
The code data (C ₃ i-1, D ₃ i, C ₃ i+ _{1) is serial data g of the number of bits (m, m, n) in the order of (C 3 i} -1, C ₃ i+1, D 3 i). It is output from the PCM processor 30 as This serial data output g
is directly recorded on the magnetic tape 4 by the magnetic head 3 via the recording amplifier 60 (so-called NRZ recording).

Next, an embodiment of the decoder 90 according to the present invention is shown in FIG. 7, and a waveform diagram of each part for explaining its operation is shown in FIG. 8.

During reproduction, the data recorded as described above is reproduced from the magnetic tape 4 by the magnetic head 3, and is appropriately equalized by the reproduction equalizer 70.
From (C ₃ i
-1, C ₃ i+1, D ₃ i) in the order of the number of bits (m,
A serial data output g'(g' in FIG. 8) of the data m, n) is obtained.

This serial data output g' is
The data is converted word by word into parallel data via 0 and then sequentially written into the memory 40. The data written to the memory 40 in the order (C ₃ i-1, C ₃ i+1, D ₃ i) is first m-bit data C ₃ i-1,
Next, n-bit data D ₃ i is read out, followed by the remaining m-bit data C ₃ i+1. Therefore, the PCM processor 30 outputs an output a' (eighth
a') in the figure is obtained, and this output a' is supplied to the terminal 301 of the decoder 90 shown in FIG.

Here, from equation (1) above, the original sample value A ₃ i-1 and
A ₃ i+1 can be determined by the following formula.

A ₃ i-1=A ₃ i-B ₃ i-1 A ₃ i+1=A ₃ i-B ₃ i+1 (2) The decoder 90 receives the recorded and reproduced data (C ₃
By obtaining n-bit data B ₃ i-1, B ₃ i+1 and A ₃ i from (i-1, D ₃ i, C ₃ i+1) and performing calculations based on equation (2) above, the original This is to restore the sample values (A ₃ i-1, A ₃ i, A ₃ i+1).

That is, in FIG. 7, the output a' from the PCM processor 30 supplied to the terminal 301 is input to the reference data extractor 330, while the output a'
0, the output b'(b' in Fig. 8) is delayed by a time corresponding to the sampling period τ, and the output b'(b' in Fig. 8) is
Provided as a bit address signal.

The m-bit data C ₃ i-1 and C ₃ i+1 outputted from the delay device 310 in the ROM 350 are n-bit data according to the characteristics shown in FIG.
They are converted into B ₃ i-1 and B ₃ i+1, respectively. As an example, as shown in FIG.
If the output data Ci corresponds to _a5 , data Bi having a value of 54 is output from the ROM 350.

Thus, the output c'(c' in FIG. 8) converted into n bits by the ROM 350 is supplied to one side of the subtracter 340.

In the reference data extractor 330, the reference data D ₃ i included in the above output a' is N(=3)τ
The reference data is extracted every time, and the sign is inverted by the sign inversion circuit 331 every one reference data (every N (=3) τ). The output signal of the sign inversion circuit 331 (A′ ₃ i, A ₃
i′+3...) is supplied as the address signal of the ROM 332, and based on the code conversion shown in FIG. 6, the original reference data (A ₃ i, A ₃ i+3,...) is obtained, and 3τ
The reference data is held and output for a period of .
The output signal d'(d' in FIG. 8) of the ROM 332 is input to the other side of the subtracter 340 and is also supplied to the terminal Y ₂ of the data selector 360.

In the subtracter 340, the reference data A ₃ of the above output d'
Difference data between i and the above output c′ B ₃ i−1, B ₃ i+
1 is performed, and the subtracter 340 outputs the difference data A ₃ i-1, A ₃ i+1 shown in equation (2) above. This output e'(e' in FIG. 8) is supplied to the terminal _Y1 of the data selector 360.

The data selector 360 selects the reference data A ₃ i from the output d' and the difference data A ₃ i from the output e'.
-1 and A ₃ i+1 are selected, and the data f'(f' in FIG. 8) corresponding to the original sample values (A ₃ i-1, A ₃ i, A ₃ i+1) is restored and sent to the terminal 302. is output to.

In the embodiment of the present invention shown in the waveform diagrams of FIGS. 3 and 8, code data (C ₃ i-1, D ₃ i, C ₃ i+
1 in the order of (C ₃ i-1, C ₃ i+1, D ₃ i)
It is now possible to output from PCM processor 30.
Here, the m-bit data Ci has a small CDS and has few DC components and low frequency components. On the other hand, regarding D ₃ i of n-bit data, A ₃ i'-3 and ' ₃ cancel out the CDS to suppress the DC component and the low frequency component.
Therefore, the DC component and the low frequency component can be further suppressed by the following procedure. That is, the code data reading order in the PCM processor 30 is set in a 4-word period (C ₃ i-4, C ₃ i-2, A' ₃ i-3),
(′ ₃ , C ₃ i−1, C ₃ i+1),
Read two pieces of n-bit data consecutively. As a result, n-bit data A' ₃ i-3 and A ₃ i' are adjacent to each other,
The CDS cancels each other within two words, creating a DC component,
The effect of significantly suppressing low frequency components can be obtained.

Another embodiment of the invention is shown in FIG. FIG. 9 is a block diagram showing another embodiment of the encoder 20 according to the present invention, and FIGS. 10 and 11 are waveform diagrams of various parts for explaining its operation. FIG. 12 is a block diagram showing another embodiment of the decoder 90 according to the present invention, and FIG. 13 is a waveform diagram of each part thereof. 9th
Parts of FIG. 12 and FIG. 12 are common to FIG. 2 and FIG. 7, and the common parts are denoted by the same reference numerals and detailed explanation thereof will be omitted.

In FIG. 9, from the terminal 201 to A/ in FIG.
The n-bit digital signal a output from the D converter 10 is input, and the following signals b, c, and d are the second
Obtained similarly to the figure. Figures 10 a to d show each signal a.
It is a waveform diagram of ~d.

In this embodiment, one redundant bit is added to the beginning of the n-bit reference data A ₃ i extracted by the reference data extraction circuit 230, and a sign of n+1 bits is added.
NRZI conversion (a code conversion method that does not invert if the code is "0" and inverts if the code is "1"), and converts the DSV value immediately before the reference data A ₃ i (the "1" level from the past to the present and the "0" level). This method suppresses the DC component and low-frequency component of the transmission code by determining the difference in the total number of occurrences of each level and controlling the added redundant bits so that the following DSV values approach 0. The details will be explained below.

The output of the subtracter 240 is input to one input terminal X ₁ of the data selector 420 and the other input terminal X ₁ via a delay device having a delay time τ. The data selector 420 alternately selects the signals input from the terminals X ₁ and X ₂ to select the signal d ₁ (10th
Output d ₁ ) in the figure. The signal d ₁ is input to the ROM 250, and the DC component and low frequency component are suppressed according to the characteristics shown in FIGS. 4 and 5, and the signal e (e in FIG. 10) is generated.
is output, and the signal e is connected to the terminal _Y1 of the data selector 260 and the DSV counter circuit 430 that counts the DSV.
is input.

On the other hand, the reference data A ₃ i extracted by the reference data extraction circuit 230 is input to the NRZI conversion circuit 440, and after NRZI conversion (NRZI converted reference data is designated as E ₃ i), the redundant bit control circuit 4
50 is entered. The redundant bit control circuit 450 adds one redundant bit immediately before the signal E ₃ i and controls its sign so that the following DSV values approach zero. Note that redundant bits are added according to the NRZI conversion rules, which will be explained using FIG.

FIG. 11 is an explanatory diagram of a redundant bit control method in the redundant bit control circuit 450. 1 and 2 in Fig. 11 are immediately before the reference sample value E ₃ i (signal C ₃ i-2)
3 and 4 are for negative cases. Further, 1 and 3 indicate the case where the CDS of E ₃ i is positive, and 2 and 4 indicate the case where the CDS of E 3 i is negative. In each case, the redundant bits are controlled so that the DSV up to E ₃ i approaches 0. That is, 1,4
In this case, the redundant bit becomes “1” and the data E _{3
E 3 i}
control so that it is output as is.

By controlling the redundant bits as described above, the DSV value can be brought close to 0, and the effect of suppressing DC components and low frequency components can be obtained.

Also, no matter which redundant bit is selected, the data
If the DSV value up to E ₃ i does not change, the signal
The sign of the redundant bit is controlled so that the sign is inverted between the last bit of C ₃ i-2 and the redundant bit. By controlling in this manner, it is possible to increase the frequency of code inversion, provide a large amount of timing extraction information required during reproduction, and have the effect of reducing transmission errors.

The redundant bit control circuit 45 operates as described above.
The output of 0 is input to the data selector 260 and the DSV counter circuit 430. In the following, reference data to which redundant bits have been added will be referred to as F ₃ i.

The signal F ₃ i is input to the DSV counter circuit 430, and following the difference signal (C ₃ i-3, C ₃ i-2)
A DSV count is performed.

The data selector 260 alternately selects the difference signal and the reference data, and selects the signal f (f in FIG. 10).
get. Hereinafter, similarly to the embodiments shown in FIGS. 1 and 2, the signal f is sequentially written to the memory 40 via the PCM processor 30, and then, similarly to the embodiment shown in FIG. (g in Figure 10) is output. In the case of this embodiment, if the number of bits is set so that n+1=2m, one word can be treated as n+1 bits, and processing can be performed in units of words. Like the embodiment shown, memory can be used efficiently.

Next, FIG. 12 shows an embodiment of a decoder corresponding to the encoder of FIG. 9. FIG. 13 is a waveform diagram of each part. A part of FIG. 12 is common to FIG. 7, and the common parts are given the same reference numerals and detailed explanation thereof will be omitted. In FIG. 12, 510 is an NRZI demodulation circuit, and 520 is a redundant bit removal circuit.

The signal recorded as shown in Figure 10g is the first
It is reproduced as shown in Figure 3g'. The signal g' is converted word by word into parallel data via the PCM processor 30, and then sequentially written into the memory 40. The data written to the memory 40 in the order of (F ₃ i, C ₃ i-1, C ₃ i+1) is (C ₃ i-1, F ₃ i, C ₃ i
+1) (a' in FIG. 13) and input to the decoder from the terminal 301 in FIG. 12.

Data a' inputted from the terminal 301 is inputted to the reference data extractor 330 and also inputted to the delayer 310. Similarly to the embodiment of FIG. 7, the data a' input to the delay device 310 is delayed by a time τ (b' of FIG. 13), and then its output is sent to the ROM 35.
0, n-bit difference data (c' in FIG. 13) is obtained, and is input to the subtracter 340.

On the other hand, the reference data F ₃ i extracted by the reference data extractor 330 is input to the NRZI demodulation circuit 330 and demodulated, and then the redundant bits added to the beginning of the reference data are removed by the redundant bit removal circuit 520 ( d' in FIG. 13, the output data d' is input to the subtraction circuit 340 and the Y ₂ terminal of the data selector 360.

In the subtraction circuit 340, the operation shown in equation (2) is performed as in the embodiment shown in FIG. 7, and the original sample value is restored (e' in FIG. 13). The output data e' of the subtraction circuit 340 is input to the terminal _Y1 of the data selector 360, and is processed in the same manner as in the embodiment shown in FIG. 7 to restore the image signal V'.

In the embodiments shown in FIGS. 9 and 12, NRZI conversion is performed to suppress DC components and low-frequency components of n-bit reference data, and redundant bits are added according to the NRZI conversion rules. Ta. However, it is also possible to suppress DC components and low frequency components without performing NRZI conversion on the n-bit reference data.

In FIG. 9, the output of the reference data extractor 230
A ₃ i is input to the redundant bit control circuit 450 without going through the NRZI conversion circuit 440. If the redundant bit is "1", each sign of the input reference data A ₃ i is inverted and ₃ is output; if the redundant bit is "0", it is not inverted and is output as A ₃ i. . The redundant bits are controlled based on the DSV value immediately before the reference data A ₃ i and the CDS value of the reference data A ₃ i, as in the embodiment shown in FIG.
The DSV value is controlled to approach 0. By performing the same processing as in the embodiment shown in FIG. 9, the direct current component and low frequency component can be suppressed.

The operation of the decoder corresponding to the above will be explained. 1st
In Figure 2, the output of the reference data extractor 330 is
The signal is input to the redundant bit removal circuit 520 without going through the NRZI demodulation circuit 510. Redundant bit removal circuit 52
At 0, the sign of the input reference data is inverted based on the sign of the redundant bit, and the redundant bit is further removed to output restored reference data. The above inversion control is made to correspond to the operation of the encoder, and in a decoder corresponding to the example of the encoder described above, code inversion is performed when the redundant bit is "1", and non-inversion control is performed when the redundant bit is "0". Part 1 below
The video signal V' can be restored by performing the same processing as in the embodiment shown in FIG.

〔Effect of the invention〕

As described above, according to the present invention, the information signal to be transmitted can be improved without causing deterioration of the information signal, or even if it occurs, the influence thereof is small, and without causing error propagation due to accumulation of quantization noise or code errors. In addition to efficiently reducing the amount of information, it is possible to suppress the DC and low-frequency components of the digital signal being transmitted without adding redundant bits, or with the minimum amount of redundant bits added, thereby reducing code errors. This has the effect of increasing the amount of information that can actually be transmitted.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention;
FIG. 2 is a block diagram showing an embodiment of the encoder according to the present invention, FIG. 3 is a waveform diagram of each part thereof, FIG. 4 is a diagram showing its encoding and decoding characteristics, and FIGS. FIG. 7 is a block diagram showing an embodiment of the decoder according to the invention, FIG. 8 is a waveform diagram of each part thereof, and FIG.
The figure is a block diagram showing another embodiment of the encoder according to the present invention, FIGS. 10 and 11 are waveform diagrams of each part thereof, and FIG. 12 is a block diagram showing another embodiment of the decoder according to the present invention. , FIG. 13 is a waveform diagram of each part thereof. 20...Encoder, 90...Decoder, 210,3
10,410...Delay device, 230,330...Reference data extractor, 240,340...Subtractor,
250, 251, 332, 350...ROM, 2
52, 331... Sign inversion circuit, 260, 36
0,420...Data selector, 430...
DSV counter circuit, 440...NRZI conversion circuit,
450... Redundant bit control circuit, 510...
NRZI demodulation circuit, 520...redundant bit removal circuit.

Claims (1)

[Claims] 1. For each of N sample values (N is an integer of 2 or more) of the information signal, at least one sample value among them is used as a reference sample value, and the number of bits is n (n is an integer of 2 or more).
In a code conversion method that encodes the remaining sample value with the number of bits m (m<n integer) based on the difference from the reference sample value, CDS ( Assign the above m-bit code with a large absolute value of the difference in the number of occurrences of "1" and "0" from the beginning to the end of one code, and for the above difference with a small absolute value,
A code conversion method characterized in that encoding is performed by assigning the above-mentioned m-bit code having a small absolute value of CDS. 2. Assign the n-bit codes to the reference sample values in the order of their CDS sizes and convert the codes, and then convert the code-converted n-bit reference sample values alternately for each reference sample value. 2. The code conversion method according to claim 1, wherein the code is inverted. 3 Before the encoded reference sample value above
DSV (“1” level and “0” from the past to the present)
add at least one redundant bit in front of the encoded reference sample value, calculate the CDS of the encoded reference sample value, Controls whether or not the sign of the coded reference sample value is reversed by the sign of the code, and the DSV up to the coded reference sample value before the coded reference sample value is
2. The code conversion method according to claim 1, wherein the sign of the redundant bit is controlled so that the subsequent DSV approaches 0 based on the CDS of the coded reference sample value. 4 Before the encoded reference sample value above
Determine the DSV, perform NRZI conversion on the encoded reference sample value, add at least one redundant bit in front of the reference sample value based on the NRZI conversion rule, and calculate the CDS of the NRZI-converted reference sample value. Find the above DSV and the above NRZI converted reference sample value.
2. The code conversion method according to claim 1, wherein the code of the redundant bit is controlled by CDS so that subsequent DSV approaches 0.