JPH0869670A - Digital signal transmission device and digital magnetic recording and reproducing device - Google Patents

Abstract

PURPOSE: To provide a digital signal transmission method and a digital magnetic recording and reproducing device in which the size of the hardware is reduced and the self-synchronization capability of the data being handled is improved. CONSTITUTION: Input data columns inputted from an input terminal 1 are sent to a PR4 channel 5 through an S/P converter 2, an 8/9 encoder 3 and a P/S converter 4. The signals outputted from the PR4 channel 5 are transmitted to a phase detecting circuit 14 and a viterbi decoding circuit 9. The signals sent to the circuit 14 are phase detected and outputted from a synchronization information output terminal 15. Moreover, the signals transmitted to the circuit 9 are outputted from an output terminal 13 through an S/P converter 10, an 8/9 decoder 11 and a P/S converter 12. The PR4 channel 5 consists of a precoder 6, a transmission circuit 7 and an equalizing circuit 8.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital signal transmission device for converting recorded data into a digital reproduction signal, and more particularly to a digital signal transmission device preferably applied to a digital magnetic recording / reproduction device.

[0002]

2. Description of the Related Art As a signal processing system in digital magnetic recording, a system combining partial response and maximum likelihood decoding is advantageous for high density recording.

The partial response method is a method of positively utilizing intersymbol interference which is a problem during high density recording.
Specifically, the output (dipulse response) waveform when recording a signal represented by a unit bit, for example (... 0001000 ...), uses a correlation waveform in which the response is not 0 at multiple recording points. Then, equalization is performed so as to show a prescribed waveform. As the types of partial responses, PRS (1,1), PRS (1, -1),
There are PRS (1,0, -1) and the like, but here, PRS (1,0, -1) which is often used in a magnetic recording system will be described as an example.

Here, PRS (1, 0, -1) is also called partial response class 4 (hereinafter referred to as PR4), and the equalized waveform of the dipulse response is 1 at the sample point (symbol existence point). , 0, −1 to equalize. The system polynomial of PR4 is represented by G (D) = 1-D ² (D: 1-bit delay operator). Also, since PR4 itself has the property of causing a catastrophic error, precoding is performed before recording. This precoding system polynomial is H (D) = 1 / (1-D ² ). That is, the propagation of an error is prevented by first performing the inverse conversion that is originally PR4 decoding.

FIG. 3 is a diagram showing an outline of a simplified PR4 channel model.

In FIG. 3, the recording data input from the input terminal 41 is sent to the precoder 42, precoded based on the value of H (D), and sent to the recording circuit 43 in the magnetic recording channel 46. The above system polynomial G
The arithmetic processing is performed based on the value of (D) and the result is sent to the adding circuit 44. In addition, the addition circuit 44 performs addition processing on the noise input from the noise input terminal 45 and the recording data processed by the recording circuit 43, and sends the addition processing to the equalizer 47, where the system polynomial G (D) The value is calculated based on the value, sent to the decoder 48, decoded, and output from the output terminal 49 to the outside.

The magnetic recording channel 46 is a comprehensive view of the recording head, the recording medium, the reproducing head and the reproducing circuit in addition to the recording circuit 43. The noise is caused by the reproducing head from the recording medium. These are noise picked up, noise generated in the reproducing circuit, and the like.

In FIG. 3, the signal actually input to the input terminal is sample data of digital binary data, and this sample data is first converted into a recording current by the recording circuit 43. This recording current becomes a reproduction signal through the recording medium, and the reproduction signal is modeled by adding the noise, and the signal is A / D converted and equalized by the equalizer 47 to reproduce data. Is done.

Although the ideal state has been taken as an example here, the magnetic recording channel 4 is actually caused by intersymbol interference or the like.
Since 6 cannot be said to be (1-D), the equalizer 47 cannot actually be said to be (1 + D), and the data processing becomes more complicated.

FIG. 4 is a diagram showing an example of an ideal transition of the signal data processed by the PR4 channel shown in FIG.

Here, in FIG. 4, the precoding data and the decoded data are digital binary data.
On the other hand, the equalized data is the analog reproduction signal A
It becomes the equalized form of the / D conversion. In reality, noise and distortion are added to the digital data that has been subjected to arithmetic processing, and data after equalization is obtained.

It can be seen from FIG. 4 that the reproduction equalized signal from the PR4 recording channel has three levels {-1, 0, +1}.

FIG. 5 is a diagram showing an example of an image of the reproduction equalized signal. In FIG. 6, the sample points are represented by white circles.

In FIG. 5, in order to return the reproduction equalized signal to binary data, ± 1 is decoded into 1 and 0 is decoded into 0. As a method of achieving this, ternary level detection using a fixed threshold and Viterbi (vi
terbi) Decoding etc. are considered.

Here, in the ternary level detection, a threshold level which is a fixed value, that is, a so-called threshold value is set between 0 and +1 and 0 and -1, and the sample point falls in a region where the above threshold value is taken into consideration. It is what is decoded by. The advantage of this method is that a very simple circuit is sufficient, but the drawback is that the detection capability is not very high.

Maximum likelihood decoding or Viterbi decoding is a method of estimating the most probable data series, a so-called path, among the possible data series by using the values of sample points and the values of preceding and following sample points. The detection ability is expected to be higher than that of the ternary level detection described above. However, in Viterbi decoding, although the path whose path has been determined by calculation is output, if the 0 level continues in the channel output signal, the path is not fixed and the signal data continues to be stored in the memory. Therefore, the number of consecutive 0s (hereinafter 0
It is called running length. ) Exceeds the memory length of the path memory, an overflow may cause an error.

Generally, a signal is encoded to solve this problem. As this encoding method, for example, 8/9 code conversion is used. In the 8/9 code conversion, 8-bit binary data (hereinafter referred to as an information word) is converted into 9-bit binary data (hereinafter referred to as a code word) according to a predetermined conversion rule, that is, an encoding process. Is performed, the encoded data is recorded / reproduced, the obtained decoded data is inversely converted, that is, the decoded data is decoded, and the original data is restored. In addition, in order to prevent the overflow of the path memory, it is possible to set the 0-run length in the codeword string and to perform code conversion such that a codeword that satisfies this condition is coded.

However, since the system polynomial of PR4 is G (D) = 1-D ² as described above, the calculation is performed between the value of the sample point and the value of the sample point two before. Since there is no relationship between the odd-numbered sample and the even-numbered sample, each of them has independent P
It can be regarded as a sequence of RS (1, -1).

FIG. 6 is a diagram showing an example of a Viterbi decoder used in combination with the conventional PR4.

FIG. 6A is a diagram showing that the data inputted from the input terminal 71 is processed by the Viterbi decoder 72 and outputted from the output terminal 73. The Viterbi decoder 72 is
Since it can be considered that the odd-numbered column and the even-numbered column are independent signals, the Viterbi decoder 72 as shown in FIG.
This is the same as the PRS (1, -1) Viterbi decoders 72a and 72b which are independent for the odd and even columns. That is, the decoded data input from the input terminal 71 is separated into an odd-numbered column and an even-numbered column, and a path metric calculation is performed for each data column. You must limit the length.

Further, here, the maximum 0 length is k, and the odd number column /
A set of code words that can express the maximum 0-length of even-numbered columns by k ₁ is represented by k / k ₁ . For example, IBM US Pat. No. 4,707,681 (US Pat. No. 47).
07681), the technology disclosed in (k / k ₁ )
= (4/4) A set of code words is handled. This is a set of code words whose 0-run length is 4 or less, and whose 0-run length is 4 or less in odd-numbered columns and even-numbered columns. Perform encoding processing with this codeword,
If the path memory length of the Viterbi decoder is made sufficiently longer than the 0-run length limit, the above-mentioned problem can be effectively avoided.

[0022]

By the way, the above-mentioned P
If the path memory length of the Viterbi decoder used together with R4 is sufficiently long, the overflow of the path memory can be avoided, but the hardware becomes large.

Another problem with PR4 is that self-synchronization is difficult because it does not have a sampling clock component. As a synchronization method in PR4, a method of detecting a peak of an analog reproduction signal and performing synchronization is generally used. However, in the case where the reproduction signal detection and subsequent steps are all performed by digital signal processing, it is necessary to obtain a synchronization signal from sampled data. There is.

Here, for example, as a method of obtaining the synchronization signal from the sampled data, (1, 0, -1) (-1, 0,
The method of calculating the sampling phase from the equalized reproduction signal having the zero-cross point 1) may be used. However, in this method, if the zero-cross points do not frequently exist, the phase following property deteriorates. Therefore, in this method, the pattern in which the equalized output is (1, 0, -1) (-1, 0, 1) is (101) in the recorded binary data string, so the above-mentioned recorded binary data is obtained. In a row (10
The phase followability greatly changes depending on how much 1) is included.

Further, in the conventional conversion code, (101)
Since there is no guarantee that such a pattern will appear within a certain interval, only the limitation on 0 running length was considered. Therefore, there is a problem that the phase information for self-synchronization is not regularly extracted and a certain synchronization performance cannot be obtained.

Therefore, the present invention has been made in view of the above-mentioned circumstances, and the digital signal transmission method and the digital magnetic recording / reproducing apparatus capable of miniaturizing the hardware of the apparatus and improving the self-synchronization of the data to be handled. The purpose is to provide.

[0027]

In order to solve the above-mentioned problems, a digital signal transmission method according to the present invention is designed to convert an input binary data string from a code word of a binary number string including a (101) data sequence. An encoding circuit for performing an encoding process on the data string, a precoder for precoding the encoded data, and a data transmission system having characteristics of partial response class 4 for transmitting the precoded data by the precoder, A so-called PR4 channel, an equalization circuit for equalizing data obtained through the data transmission system, and a zero-cross point of an output signal from the equalization circuit are detected based on the (101) data series. It has a phase detection circuit for extracting phase information and a maximum likelihood decoding circuit for converting an output signal from the equalization circuit into maximum likelihood decoded data.

Further, the encoding circuit performs an encoding conversion process of 8-bit input binary data into a 9-bit code word.
/ 9 encoder.

Further, in the above codeword, the maximum 0 running length, which is the maximum number of consecutive 0s in the codeword string, is k, 6 ≦ k ≦ 10.
And the maximum 0 running length k1 of the odd / even columns, which is the maximum number of consecutive 0s in each of the case where the code word sequence is divided into the odd / even columns, is 6 ≦ k ≦ 7. .

Further, the maximum likelihood decoding circuit is
rbi) A decoding circuit.

Also, a digital magnetic recording / reproducing apparatus using a magnetic recording / reproducing system as a data transmission system of the above-mentioned digital signal transmitting apparatus may be used.

[0032]

According to the digital signal transmission apparatus and the digital magnetic recording / reproducing apparatus of the present invention, the encoding circuit is 8 /
Using 9 encoders, the maximum 0 running length, which is the maximum number of consecutive 0s in the codeword string used in this 8/9 encoder,
The path length of the maximum-likelihood decoding circuit is shortened by setting the maximum 0 run length of the odd-numbered / even-numbered columns, which is the maximum number of consecutive 0s when the codeword sequence is separated into the odd-numbered / even-numbered columns. And the (101) sequence appears at least once within a word long time.

Further, the phase information is periodically obtained by performing the phase detection based on the (101) data series.

[0034]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Preferred embodiments to which the digital signal transmission device according to the present invention is applied will be described in detail below with reference to the drawings.

FIG. 1 is a diagram showing a schematic configuration of a main part of a digital signal transmission device according to the present invention.

In FIG. 1, the input data input from the input terminal 1 is serial / parallel (S / P) converters 2, 8 /
It is sent to the PR4 channel 5 via the 9 encoder 3 and the parallel / serial (P / S) converter 4. The signal output from the PR4 channel 5 is sent to the phase detection circuit 14 and the Viterbi decoding circuit 9. The signal sent to the phase detection circuit 14 is output from the synchronization information output terminal 12 after the phase is detected. The signals sent to the Viterbi decoding circuit 9 include S / P converter 10, 8/9 decoder 11,
It is output from the output terminal 13 via the P / S converter 12. The PR4 channel 5 is composed of a precoder 6, a transmission circuit 7 and an equalization circuit 8.

Here, in FIG. 1, the S / P converter 2
Divides the serial data string, which is the input data, into 8-bit data, and sends each 8-bit data to the 8/9 encoder 3.

The 8/9 encoder 3 encodes each of the above 8-bit data sent from the S / P converter 2 and sends it to the P / S converter 4 as a code word of 9-bit data.

The P / S converter 4 converts the code word of the 9-bit data processed by the 8/9 encoder 3 into a serial data string, that is, converts the coded data to P
Send to R4 channel 5.

The PR4 channel 5 is a circuit group whose main part is composed of a precoder 6, a transmission circuit 7 and an equalization circuit 8. Here, the characteristic polynomial of PR4 is G (D) = 1
-D ² , the precoding system polynomial is H (D) =
Since it is 1 / (1-D ² ), the encoded data is precoded by the precoder 6 based on the value of H (D), and sent to the transmission circuit 7. The precoded data is arithmetically processed by the transmission circuit 7 based on the value of G (D) and converted into a digital signal,
It is sent to the equalization circuit 8. The digital signal is equalized by the equalization circuit 8 based on the value of G (D) so that the dipulse response matches the PR4 standard (1, 0, -1), and a digital equalized signal sample is obtained. And is sent to the Viterbi decoding circuit 9 and the phase detection circuit 14.

The Viterbi decoding circuit 9 performs maximum likelihood decoding processing on the digital equalized signal samples sent from the equalization circuit 8 in the PR4 channel 5 independently for odd columns and even columns, and performs maximum likelihood decoding. Data to S / P converter 10
Send to

The S / P converter 10 includes a Viterbi decoding circuit 9
The maximum likelihood decoded data sent by the above is divided into 9-bit data, and each 9-bit data is sent to the 8/9 decoder 11.

The 8/9 decoder 11 is an S / P converter 10
Decode each 9-bit data sent from
It is sent to the P / S converter 12 as a decoded word of bit data.

The P / S converter 12 is an 8/9 decoder 11
The decoded word of the 8-bit data sent from the above is converted into a serial data string, that is, restored to the original input data string,
Output to the outside through the output terminal 13.

Further, the phase detection circuit 14 extracts a (1,0, -1) (-1,0,1) pattern from the digital equalized signal sample sent from the PR4 channel 5, and extracts this pattern from the patterns. Phase calculation is performed from the zero-cross points existing in the
Sends information to the synchronization circuit. As an example of this phase calculation method, for example, a sampling value identified as 0 is δA, a reference amplitude value of ₊₁ is A ₊ , and a reference amplitude value of -1 is A _−.
Assuming that the amount of phase shift from the symbol existing point is δt, δt is expressed by equation (1).

Δt = 2 × δA / (A ₊ −A ₋ ) ... (1) The phase is calculated using the calculated value of δt.

Here, the operation principle of the 8/9 encoder 3 and the 8/9 decoder 11 will be described. 8/9 encoder 3
Prepares a codeword set satisfying the condition of including at least one (101) pattern in order to enhance self-synchronization, and selects a codeword with 0-length limitation again from this codeword set. It is used to encode this selected codeword.

First, the following method is used to select a code word. Let X be an information word and Y be a code word. Here, since the 8/9 conversion code is used, X and Y are represented by the equations (2) and (3).

X = (X ₁ X ₂ X ₃ ... X ₈ ) ... (2) Y = (Y ₁ Y ₂ Y ₃ ... Y ₈ Y ₉ ) ... (3) where: The condition of X and Y is shown by the equation (4), and (101)
The condition that one or more patterns are included is shown in Expression (5). There are 312 code words that satisfy the expression (5).

[0050]

[Equation 1]

Next, the above-mentioned 0 running length, that is, the number of consecutive 0s sandwiched between 1 and 1 is limited. With this restriction, 256 codewords actually used are selected. here,
Let d be the minimum value of 0 run length, k be the maximum value of 0 run length, and k _{1 be} the maximum value of 0 run length when the data sequence is divided into odd and even columns. Also, since we consider 8/9 code conversion,
The coding rate r is r = 8/9, and the theoretical limit capacity C is C
≧ r. Further, when d ≧ 1, C <r holds, so that d = 0 is determined here. k ₁ is a finite value,
When the appearance interval of the (101) pattern is 15, the ranges of k and k ₁ are given by the expressions (6) and (7).

K ≦ 10 (6) k ₁ ≦ 7 (7) Based on the above conditions, the number of codewords obtained by changing the values of k and k ₁ is examined. The condition that the number of s exceeds 256 is that when k ₁ is 6 or 7, 6 ≦ k ≦ 10 when k ₁ = 6 and 5 ≦ k ≦ 10 when k ₁ = 7.

Here, for example, 0 = k = 6 and k ₁ = 6.
Suppose you set a running length limit. In this case, by selecting such that the number of consecutive 0s in the codeword is 6 or less and at both ends of the codeword is 3 or less, 0 is generated in every codeword string.
Running length can be 6 or less. In addition, the 0 length in the odd / even columns is selected so that the number of consecutive 0's in two adjacent codewords is 6 or less. Therefore, these conditional expressions are the expressions (8), (9) and (1
It is shown by the equation (0).

(Y ₁ + Y ₂ + Y ₃ + Y ₄ ) ・ (Y ₆ + Y ₇ + Y ₈ + Y ₉ ) = 1 (8) (Y ₁ + Y ₃ + Y ₅ + Y ₇ ) ・ (Y ₃ + Y ₅ + Y ₇₎ + Y ₉ ) = 1 (9) Y ₂ + Y ₄ + Y ₆ + Y ₈ = 1 (10) By doing this, the phase detection pattern (101) always comes within 15 bits. It is possible to detect the phase automatically.

FIG. 2 is a diagram showing a set of code words satisfying the above-mentioned conditional expression.

According to FIG. 2, a total of 257 code words can be obtained. Of these code words, 256 are selected as the conversion code, and 9 bits are selected for 8-bit binary data.
A correspondence table is created in which the codewords of bits are in one-to-one correspondence. According to this correspondence table, a circuit that outputs a 9-bit code word for an 8-bit binary data input is
The 8/9 encoder 3 is a circuit that outputs 8-bit binary data in response to a 9-bit codeword input is the 8/9 decoder 11. Each circuit is purely composed of combinational circuits, since it only converts binary data into other binary data. Further, the 8/9 encoder 3 is inserted immediately before the PR4 channel 5 so as to perform the encoding processing before the signal processing is performed on the PR4 channel 5, and the 8/9 decoder 11 decodes the decoded data from the Viterbi decoding circuit 9. To be processed.

FIG. 3 is a diagram showing a specific example of the 8/9 encoder used in this embodiment.

Here, it can be seen from FIG. 3 that the 8/9 encoder is composed of pure combinational circuits. The 8/9 decoder is also composed of a combinational circuit like the 8/9 encoder.

In this embodiment, the encoding circuit is 8
Although the / 9 encoder and the 8/9 decoder are used as the decoding circuit, the present invention is not limited to these, and the read / write memory, so-called ROM, may be used to perform the encoding / decoding processing. The capacity of the ROM is 9 bits × 256 words for encoding processing, and 8 bits × 512 words for decoding processing. In this case, the ROM for the encoding process has a function of storing the data for the code word, reading the code word by using the 8-bit input data as an address, and outputting the code word, and the ROM for the decoding process is The original 8-bit data is stored in the address corresponding to the word, and the address not corresponding to the code word is set to 0.

[0060]

As described above, according to the digital signal transmission method and the digital magnetic recording / reproducing apparatus of the present invention, the input binary data sequence is a codeword of a binary number sequence including a (101) data sequence. A coding circuit for coding into a data string, a precoder for precoding the coded data, and a data transmission system having characteristics of a partial response class 4 for transmitting the precoded data by the precoder. A so-called PR4 channel, an equalization circuit for equalizing data obtained through the data transmission system, and detecting a zero-cross point of an output signal from the equalization circuit based on the (101) data sequence. And a maximum likelihood decoding circuit for converting the output signal from the equalization circuit into maximum likelihood decoded data. Because regularly the phase information is obtained, thereby improving the self-synchronization performance.

Also, using the 8/9 encoder, this 8
/ 9 maximum 0 run length, which is the maximum number of consecutive 0s in the codeword string, and the odd number column, which is the maximum number of consecutive 0s in the case where the above codeword string is divided into odd columns / even columns / By setting the maximum run length of even-numbered columns to 0, the path memory length of the maximum likelihood decoding circuit can be shortened and the hardware can be downsized.

[Brief description of drawings]

FIG. 1 is a diagram showing a schematic configuration of a main part of a digital signal transmission device according to the present invention.

FIG. 2 is a diagram showing an example of a set of code words used in this embodiment.

FIG. 3 is a diagram showing an example of a conventional PR4 channel.

FIG. 4 is a diagram showing an example of a data string processed by a conventional PR channel.

FIG. 5 is a diagram showing an example of an image of a reproduction equalized signal processed by a conventional PR4 channel.

FIG. 6 is a diagram showing an example of a Viterbi decoder used in combination with a conventional PR4 channel.

[Explanation of symbols]

 1 Input Terminal 2 Serial / Parallel Converter 3 8/9 Encoder 4 Parallel / Serial Converter 5 PR Channel 6 Precoder 7 Transmission Circuit 8 Equalization Circuit 9 Viterbi Decoder 10 Serial / Parallel Converter 11 8/9 Decoder 12 Parallel / Serial converter 13 Output terminal 14 Phase detection circuit 15 Sync information detection terminal

Claims (5)

[Claims] 1. A digital signal transmission method combining partial response and maximum likelihood decoding, wherein an input binary data string is encoded into a data string composed of a code word of a binary number string including a (101) data series. An encoding circuit, a precoder for precoding the encoded data, a data transmission system having characteristics of partial response class 4 for transmitting the precoded data by the precoder, and the data transmission system. An equalization circuit for equalizing the data obtained by the above, and a phase detection circuit for extracting phase information by detecting the zero-cross point of the output signal from the equalization circuit based on the (101) data series, And a maximum likelihood decoding circuit for converting an output signal from the equalization circuit into maximum likelihood decoded data. . 2. The encoding circuit performs an encoding conversion process on 8-bit input binary data into a 9-bit code word.
The digital signal transmission device according to claim 1, wherein the digital signal transmission device is an encoder. 3. The code word, wherein the maximum 0 running length k, which is the maximum number of consecutive 0s in the code word string, is 6 ≦ k ≦ 10, and the code word string is divided into odd-numbered columns / even-numbered columns. 3. The digital signal transmission device according to claim 2, wherein the maximum 0 running length k1 of the odd-numbered / even-numbered columns, which is the maximum number of consecutive 0s in 0, is 6 ≦ k ≦ 7. 4. The maximum likelihood decoding circuit is viterbi.
3. The digital signal transmission device according to claim 1, which is a decoding circuit. 5. A digital magnetic recording / reproducing apparatus, wherein a magnetic recording / reproducing system is used as a data transmission system of the digital signal transmitting apparatus according to claim 1.