JPS63122322A - Encoder - Google Patents

Abstract

PURPOSE:To prevent the production of level inversion by comparing the absolute value of an error caused by the result of decoding both a 1st value obtained at a 1st compression conversion means and a 2nd value obtained at the 2nd compression conversion means and outputting a 1st or 2nd value which is smaller as the result of comparison. CONSTITUTION:The level inversion takes place when a difference signal C is compressed by a compression ROM 19 and expanded afterward by an expansion ROM 41 of a decoder and the absolute value of the difference signal C'' obtained by the expansion is larger than that of the original difference signal C. Thus, the compression ROM 24 is used and the difference signal C is compressed into a signal E' lower by one step thereby preventing the absolute value of the difference signal C'' obtained at the expansion of the expansion ROM 41 of the decoder from being larger than that of the original difference signal C. Thus, although the error between the decoding output (signal A') and the original value (signal A) might be larger, the level inversion at least does not take place.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to a device that samples and quantizes an analog information signal in the time axis direction and performs digital transmission or recording/reproduction, and particularly relates to a device that samples and quantizes an analog information signal in the time axis direction and performs digital transmission or recording/reproduction. The present invention relates to an encoder suitable for preventing the occurrence of level reversal phenomena.

[Conventional technology]

In a device that digitally transmits an image signal, the number of quantization bits per 111 values (hereinafter referred to as 1 pixel) is:
In the case of linear sonization, 7 to 8 bits are usually required. When a standard television system signal is digitized by linear quantization, the transmission rate of the digital signal is 100 Mbp.
s (megabits per second), and even higher transmission rates are required for high-definition television systems that are being proposed by some.

Digital VTRs that magnetically record and reproduce digital image signals have extremely high transmission rates as described above, so they consume more tape than conventional analog recording VTRs, making it difficult to obtain sufficient recording time. In addition, the signals to be handled have a very wide band, and the operating speed of the digital signal processing circuit has become a problem, resulting in technical difficulties, and this has become a major obstacle to the widespread use of digital VTRs 1 in households.

In order to improve these problems, so-called high-efficiency coding has been studied for a long time.
a! "Digital signal processing of Ii image" (Nikkan Kogyo Shimbun)
As described in Chapter 9 of this document, as a method to reduce the number of bits per pixel, the current 11iL is predicted from the koji of the already encoded pixel, and the error from that is calculated. So-called predictive coding (DPCM) that encodes
The method is known.

The prior art will be described below with reference to the drawings.

First, before explaining the conventional encoder, let us first explain the digital VTR, which is one of the devices in which the encoder is used.
The configuration and operation will be explained.

FIG. 4 is a block diagram showing the configuration of a general digital VTR.

In FIG. 4, 1 is an image signal input terminal, 2 is an A/D converter, 3 is an encoder, 4 is a PCM processor, 5 is a memory, 6 is a modulator, 7 is a recording amplifier, 8 is a magnetic head, and 9 is a magnetic tape, 10 is a reproduction equalizer, 11 is a demodulator, 1
2 is a decoder, 13 is a D/A converter, and 14 is a reproduced image signal output terminal O. A general digital VT which is a type of magnetic recording and reproducing device.
In R, first, as shown in the figure flllA, terminal 1 is
The image signal V input from the A/D converter 2 is converted into a digital signal having n quantization bits. This n-bit digital signal is appropriately bit-compressed by the encoder 3 as described later.

The output of this encoder 3 (hereinafter abbreviated as data ◇)
are sequentially written to the memory 5 via the PCM processor 4, and when writing to the memory 5, address signals, error correction codes, etc. are added to each predetermined block of data IO as necessary. It will be done.

Then, operations such as interleaving (rearranging data to perform error correction) and shuffling (rearranging data to perform correction) are performed via the memory 5, and the data read from the memory 5 is Further, if necessary, an error detection and correction code, a synchronization signal for finding the beginning of a block, a start-stop code used for four-way playback, etc. are added by the PCM processor 4 and output.

The output data string from the PCM processor 4 is sent to the modulator 6.
After being tuned into a code with a configuration suitable for magnetic recording,
The output is sequentially recorded on the magnetic tape 9 by the magnetic head 8 via the recording 114M device 7.Next, on the reproduction side, the signal reproduced from the magnetic tape 9 by the magnetic head 8 is re-recorded by the equalizer 10 as necessary. After performing m-width equalization, phase equalization, etc. accordingly, the demodulator 11
The modulation performed during recording is demodulated to the original code, and a signal equivalent to the data string input to the modulator 6 during recording is output.

The output data string from the demodulator 11 is subjected to a PCM processor 4 that detects a synchronization signal, locates the beginning of a data block, detects and corrects a code error, or performs deinterleaving, deshuffling, etc. via a measuring circuit 5.

Data successively outputted from the memory 5 and subjected to elaboration and correction by the PCM processor 4 is supplied to the decoder 12 as bit-compressed data E' equivalent to the output data E from the encoder 3 during recording. The decoder 12 decodes the data A and outputs an expanded n-bit digital signal A'. The digital signal person with
The D/A converter 13 converts it into an analog/4G signal, restores the image signal V, and outputs it to the terminal 14. More than,
This is an explanation of the operation of a general digital VTR.

Now, conventionally, as the encoder 3 and decoder 4 shown in FIG. 4, the encoder and decoder shown in FIG. 5 and Factor 6 have been used.

FIG. 5 is a block diagram showing a conventional example of a DPCM encoder using prior value prediction, and FIG. 6 is a block diagram showing a conventional example of a decoder.

In FIG. 5, 50 is an input terminal, 5.1 is a subtracter, and 5.
2 is a compression ROM, and 53 is an expansion ROM.

54 is an adder, 55 is a delay circuit, and 56 is an output terminal.

Further, in FIG. 6, 40 is an input terminal, 41 is an expansion ROM, 42 is an adder, 43 is a delay circuit, and 44 is an output terminal.

In addition, FIG. 7 shows the compression ROM shown in FIGS. 5 and 6.
and a graph showing the conversion characteristics of expansion ROM', #! 7A
The figure is an explanatory diagram for explaining how to view the R conversion characteristic in Fig. 7,
〇The horizontal and vertical axes in Figure 7 are Figure 5 and 1, respectively.
The compression ROM and expansion BOM shown in Figure 16 are @7A
When connected as shown in the figure, the compression RO
The level of input a of M and the level of output C of expansion ROM are shown. Also, the diagonal Im(-
The numbers from -8 to +7 written near the dashed dotted line are the 7th
This shows the output level of the compression ROM or the input level of the expansion ROM shown in Figure A. Therefore, it can be said that FIG. 7 shows the input/output characteristics of the compression ROM and the input/output characteristics of the expansion ROM at the same time.

First, the operation of the encoder 3 shown in FIG. 5 will be explained.

#! In FIG. 5, the input terminal 50 of the encoder 3 is supplied with a digital Ili image signal having n quantized bits which has been subjected to digital/digital conversion by the A/D converter 2 as described above. Here, the number of quantization bits n is a value so large that the quantization error can be ignored, and in this case, for example, n-7
It is determined that

This digital signal of 7 bits/ill element is subtracted by the subtracter 51 from the signal of one pixel before (7 bits signal) as the predicted value obtained from the delay circuit 55.
Obtain a bit difference signal c4-. Here, the delay time τ of the delay circuit 55 is the pixel interval. The 8-bit difference signal CFi obtained by the subtracter 51 is converted into an m-4-bit compressed difference signal E by the compression ROM 52 having the conversion characteristics shown in FIG.

Then, this compressed difference signal E of 4 bits/pixel is outputted as the aforementioned data (2) via the output terminal 56.

Furthermore, the 4-bit compression difference signal E from the compression ROM 52 is converted into an 8-bit expansion signal C by the expansion ROM 53 having the conversion characteristics shown in FIG. .

ζHere, the other input of the adder 54 is connected to a delay circuit 55.
The adder 54 adds this signal to the expanded signal C and inputs the result to the delay circuit 55.

The above is an explanation of the operation of the encoder 3 shown in FIG.

Next, the operation of the decoder 12 shown in FIG. 6 will be explained.

In FIG. 6, at the input terminal 40 of the decoder 12! In this case, a 4-bit signal ■ equivalent to the compressed difference signal B is input, and then the decompression ROP having the conversion characteristics shown in Fig. 7 is input.
It is converted into an 8-bit differential signal C by ds1. This difference signal C is added by an adder 42 to a signal from one pixel before from a delay circuit 43 having a delay time τ equal to the pixel interval, and is then added to a 7-bit digital image signal signal equivalent to the above-mentioned digital signal signal. is output as This digital image signal is outputted via the output terminal 44t, and is then D/A converted by the D/person converter 13 as described above to become an analog image signal.

That’s it! , 6@ is a description of the operation of the decoder 12 shown in FIG.

As described above, by using the DPCM encoder tube, the number of bits per pixel can be reduced to about 4 bits, and the transmission rate can be reduced to 4 bits compared to the linear quantization method described above.
It is possible to reduce it to /7.

[Problems to be Solved by the Invention] Now, the input signal in the conventional encoder 3 shown in FIG. 5 and the output signal in the conventional decoder 12 shown in FIG. 6 each have quantized bits. By setting it to several t-7 bits, the range of the quantization level is -64 to +6
It is 3. The correspondence relationship between the 7-bit decimal representation and the binary representation is as shown in FIG.

Now, the input digital signal of n-7 bits to the encoder 3 shown in FIG.
→35, old, etc., the 8-bit difference signal C from the subtracter 51 is -31→93→74→-18
→24..., and the compression difference signal B of the compression ROM 52 is -5→7→6→-4→4...
The data of m-4 bits corresponding to K is outputted from the output terminal 56. On the other hand, the decoder 12 shown in Figure @6 receives a 4-bit signal I that is the same as the compressed difference signal E.
is input through the input terminal 40, and the 8-bit difference signal C which is the output of the expansion ROM 41 is 131→110→7.
7→“-17→31...and the output digital signal from the adder 42 is -31→79(-49)→
28→11→42... In this case, data 79 exceeds the range (-64 to +63) t- of the quantization level of the bit number n-am 7 described above, so the level is inverted to the opposite polarity and is output as data -49. Put it away.

That is, since the number of quantization bits is set to t-7 bits as described above, the output of the adder 42 is only 7 bits (the same applies to the adder 54). In other words, even if it is obtained as 8-bit data of 0X001111, the most significant bit O is deleted and output as 7-bit data, so 100
1111, that is, -49 is output.

As described above, when using a conventional encoder, depending on the level of the input signal and its level changes, when the decoder decodes the data, the level of the data exceeds the range of the quantization level of the number of bits n. This has caused a problem in that a level inversion phenomenon of the information signal occurs.

Image file! When such a level inversion phenomenon occurs in the F-report signal, image quality deterioration occurs, such as a white spot suddenly appearing in a black area on the 111th screen, for example.

The purpose of the present invention is to solve the problems of the prior art described above,
It is an object of the present invention to provide an encoder that can perform encoding without causing the level inversion phenomenon of information signals during decoding.

[Means for solving problems]

In order to achieve the above object, the present invention provides calculation means for calculating predetermined predicted values of bits an corresponding to at least some of the inputted sample values; The difference between the value and the corresponding sample value is calculated, and If! a first calculation means for obtaining a difference value of 1; a first compression conversion means for compressing and converting the first difference value to obtain a first value of the number of bits mo smaller than the number of bits; a second compression conversion means for compressing and converting the difference line of 1 to obtain a second m having m bits; an extension converter that respectively extends and converts the value of l and the second value to obtain a third value and a fourth value, respectively, with the same number of bits as the first difference value, The second compression conversion means sets, as the second value, a value such that the absolute value of the fourth value after expansion conversion by the expansion conversion means is smaller than the absolute value of the third value. At the same time, addition (or subtraction) is performed between the third value obtained by the expansion conversion means and the predicted value, and between the fourth fly and the predicted value. Do the number of bits n! I! a calculation means for wX2 that obtains a value of 5 and a 6th value, respectively, a difference between the fifth value and the sample value corresponding to the predicted value, and a difference between the value of A6 and the sample value; a third calculation means for obtaining a second difference value and a third difference value, respectively; and a comparison means for comparing the absolute value of the @2 difference value and the absolute value of the third difference value. and, as a result of the comparison by the comparison means, if the absolute value of the second difference value is smaller than the absolute value of the third difference value, the first difference value obtained in the first compression conversion means is The value of 1 is output as an encoded value, and the absolute value of the second difference value is the third value.
If the absolute value of the difference line is greater than the absolute value of the difference line, the value @2 obtained in the second compression conversion means is output as an encoded value instead of the first value.

[Effect]

When decoding is performed for the fs1 signal and the @2 signal, the error between the decoded output and the sample square is usually smaller when decoding is performed using the first value.

However, if a level reversal phenomenon occurs, the first
When decoding is performed using the value of , an inversion occurs and the error of the decoded output with respect to the sample value becomes large, but when decoding is performed using one of the second values, the error does not become so large.

Therefore, if the absolute Ii of the error generated by both decodings is compared and the smaller of the comparison results is outputted between the first value and the second value, the decoded output at the time of decoding will be the number of bits. The level does not exceed the range of the quantization level of n, and it is possible to prevent the level inversion phenomenon from occurring.

In the present invention, the second difference value corresponds to an error generated by decoding the first wax, and the third difference value corresponds to an error generated by decoding the second value.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 (
1) and (2) are explanatory diagrams for explaining the operation of FIG. 1, respectively. In addition, in FIG. 2, the horizontal axis indicates time.

Hereinafter, the encoder t, ml! in this embodiment will be described. The following description assumes that the encoder 3 is used as the encoder 3 of the digital VTR shown in FIG.

In FIG. 1, 15 is an input terminal for an n-bit digital signal output from the A/D converter 2 in FIG. As shown in FIG. 2 (1), in the A/D converter 2, the image signal V input from the terminal 1 is sampled sequentially at every period τ, and is converted into an n-bit digital signal Ai according to each sample value. converted. Here, in this embodiment, the number of quantization bits n is set to n-7, which is a value that allows quantization errors to be ignored when handling image signals.

The predicted value B from the delay circuit 18 (FIG. 2(2)b) is subtracted from the 7-bit digital signal A (FIG. 2(2)a) inputted from the input terminal 15 by the subtracter 16.

Due to the conversion characteristics shown in FIG. 7, the predicted value B from the delay circuit 18 is the transmission signal! (4 bits) The output of the expansion ROM 32 expanded to an 8-bit value and the output signal B of one pixel before from the delay circuit 18 are added in an adder 17, and the 7-bit value from the adder 17 is Output signal D (Figure 2 (2)
d)? The delay circuit 18 increases the time τ for one pixel interval tlL.
This is a signal delayed by 1 sample, and corresponds to the decoding basket one sample before the input digital signal. Therefore, the output signal C of the subtracter 16 (FIG. 2 (2) C) is a difference signal between the digital signal A and the decoder one sample before the digital signal A. Since this output difference signal C is a difference between 7-bit signals, its number of bits is 8 bits. This 8-bit difference signal C is converted into signals E and E compressed to 4 bits by the compression ROMI 9 and the compression ROM 24, respectively.

In the compression ROM 19, the 8-bit output signal C of the subtracter 16 is converted into a 4-bit signal E ((2)e in FIG. 2) according to the conversion characteristics shown in FIG. 11!7.

As an example, if the difference signal C is +77, the seventh
As shown in the figure, a 4-bit signal E corresponding to 6 is output from the compression ROM 19. The output signal E of the compression ROM 19 converted to 4 bits is supplied to one input of the data selector 30 and is also input to the expansion ROM 20.

On the other hand, the compression ROM 24 has a subtracter 16 as its input.
8-bit signal Ct-1 [4-bit signal E (second
Figure C2) e). In an example similar to the above, when the output C of the subtracter 16 is +77, the 4-bit signal B corresponding to 5 is one step smaller than the output 6 of the compression ROM 19, and when it is -128, the 4-bit signal B is -8. A 4-bit signal E corresponding to -7, which is one step smaller in absolute value, is output. Compression ROM converted to 4 bits
The output signal of 24 is supplied to the other input of the data selector 30 and is also input to the expansion ROM 25.

By the way, in general, when does the above-mentioned level inversion phenomenon occur, the difference signal C is
When compressed by M19 and then expanded by expansion ROM 41 of the decoder shown in FIG. is at least possible to occur.

Therefore, in this embodiment, the compression converter 0M24 is used to compress and convert the difference signal C1 into the signal E which is one step lower as described above. The absolute value of the obtained difference signal C is prevented from becoming larger than the original difference signal C.

That is, when decoded, the signal E obtained from the compression ROM 24 is lower than the signal E obtained from the compression ROM 0M19.
Decoded output (digital signal A shown in Figure 6) and original value (
That is, although the error with the digital signal A) may become large, at least the level inversion phenomenon will not occur.

Next, the expansion ROM 20 is equivalent to the expansion ROM used in the decoder 12 (the expansion ROM 41 in FIG. 6), and receives the 4-bit signal E from the compression ROMx 9 as #! The 8-bit expanded signal d(
Figure 2 (2) C) Perform K conversion. As in the example above, 4
If the bit signal E is 6, +7 as shown in Figure 7.
If the negative value corresponds to 7, and if the value is 4, a value corresponding to +31 is output as the 8-bit signal C. In this way, the output signal C of the ROM 20 is compressed into an 8-bit differential signal Ct-a bit, which is the output of the subtracter 16, and again
The signal is expanded to bits.

The expansion ROM 25 is exactly the same as the expansion ROM 20, and the 4-bit signal E from the compression ROM 24 is expanded into an 8-bit signal C (FIG. 2 (2) C) using the conversion characteristics shown in FIG. ◎In the same example as above, when the 4-bit signal E is 5, the value corresponding to +52 is as shown in Figure 7, and when it is -7, the value corresponding to -77 is 8. The output signal C of the decompression ROM 20 and the output signal C of the decompression ROM 25, which are expanded to 8 bits, are outputted as a bit signal C, respectively, by the adder 2.
1 and the predicted value B from the delay circuit 18 used to obtain the difference signal C in the subtraction a16 by the adder 26 to obtain a 7-bit output. By that,
As is clear from a comparison with the configuration of the decoder shown in Figure #f6, the output of the adder 21 is obtained when the signal B from the compression BOM 19 is input to the decoder shown in Figure #f6. It is the same as the decoded output, and is also the same as the decoded output obtained when the output line of addition 1$26 and the signal E from the compression ROM 24 are also input to the decoder.

Therefore, below, the output from the adder 21 is used as the temporary decoded signal F(
(2) f) in FIG. 2, and the temporary decoded signal F (FIG. 2 (2) f') which is the output from the adder 26.

Therefore, we will examine the errors between these provisional decoded signals P and F and the input digital signal person.Normally, the difference between the provisional decoded signal F and the digital signal person should be smaller than that of the temporary decoded signal F, but as mentioned above, When a level inversion phenomenon occurs, since the polarity is inverted during decoding, the error between the decoded output, that is, the provisional decoded signal F, and the digital signal person will naturally become very large. However, the temporary decoded signal F
As mentioned above, since the level reversal phenomenon does not occur, the error with the digital signal person, which also causes polarity reversal, is due to the level reversal! It never becomes larger than that of the decoded signal F.

Therefore, by comparing the errors between the provisional decoded signals F, F and the input digital signal, the level inversion phenomenon can be detected.

Therefore, these temporary decoded signals F and F are subtracted from the input digital signal A by the subtracter 22 and the subtracter 27, respectively, and the error signal G (Fig. 2 (2) g) and the error signal G (1 step below) are obtained. 2 (2) g) is determined as 0. Then, the absolute values of these error signals G and G#-1 are determined by absolute value converters 23 and 28, respectively, and input to a comparator 29.

The output of the comparator 29 is input to the select terminal of the data selector 30, and when the absolute value of the error signal G is larger than the absolute value of the error signal G one step below, the data selector 30 is input to the output of the compression ROM 24. Switch to the 4-bit compressed signal E side whose absolute value is one step smaller, and conversely, if the absolute value of the error signal G which is one step lower is larger,
Switch to the 4-bit compression signal E side from the compression ROM 19. The output from the data selector 30 is the output terminal 30t.
- is output as a transmission signal I.

For example, if the 7-bit input digital signal A is 131→6
2→25→lO→35..., the 8-bit difference signal C output from the subtracter 16 changes from -31→9.
It changes as 3→-21→-19→23... Therefore, the 4-bit compression difference signal E of the compression ROM 19 becomes -5→7→-4→-4→4..., and on the other hand,
The 4-bit output signal E of the compression ROM 24 is -4→6→-
3→-3→3...

Then, the output C of the expansion ROM 20 is -31→110→
-17→-17→31・・・・・・ Also, RO for expansion
The output C of M25 is -17→77→-8→-8→17...
. . . Furthermore, a 7-bit provisional decoded signal 1. is obtained by adding these signals and the predicted value B which is the output of the delay circuit 18. That is, the output F of the adder 21 is -31→-48→29→12
→43..., and the output F of the adder 26 is -1
It changes like 7 → 46 → 38 → 21 → 29... Therefore, the error value between these temporary decoded values F and F and the input digital signal, that is, the output G of the subtracter 22 is 0.
-+110→-4→-2→-8..., subtractor 2
The output G of 7 is -14→16→-13→-11→6...
...becomes... Based on the output of the comparator 29, which compares the absolute values of the output G of the subtracter 220 and the output G of the subtracter 270, the data selector 30 selects B-+E.
-4E → E → B... The output crab (Fig. 2 (2) i) is -5 → 6 → -4 → -4 → 3...
A 4-bit signal of . . . is selected and output from the output terminal 31.

In this way, in this embodiment, the value (F--48) at the time of temporary decoding causes a level inversion, like the second data (A 62. C-93, E-7) in the above example. In this case, since the 4-bit compressed signal t-E is switched to E (E-s) and output, it is possible to prevent level inversion during decoding. Also,
The fifth data in the above example (A-35, C-23, g-
Even if the level inversion does not occur as in 4), even if the difference value is on the boundary of the quantization step, E with less decoding error can be used.
◎ The above is an explanation of the operation of the encoder shown in FIG.

In this way, the output obtained by encoding with the encoder shown in FIG.
f: Written to the memory 5 as data compressed to 4 bits/II elements. Thereafter, the data written in the memory 5 is read out via the PCM processor 4, and recorded on the magnetic head 19 by the magnetic head 8 via the modulator 6 and recording amplifier 7.

During reproduction, a signal is reproduced from the magnetic tape 9 by the magnetic head 8, and the signal is reproduced by the reproduction equalizer 10 and the demodulator 1.
After being appropriately reproduced and equalized and demodulated by PCM processor 4 and memory 5f:

The signal is supplied to the decoder 12 as a signal equivalent to the output from the encoder 3 described above. Note that the decoder 12 used here
is similar to the decoder using the conventional predictive coding method shown in Figure 6.

FIG. 2(3) is an explanatory diagram for explaining the operation of the decoder shown in FIG. 6.

The signal (1) from the PCM processor 4 inputted from the input terminal 40 ((3) 1 in FIG. 2) is 4-bit compressed data, which is converted into 8-bit data by the decompression ROM 41 according to the conversion characteristics shown in FIG. Expanded data C (Figure 2 (3) C
) is converted to For example, as shown in Figure 7, when the 4-bit signal is data corresponding to 6, 31 (M[
The 8-bit data corresponding to the signal C value is used as R for expansion.
Output from OM41. The predicted value K ((3) k in FIG. 2) from the delay circuit 43 is added to the signal C expanded to 8 bits by the expansion ROM 41 by the adder 42. The predicted value of the delay circuit 43 is a signal obtained by delaying the output signal of the adder 42 by the delay circuit 43 by a time τ equal to one pixel interval.

Therefore, the output of the adder 42 is the predicted fJMK and the difference gkC
The decoded data A'(
(3) a) in Fig. 2, and is output to the terminal 44 as a 7-bit/pixel signal ◇ As described above, in this embodiment, during recording, the compressed difference signal, the signal with the smaller one-step absolute value, and the K Then, the level inversion phenomenon that occurs when the compressed difference signal is decoded is detected based on the size of the error between both temporary decoding signals and the input signal, and when level inversion occurs,
Instead of the compressed difference signal, the absolute monkey transmits a signal that is one step smaller.

This can prevent level inversion of the image signal from occurring during reproduction.

Next, FIG. 3 is a block diagram showing another embodiment of the present invention.

In the embodiment of FIG. 1, the 4-bit compressed difference signal E
The compression ROM 19 and the compression ROM 24 for obtaining the signal E''Ik with a small absolute value of 1 step are used in parallel, but as in the embodiment shown in FIG. R for compressing the desired ROM24
It may be used in series with the OM 19, inputting a large 4-bit compressed difference signal Ef, and outputting a 4-bit signal Ei whose absolute value is one step smaller than this. In this case, the ROM capacity j1 can be reduced.

In addition, in the embodiments of FIGS. 1 and 3, the expansion RO
M20 and expansion ROM 25, adder 21 and adder 26,
Since the subtracter 22 and the subtracter 27, and the absolute value converter 23 and the absolute value converter 28 are each the same circuit, it is also possible to make them all one-plane paths and use them in a time-sharing manner.

In the embodiments described above, the present invention is fully applied to a magnetic recording/reproducing apparatus such as a digital VTR, but the present invention is not limited to this, and may be applied to any information signal other than an ail image signal, such as an audio signal. It can also be applied to recording/reproducing or transmitting via any transmission medium. In addition, although the above embodiments have shown the case of the previous value predictive encoding method, the present invention is not limited to this, but generally applies to the N-order curve edge predictive encoding method, and furthermore, to the case where the difference between the predicted value or the reference value is calculated. It is clear that the present invention can also be applied to other differential encoding methods that perform bit compression and encoding.

Furthermore, depending on the characteristics of the transmission path, so-called weighted mapping may be applied to the 4-bit compressed difference data that is the transmission signal. In the above example, the 4-bit compressed difference data is 7, 6, 5, 4, in descending order of the 8-bit decompressed data.
,3,2,1,0°-1,-2,-3,-4,-5,-
6, -7, -8, but with weighted mapping, for example, 0, 1
゜2.4,7,3,6,5. -6. -7. -4. -8
, -5, -3, -2, -1 (assuming that the value after decompression is O at 50 o'clock). Therefore,
In the above example, 5 is used as the l step lower value for the 4-bit compression difference value 6, but this weighted!
In the tubbing, a value of 2 is used as the value one step lower than the 4-bit compression difference wi1. The present invention is also applicable to cases where weighted mapping is performed in this manner.

In addition, in the above-mentioned embodiment, the ROM was used to obtain the value one step lower than the 4-bit compression difference official recognition, but if weighted mapping as described above is not performed, the polarity of the difference value -l or + by subtractor or adder depending on
It is also possible to obtain fii of 1.

[Effects of the Invention] As described above, according to the present invention, information can be transmitted without causing the level reversal phenomenon of the information signal, which was the case in the old days of PCM, so that it can be used in magnetic recording and reproducing devices such as digital VTRs. is effective in preventing image quality deterioration.

Furthermore, even if level inversion does not occur, compressed data with a smaller quantization error after decoding is selected for difference values near the boundaries of each quantization step, so the overall quantization error is reduced. It has a mitigating effect.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of the present invention, FIG.
Figure 4 is a block diagram showing another embodiment of the present invention, Figure Wg4 is a block diagram showing the configuration of a general digital VTR to which the encoder is applied, Figure 5 is a block diagram showing a conventional encoder, and Figure 6 is a block diagram showing a conventional encoder. The figure is a block diagram showing general decoding, FIG. 7 is a graph showing the conversion characteristics of compression ROM and expansion ROM, FIG. 7A is an explanatory diagram for explaining how to view the conversion characteristics of FIG. FIG. 8 is an explanatory diagram for explaining the correspondence between decimal representation and binary representation of a 7-bit digital value. Code explanation 3...Encoder, 12...Decoder, 16
,22゜27.51...Subtractor, 17,21,
26,42゜54... Adder, 29...
・Comparator, 30... Data selector, 18, 4
3,55°°°゛°°delay circuit 119.24,52...
...Compression ROM, 20.25. Agent Patent Attorney Akira Namiki Husband 2 Zuken 5WJ 16WJ Wi7 Zuutai TA Suman 8 Diagram [1 Fukangen] [2 Naishi Gen J+65 -
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Claims (1)

[Claims] 1. An encoder that inputs a sample value of n bits obtained by sampling and quantizing an analog information signal, encodes it into a value of m less than n bits, and outputs the encoded value, Calculation means for calculating a predetermined predicted value of the number of bits n corresponding to at least some of the inputted sample values, and calculating a difference between the predicted value and the corresponding sample value. , a first calculation means for obtaining a first difference value, a first compression conversion means for compressing and converting the first difference value to obtain a first value of m bits, and the first difference value. a second compression converting means for compressing and converting to obtain a second value having m bits, and decompressing and converting each of the first value and the second value to obtain a second value equivalent to the first difference value. 3rd number of bits
and a decompression conversion means for respectively obtaining a value of
Compression conversion is performed to obtain a value such that the absolute value of the fourth value after the expansion conversion by the expansion conversion means is smaller than the absolute value of the third value, and Addition (or subtraction) is performed between the third value and the predicted value, and between the fourth value and the predicted value, to obtain a fifth value and a sixth value of the number of bits n. a second arithmetic means for obtaining each, and a fifth arithmetic means for
and a difference between the sample value corresponding to the predicted value, and a difference between the sixth value and the sample value, and obtain a second difference value and a third difference value, respectively. and a comparison means for comparing the absolute value of the second difference value and the absolute value of the third difference value, and as a result of the comparison by the comparison means, the second difference value If the absolute value of is smaller than the absolute value of the third difference value, the first value obtained in the first compression conversion means is output as an encoded value, and If the absolute value is larger than the absolute value of the third difference value, the second value obtained in the second compression conversion means is output as an encoded value instead of the first value. An encoder characterized by: 2. In the encoder according to claim 1, the second compression conversion means has the same polarity as the first value obtained in the first compression conversion means as the second value. , an encoder characterized in that compression conversion is performed to obtain a value of m bits whose absolute value is at least one step lower.