JPS60209852A - Chip for evaluation of microcomputer - Google Patents

Abstract

PURPOSE:To evaluate exactly a timer processing program by inhibiting counting- up of a timer if a break function, a step function, or the like is executed while a chip for evaluation is used to evaluate a program. CONSTITUTION:While the program to be evaluated is executed, contents of a program counter 7 are impressed to an instruction register 5 from external terminals PM0-PM11 through external terminals IM0-IM7 and are executed. If an instruction which transfers data in a RAM8 to an accumulator 10 is executed independently of instructions of the program to be evaluated, an external terminal AC/PC is set to ''0'', and an external terminal RAPC is set to ''1''. In this case, the data transfer instruction is impressed to external terminals IM0-IM7. Since a control signal TSTP is outputted from an output mode control circuit 15, counting-up of a timer counter 12 is not performed by execution of the instruction, and deviation from the actual timer counted value is prevented.

Description

[Detailed Description of the Invention] (a) Industrial Application Field The present invention is an evaluation tool created for developing a program to be stored in a built-in ROM or examining its operation when manufacturing a one-chip microcomputer. Regarding chips.

(b) Prior art In general, a one-chip microcomputer with a built-in ROM and RAM operates by itself based on a program stored in the ROM, but the program is not stored in the ROM during the manufacture of the one-chip microcomviator. Done with a mask.

That is, when one-chip micro combinators are mass-produced, the same program is written to all of the mass-produced products. Therefore, programs cannot be easily rewritten or changed, and sufficient consideration is required when creating a program. Therefore, an evaluation chip was created that has the same functions as a mass-produced one-chip microcomputer, but operates according to instructions given from the outside, and this evaluation chip is used for program development and examination. will be carried out.

This evaluation chip has a terminal for outputting the contents of the program counter to the outside, and a terminal for presetting the instruction code to the instruction register from the outside.
By externally connecting an EP-ROM or the like that stores the program to be evaluated to these terminals, the operation according to the program is performed, but in order to evaluate the program, it is necessary to stop the execution of the program. A break function and a step function to execute one instruction of the program during the break state are provided. The break function is a function that stops program execution by applying a signal at a predetermined level to the break input terminal, and holds the program counter at the address of the next instruction. Each time a pulse of a predetermined level is applied to the step input terminal, the program is executed one step (
This function executes only one instruction (one instruction), and by using the break function and step function, it is possible to take out the internal state of the evaluation chip to the outside and evaluate whether the program is being executed correctly.

On the other hand, in the case of a microcomputer with a built-in timer counter, when the timer is set by a program, the timer is incremented each time an instruction is executed. Of course, in the evaluation chip corresponding to this microcomputer, addition is made to the timer every time an instruction is executed, and especially when the step function is executed during the break state mentioned above, - Execution of the instruction causes an addition to the timer. This is stated in page 16, page 3 of the "Microcomputer Data Series NO3LM649.9 Manual" published by the applicant on February 15, 1980.
．． It is described in Section 2.

However, when evaluating the program using an evaluation chip,
If you want to check the data by outputting or changing the data in the internal RAM, use the break function and step function to write instructions different from the measurement program. For example, data can be retrieved or changed by applying a data transfer command, store command, etc. from the outside and having it executed.However, since the command is executed using this step step function, the timer addition As a result, the timer value deviates from the value counted by the actual program execution. Therefore, it was not possible to strictly evaluate the timer.

(C) Purpose of the Invention The present invention has been made in view of the above-mentioned points, and it is possible to prevent the timer from adding when an instruction different from that of the program being evaluated is executed during program evaluation. The present invention provides an evaluation chip that enables strict evaluation of a timer by ensuring that the value of time does not deviate from the actual value.

B) Structure of the Invention The present invention provides a break function that stops execution of instructions based on a signal applied to a break input terminal in order to develop or evaluate a program written in a ROMK built into a one-chip microcomputer. In an evaluation chip having a step function that executes one instruction according to a signal applied to a step input terminal during the break function, the contents of a program counter or a plurality of registers are switched and outputted to a plurality of output terminals. An output mode in which the switching circuit is controlled by a signal applied to a plurality of input terminals, and a signal is output to stop the counting operation of the timer circuit when a predetermined signal is applied to the plurality of input terminals. A control circuit is provided, and the counting operation of the timer circuit can be stopped when a program or instructions other than the program to be evaluated is executed.

(E) Embodiment FIG. 1 is a block diagram of an evaluation chip showing an embodiment of the present invention. The evaluation chip, like a one-chip microcomputer for mass production, has an input/output circuit (11 2+(3
) (41, an instruction register (5) that stores an instruction code to be executed, and an instruction decoder (6) that decodes the instruction code stored in the instruction register (5) and controls each part to execute the instruction. , a program counter (7) for specifying the address of a program in order to execute the program sequentially, a RAM (8) for storing data, and a RAM (8) for storing data.
RAM address register (RA
MAD) (91), Akinimulator (AC) (10+) for temporary storage of the booter, 5ALUQ11 for calculation, kill timer counter 02 controlled by the program, and 8-bit bus Q31 for data transfer between each circuit. However, it is not equipped with a ROM for storing programs like that provided in mass-produced one-chip microcomputers.Instead, it is equipped with a program counter (7
) External terminals PMO to PMI where each bit output is output
I and external terminals IMO to IM that can externally apply an instruction code to the instruction register (5).
7 and 'C are provided, and external terminals PMO-PMI 1
By connecting an EP-ROM (not shown) in which a program to be evaluated is written in advance to the external terminals IMO to IM7, the evaluation chip can be operated. Furthermore, external terminals PMO to PMll
C&! In addition to the output of each bit of the program counter (7), the output of each bit of the akimulator (IUI or RAM address register (9)) can be switched and outputted by a switching circuit (14). Accordingly, the contents of the Akinimulator 00) and the RAM address register (9) can be retrieved.

Which output is selected by the switching circuit I is controlled by an output mode control circuit Q51 to which external terminals AC/PC and RAPC are applied.
Control signal CHG selects the output depending on the combination of signals applied to APC.

For example, both external terminals A C/P C and RAPC are 0.
As soon as " is applied, the output of the program counter (7) is selected, and the external terminals AC/PC&C"'1", RA
When "0" is applied to the PC, K is the akini mulator 0.
0) is selected, and when '1' is applied to both external terminals AC/PC and RAPC, the output of the RAM address register (9) is selected and the output from external terminals PMO to
Output to PMII. On the other hand, external terminal AC/PCK"
0'' and 1'' is applied to RAPC, the output mode control circuit Q51 controls the switching circuit (141) to select the output of the program counter (7) and outputs the control signal TSTP.Control signal TSTP is a signal for inhibiting the counting operation of the timer counter (12), and is applied to the timer control circuit (16).

On the other hand, the break function and step function are controlled by a break/step control circuit (17) to which a break terminal BREAK and a step terminal 5TEP are connected. Break step control circuit (17) &i, pv-
When a force is applied to the BREAKK'''1'' terminal, an inhibit signal INH is applied to the program counter (7) and the instruction decoder (6), and after the instruction being executed is completed, the program counter (7) is The contents are held at the next address, and the instruction code is prohibited from being applied from the instruction register (5) to the instruction decoder (6) to stop the execution of the instruction. Then, while applying the break terminal BREAKK ``1'' to the break state, connect the step terminal 5TB.
When a pulse of PK'''1'' is applied, the inhibition signal INH is temporarily released, so the operation of the program counter (7) and instruction decoder (6) is restarted, and the instruction stored in the instruction register (5) is The command is executed by being applied to the decoder (6), but after executing the - command, the inhibit signal INH is applied again.
is output and a break state occurs.

Further, from the break step control circuit (L7), when 1'' is applied to the break terminal BREAK to enter the break state, a control signal BRK is output to the timer control circuit (L61). In the state where the control signal BRK is applied, that is, in the break state, the external terminal AC/PC is set to 0" and the RAPC is set to 1".
In addition, when the control signal TSTP is output from the output mode control circuit (15), the timer counter (1
The timer counter 02) is controlled by outputting a signal TINH for inhibiting the addition operation of 21.

EP-R using the evaluation chip configured as shown in Figure 1.
The operation in a break state when evaluating a program stored in an OM or the like will be explained using the timing diagram shown in FIG. While the program to be evaluated is being executed, the contents of the program counter (7) are output from the external terminals PMO-PMII, and the instruction at the address specified by the contents is output from the external terminal I.
Instruction register (5
) is applied and executed. Therefore, break terminal BRE
When AKK ``1'' is applied, execution of the program is stopped by the inhibition signal INH while the contents of the program counter (7) specifying the next address are output from the external terminals PMO-PMI 1. In this state, step terminal 5
When a pulse of TEPK “l” is applied, the external terminal PMO
The instructions are read out using the address signals output from PMII and preset in the instruction register (5) via external terminals IMO to IM7. - When the instruction is executed, the break state again occurs, but at this time, if a timer is installed, "1" is added to the count value t of the timer counter (121) before the - instruction is executed. Similarly, further step terminal 5
When the pulse of TEPVc"1" is applied, the command at the next address is executed, and the count value of the timer counter Q21 becomes t+2. When checking the contents of the accumulator (10) in this state, use the external terminal AC/P.
When CK "l" is applied, the switching circuit α4) is controlled by the output mode control circuit 0□□□, and the external terminals PMO to P
The contents of the accumulator are output to MII. Also, if external terminal RAPCK''1'' is applied while external terminal AC/PC is set to '1', external terminal PMO-P
The contents of the RAM address register (9) are switched and output to MI 1, and the contents are checked.

On the other hand, in the above-mentioned state, it is also possible to take out and check the data stored in the RAM (8). That is,
1if1FllIIn addition to the program instructions, I
t A M (Data in 81 is stored in the accumulator (1
01 to execute the instruction to be transferred. In this case, set the external terminals AC/PC to 0" and RAPC to "1", and then output the contents of the program counter (7) to the external terminals PMO to PMII) and to the external terminals IMO to M7. Switch to the bond value subbegi program command, apply the data transfer command, and in this state, step terminal 5TEPK"
A pulse of 1' is applied. As a result, the transfer command is executed and the data in the RAM (81) is transferred to the accumulator (
However, at this time, since the control signal S 'It' P is output from the output mode control circuit α9, no addition is made to the timer counter 02 due to the execution of the command, and the timer counter 02 is not added. The numerical value remains t+2. Next, by setting the external terminal AC/PC to 1" and setting ILAPC to O", the data transferred to the accumulator uUl is output to the external terminals PMO to PMII.

Then, both external terminals AC/PC and RAPC are set to '0''.
', apply the next instruction of the program to be evaluated to the external terminal, and apply a pulse of '1'' to the step terminal 5TEP, the - instruction is executed as described above, and at this time, the timer counter ( "1" is added to 12, and the counted value becomes t+3.

In this way, when executing an instruction different from the program to be evaluated, the timer control circuit (1G+
Since this prohibits the counting operation of the timer counter a2, there is no deviation from the timer count value in the actual program.

(f) Effects of the Invention As described above, according to the present invention, it is possible to strictly evaluate a timer processing program, and therefore it has the advantage of preventing mistakes and malfunctions when creating a timer processing program.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing the operation of the embodiment shown in FIG. (11+2) (31(4)...input/output circuit, (5)
...Instruction register% (6)...Instruction decoder, (7)...Program counter, (8)...RAM. +91...RAM address register, (10)...
Akinimulator, ■...ALLI, UJ...Timer counter, (13)...Bus, I...Switching circuit, Q9...Output mode system Applicant Sanyo Electric Co., Ltd. and one other representative Patent Attorney Masao Sano Figure 1

Claims (1)

[Claims] 1. RO built into one-chip microcomputer
In order to develop or evaluate the program written in M, there is a break function that stops the execution of instructions based on a signal applied to the break input terminal, and a signal applied to the Stellaf' input terminal during the break function. In an evaluation chip having a step function for executing one command, a switching circuit that switches and outputs the contents of a program counter or a plurality of registers to a plurality of output terminals;
When the switching circuit is controlled by signals applied to a plurality of input terminals, output mode control outputs No. 48 that stops the counting operation of the timer circuit when sufficient signals are applied to the plurality of input terminals. A chip for evaluating a microcomputer, characterized in that the counting operation of the timer circuit described in @11 can be stopped when a block diagram or instructions other than the program to be evaluated is executed.