JPS6343559Y2 - - Google Patents

Description

[Detailed description of the invention] (a) Industrial application field This invention is an evaluation tool created to develop a program to be stored in the built-in ROM or to examine its operation when manufacturing a one-chip microcomputer. Regarding chips.

(b) Prior art In general, a one-chip microcomputer with a built-in ROM and RAM operates by itself according to a program stored in the ROM.
Programs are stored in the ROM using a mask when the one-chip microcomputer is manufactured. That is, when one-chip microcomputers are mass-produced, the same program is written into all of the mass-produced products. Therefore, programs cannot be easily rewritten or changed, and sufficient consideration is required when creating a program. Therefore, an evaluation chip was created that has the same functions as a mass-produced one-chip microcomputer, but operates according to commands given from the outside, and this evaluation chip is used to develop and study programs. It will be done.

This evaluation chip has a terminal for outputting the contents of the program counter to the outside, and a terminal for presetting the instruction code from the outside into the instruction register, and an EP-ROM that stores the program to be evaluated. Operation according to the program is performed by externally connecting to the terminal of A step function for executing the command is provided. The break function holds the program counter at the address of the next instruction and stops program execution when a signal of a predetermined level is applied to the break input terminal. This function executes only one step (one instruction) of the program each time a pulse of a predetermined level is applied to the step input terminal, and uses the break function and step function to extract the internal state of the evaluation chip to the outside. It is possible to evaluate whether the program is running correctly.

On the other hand, in mass-produced one-chip microcomputers, write-only registers are provided when data only needs to be written but does not need to be read. For example, the control register CTL shown on pages 2 and 12 of page 19 of "Microcomputer Material Series No. 8 LC6500 Series User's Manual" published by the applicant on August 20, 1981 is a write-only register. This control register
The CTL is a register that controls interrupts and input/output switching of the input/output common port, and data is written by executing a set instruction and a reset instruction, and each bit output is used as a control signal. Similarly, a plurality of timer counters are provided, and registers that control the operation modes of these timer counters are also configured as write-only registers.

A write-only register is also provided in the evaluation chip of a one-chip microcomputer that has such a write-only register, but the contents of the write-only register cannot be retrieved externally when creating or evaluating a program. Therefore, it is inconvenient to evaluate processing programs related to write-only registers, and the disadvantage is that they are difficult to use.

(c) Purpose of the invention The present invention was made in view of the above points, and provides an output circuit between the output of the write-only register and the bus so that the contents of the write-only register can be retrieved to the outside during program evaluation. The purpose is to configure.

(d) Structure of the invention The invention provides a break function that stops the execution of instructions based on a signal applied to a break terminal in order to develop or evaluate a program written to a ROM built into a one-chip microcomputer. In an evaluation chip having a step function that executes one instruction according to a signal applied to a step terminal during the break function, the contents of a program counter or a plurality of registers are switched to a plurality of output terminals. A switching circuit that outputs an output, an output mode control circuit that controls the switching circuit based on a signal applied to a predetermined input terminal, and a write-only register whose data cannot be read in a mass-produced one-chip microcomputer. the output circuit is controlled by a signal output during the break function and a signal output when a data transfer instruction is executed by the step function; The configuration is such that the data can be read by transferring the output of the data via the output circuit to one of a plurality of registers whose output is connected to the switching circuit.

(E) Embodiment FIG. 1 is a block diagram of an evaluation chip showing an embodiment of the present invention. The evaluation chip has input/output circuits 1 and 2 that input and output data through A port, B port, C port, and D port, each consisting of 8-bit external terminals, similar to a one-chip microcomputer for mass production. , 3, 4, an instruction register 5 that stores the instruction code to be executed, and an instruction decoder 6 that decodes the instruction code stored in the instruction register 5 and controls each part to execute the instruction.
and a program counter 7 for specifying the address of the program in order to execute the program sequentially.
RAM 8 that stores data, RAM address register 9 that specifies the address of RAM 8, accumulator 10 that temporarily stores data, ALU 11 that performs calculations, timer circuit 12 that can be controlled by a program, and operation of timer circuit 12. Timer mode selection register 13 that controls the mode
and an 8-bit bus 14 for data transfer between various circuits, but it is not equipped with a ROM for storing programs as is provided in mass-produced one-chip microcomputers. Instead, external terminals PM0 to PM11 to which each bit output of the program counter 7 is output, and external terminals IM0 to IM7 to which an instruction code can be externally applied to the instruction register 5 are provided. By connecting an EP-ROM (not shown) in which a program to be evaluated is written in advance to terminals PM0 to PM11 and external terminals IM0 to IM7, it is now possible to operate the evaluation chip. There is. Furthermore, external terminal
In addition to each bit output of the program counter 7, each bit output of the accumulator 10 or the RAM address register 9 can be switched and outputted to PM0 to PM11 by a switching circuit 15. That is, the contents of the accumulator 10 and the RAM address register 9 can be taken out as necessary. Which output is selected by the switching circuit 15 is determined by the external terminal AC/
It is controlled by the output mode control circuit 16 to which PC and RAPC are applied, and external terminals AC/PC and
Depending on the combination of signals applied to RAPC,
Control signal CHG selects the output. For example, when "0" is applied to both external terminals AC/PC and RAPC, the output of the program counter 7 is selected, "1" is applied to external terminals AC/PC, and "0" is applied to RAPC.
is applied, the output of the accumulator 10 is selected, and the external terminals AC/PC and
When “1” is applied to both RAPC, the output of RAM address register 9 is selected and output to the external terminal.
It is output to PM0 to PM11.

On the other hand, the break function and step function are controlled by a break/step control circuit 17 to which a break terminal BREAK and a step terminal STEP are connected. Break step control circuit 1
7 applies an inhibit signal INH to the program counter 7 and instruction decoder 6 when "1" is applied to the break terminal BREAK, and after the instruction being executed at that time is completed, the contents of the program counter 7 are is held at the next address, and application of the instruction code from the instruction register 5 to the instruction decoder 6 is prohibited to stop execution of the instruction. Furthermore, if a pulse of "1" is applied to the step terminal STEP while the break state is maintained by applying "1" to the break terminal BREAK, the inhibit signal INH is temporarily released, so the program counter 7 and instruction The operation of decoder 6 is resumed,
The instruction stored in the instruction register 5 is applied to the instruction decoder 6,
The instruction is executed, but after one instruction is executed, the inhibition signal INH is output again and a break state is entered.
Also, from the break step control circuit 16,
When the break state occurs, the control signal BRK is output,
It is applied to the output circuit 18.

The timer circuit 12 consists of a prescaler that counts each time one instruction is executed, and two timer counters that count the output of the prescaler.
The operating mode of the timer circuit 12 is controlled by each bit output of the timer mode selection register 13. In a mass-produced microcomputer, this timer mode selection register 13 is connected to the bus 14.
This is a write-only register in which data sent to the timer mode selection register 13 is written, but in the evaluation chip, each bit output of the timer mode selection register 13 is applied to the output circuit 18, and is controlled by the break step control circuit 17 when in the break state. While the signal BRK is being output, the transfer command is executed by the step function and the instruction decoder 6
When the control signal REGTB is output from the timer mode selection register 13, the contents of the timer mode selection register 13 are sent from the output circuit 18 to the bus 14.

FIG. 2 is a circuit diagram of the timer mode selection register 13 and output circuit 18 shown in FIG. In FIG. 2, the timer mode selection register 13
consists of six latch circuits 19 and a NOR gate 20, the input L of the latch circuit 19 is connected to each bit B0 to B5 of the bus 14, and the input φ is
The output of the NOR gate 20 is applied, and the output of the latch circuit 19 is the control signal PR0, PR1, PR2,
The signals are output to the timer circuit 12 as TMOM, TMIM0, and TMIM1. The inputs of the NOR gate 20 include the system clock CP4B that controls the operation of the computer and the timer mode selection register 1.
When a preset instruction for presetting data in 3 is executed, the control signal BTREG output from the instruction decoder 6 and the timer mode selection register 1 attached to the instruction code are output from the instruction decoder 6.
A control signal PB made from a code indicating 3 is applied. That is, the control signal is
At the timing when BTREG and PB become “0” and system clock CP4B becomes “0”, bus 1
The data sent to the lower 5 bits B0 to B5 of 4 is taken into the latch circuit 19. Latch circuit 1
The output of 9, the control signal PR0, switches the frequency counted by one timer counter of the timer circuit 12, and the control signal TMOM is a signal that selects whether or not one timer counter repeatedly counts the preset value. becomes. Also, the control signal PR
1 and PR2 select the frequency counted by the other timer counter depending on their combination, and control signals TMIM0 and TMIM1 become signals for switching the operation mode of the other timer counter depending on their combination.

On the other hand, the output circuit 18 has six NAND gates 2
1, a NOR gate 22, and a NAND gate 23, the output Q of the latch circuit 19 is applied to one input of the NAND gate 21, the output of the NOR gate 22 is applied to the other input, and the output are connected to bits B0-B5 of bus 14, respectively. Furthermore, the system clock CP3B, a signal PB created by a code that specifies the timer mode selection register 13 attached to the instruction code, and the output of the NAND gate 23 are applied to the input of the NOR gate 22.
The break mode shown in Figure 1 is in the break state.
Control signal output from step control circuit 17
BRK and a control signal REGTB output from the instruction decoder 6 when a data transfer command is executed are applied. That is, when "1" is applied to the break terminal BERAK to enter the break state, the control signal BRK becomes "1", and in this state, for example, the instruction code for transferring data to the accumulator 10 is set to the timer mode selection register 13.
An instruction code with a code that specifies the external terminal
Instruction register 5 from IM0 to IM7
When a pulse of “1” is applied to the step terminal STEP, this transfer command is executed and the output REGTB of the instruction decoder 6 becomes “1”.
Therefore, the control signal PB becomes "0". Then,
Since the output of the NOR gate 22 becomes "1" at the timing when the system clock CP3B becomes "0", each output of the latch circuit 19 is
1 to the bus 14. The data sent to the bus 14 is then sent to the accumulator 10.
Therefore, by applying "1" to the external terminal AC/PC and "0" to RAPC shown in FIG. 1, the switching circuit 15 selects the output of the accumulator 10. Therefore, the external terminal PM
Timer mode selection register 1 from 0 to PM11
The contents of 3 are extracted.

(f) Effects of the invention As described above, according to the invention, when it is desired to check the contents of a write-only register during program evaluation, a data transfer instruction can be used with the break function and a data transfer instruction instead of the instruction of the program to be evaluated. By executing the program using the step function and switching the register that stores the transferred data using the switching circuit, the contents of the write-only register can be retrieved externally, making it easy to evaluate programs related to the write-only register and making it easier to use. It has the advantage of being an easy program evaluation chip.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a logic circuit diagram of some blocks shown in FIG. 1, 2, 3, 4...Input/output circuit, 5...Instruction register, 6...Instruction decoder, 7...Program counter, 8...
RAM, 9...RAM address register, 10...
...Acumulator, 11...ALU, 12...
Timer circuit, 13... Timer mode selection register, 14... Bus, 15... Switching circuit, 16...
...Output mode control circuit, 17...Break step control circuit, 18...Output circuit.

Claims (1)

[Scope of utility model registration request] Built-in one-chip microcomputer
In order to develop or evaluate a program written to ROM, there is a break function that stops execution of instructions based on a signal applied to a break terminal, and a break function that stops execution of instructions based on a signal applied to a step terminal during the break function. An evaluation chip that has a step function for executing instructions includes a switching circuit that switches and outputs the contents of a program counter or multiple registers to multiple output terminals, and a switching circuit that outputs the contents of a program counter or multiple registers based on a signal applied to a predetermined input terminal. An output mode control circuit for controlling the switching circuit, and an output circuit provided in a write-only register whose data cannot be read by a mass-produced one-chip microcomputer, and outputting the output circuit during the break function. and a signal output when a data transfer command is executed by the step function, and outputs the contents of the write-only register via the output circuit, the output of which is connected to the switching circuit. A microcomputer evaluation chip characterized by being readable by transferring data to one of a plurality of registers.