JPH06105433B2 - Chip for evaluation of micro computer - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention is for evaluation, which was created to develop a program to be stored in a built-in ROM or to examine its operation when manufacturing a one-chip microcomputer. Regarding chips.

(B) Conventional Technology Generally, a one-chip microcomputer having a built-in ROM and RAM operates by itself according to a program stored in the ROM. However, storing the program in the ROM is a mask at the time of manufacturing the one-chip microcomputer. Done by That is, when mass-producing one-chip microcomputers, the same program is written in all mass-produced products. Therefore, the program cannot be easily rewritten or changed, and sufficient consideration is required when creating the program. Therefore, an evaluation chip, which has the same function as a mass-produced one-chip microcomputer, but whose operation is performed by an instruction given from the outside, is created, and the development and examination of programs are performed using this evaluation chip. .

This evaluation chip has a terminal for outputting the contents of the program counter to the outside, and a terminal for presetting an instruction code in the instruction register from the outside,
By externally connecting an EP-ROM that stores the program to be evaluated to these terminals, the operation according to the program is performed.
A break function for stopping the execution of the program and a step function for executing one instruction of the program during the break state are provided. The break function is a function to hold the program counter at the address of the next instruction and stop the execution of the program when a signal of a predetermined level is applied to the break input terminal.
In the break state, this is a function to execute the program for one step (one instruction) each time a pulse of a predetermined level is applied to the step input terminal. The internal state of the evaluation chip is evaluated by using the break function and the step function. Can be taken out to evaluate whether or not the program is executed correctly.

On the other hand, in the case of a microcomputer having a built-in timer counter, when the timer is set by the program, the instruction is incremented each time one instruction is executed. Of course, also in the evaluation chip corresponding to this microcomputer, addition to the timer is made every time an instruction is executed, and especially when the step function is executed during the break state described above, Execution of one instruction causes addition to the timer. This was 1980
Published by the applicant of this application on March 15th
NO3LM6499 Manual ", page 16, page 3, item 3.

However, while the program is being evaluated using the evaluation chip, the data in the internal RAM can be output to the outside,
Or, if you want to change or check the data,
By using the break function and the step function, an instruction different from the program to be evaluated, such as a data transfer instruction or a store instruction, is applied from the outside and the instruction is executed, so that data can be taken out or changed. However, at this time, since the instruction is executed by the step function, the timer is added, so that the value of the timer counted by the actual execution of the program deviates. Therefore, a strict evaluation of the timer was not possible.

(C) Object of the invention The present invention has been made in view of the above-mentioned points, and prohibits addition of the timer when the instruction different from the program being evaluated is executed in the middle of the program evaluation. The evaluation chip is capable of performing a strict evaluation of the timer by ensuring that the value of does not deviate from the actual value.

(D) Configuration of the Invention The present invention is a break for stopping the execution of an instruction based on a signal applied to a break input terminal in order to develop or evaluate a program written in a ROM incorporated in a one-chip microcomputer. 1 depending on the function and the signal applied to the step input terminal during the break function.
In an evaluation chip having a step function for executing instructions, a switching circuit for switching and outputting the contents of a program counter or a plurality of registers to a plurality of output terminals, and the switching by a signal applied to a plurality of input terminals. An output mode control circuit for controlling the circuit and outputting a signal for stopping the counting operation of the timer circuit when a predetermined signal is applied to the plurality of input terminals, and a program different from the program to be evaluated or When the instruction is executed, the counting operation of the timer circuit can be stopped.

(E) Example FIG. 1 is a block diagram of an evaluation chip showing an example of the present invention. The evaluation chip, like the mass-produced one-chip microcomputer, is an input / output circuit (1) for inputting / outputting data via the A port, the B port, the C port, and the D port, each of which has an 8-bit external terminal. (2)
(3) and (4), an instruction register (5) that stores an instruction code to be executed, and an instruction decoder (that decodes the instruction code stored in the instruction register (5) and controls each unit to execute the instruction ( 6) and a program counter (7) for designating the address of the program for sequentially executing the program
A RAM (8) for storing data, a RAM address register (RAMAD) (9) for specifying an address of the RAM (8),
Accumulator (AC) for temporarily storing data (10)
It is equipped with an ALU (11) that performs calculations, a timer counter (12) that can be controlled by a program, and an 8-bit bus (13) that transfers data between circuits. There is no ROM for storing programs such as those provided in a computer. Instead, external terminals PM0 to PM11 to which each bit output of the program counter (7) is output, and external terminals IM0 to IM7 to which an instruction code can be externally applied to the instruction register (5) are provided. , External terminals PM0 to P
The evaluation chip can be operated by connecting an EP-ROM (not shown) in which a program to be evaluated is written in advance to M11 and the external terminals IM0 to IM7. Further, in addition to the bit output of the program counter (7), each bit output of the accumulator (10) or the RAM address register (9) can be switched and output to the external terminals PM0 to PM11 by the switching circuit (14). Has become. That is, the contents of the accumulator (10) and the RAM address register (9) can be taken out as needed. Which output is selected by the switching circuit (14) is controlled by the output mode control circuit (15) to which the external terminals AC / PC and RAPC are applied, and the combination of signals applied to the external terminals AC / PC and RAPC. The control signal CHG selects the output according to. For example, when “0” is applied to both external terminals AC / PC and RAPC, the output of the program counter (7) is selected, and when “1” is applied to external terminal AC / PC and “0” is applied to RAPC,
When the output of the accumulator (10) is selected and when "1" is applied to both the external terminals AC / PC and RAPC, the output of the RAM address register (9) is selected and the external terminal PM0
~ Output to PM11. On the other hand, the external terminal AC / PC is "0", RAP
When “1” is applied to C, the output mode control circuit (1
5) controls the switching circuit (14) to select the output of the program counter (7) and outputs the control signal TSTP. The control signal TSTP is a signal for prohibiting the counting operation of the timer counter (12) and is applied to the timer control circuit (16).

On the other hand, the break and step functions are
It is controlled by a break step control circuit (17) to which BREAK and a step terminal STEP are connected. When "1" is applied to the break terminal BREAK, the break step control circuit (17) applies the inhibit signal INH to the program counter (7) and the instruction decoder (6) so that the instruction being executed at that time is executed. After the end, the contents of the program counter (7) are held at the next address, and the instruction code is prohibited from being applied to the instruction decoder (6) from the instruction register (5) to stop the execution of the instruction. . If "1" is applied to the break terminal BREAK in a break state and a pulse of "1" is applied to the step terminal STEP, the inhibit signal INH is temporarily released. Therefore, the program counter (7) and the instruction The operation of the decoder (6) is restarted, the instruction stored in the instruction register (5) is applied to the instruction decoder (6) and the instruction is executed, but after executing one instruction, the inhibit signal INH is output again. And breaks.

The break step control circuit (17) outputs a control signal BRK to the timer control circuit (16) when "1" is applied to the break terminal BREAK to enter the break state. Therefore, the timer control circuit (16)
When the control signal TSTP is output from the output mode control circuit (15) by setting the external terminal AC / PC to “0” and RAPC to “1” in the state where BRK is applied, that is, in the break state. , The signal TINH which prohibits the addition operation of the timer counter (12) is output to control the timer counter (12).

EP-ROM using the evaluation chip configured as shown in FIG.
The operation in the break state in the case of evaluating the program stored in etc. will be described with reference to the timing chart of FIG. While the program to be evaluated is being executed, the contents of the program counter (7) are output from the external terminals PM0 to PM11, and the instruction at the address specified by the contents is transferred to the instruction register (5) via the external terminals IM0 to IM7. Applied and executed. Therefore, when "1" is applied to the break terminal BREAK, the prohibition signal INH stops the execution of the program while the contents of the program counter (7) designating the next address are output from the external terminals PM0 to PM11. In this state, applying a "1" pulse to the step terminal STEP,
The instruction read out by the address signal output from the external terminals PM0 to PM11 and preset in the instruction register (5) via the external terminals IM0 to IM7 is executed. When one instruction is executed, the break state occurs again. At this time, if the timer is set, "1" is added to the count value t of the timer counter (12) before the execution of one instruction. To be done. Similarly, further step terminal ST
When a pulse of "1" is applied to EP, the instruction at the next address is executed, and the count value of the timer counter (12) becomes t + 2. To check the contents of the accumulator (10) in this state, apply "1" to the external terminal AC / PC, and the output mode control circuit (15) will switch the switching circuit (14).
Is controlled, and the contents of the accumulator (10) are output to the external terminals PM0 to PM11. If "1" is applied to the external terminal RAPC with the external terminal AC / PC set to "1", the contents of the RAM address register (9) are switched and output to the external terminals PM0 to PM11, and the contents are confirmed. Is done.

On the other hand, in the above-mentioned state, it is also possible to take out and confirm the data stored in the RAM (8). That is, an instruction to transfer the data in the RAM (8) to the accumulator (10) is executed separately from the instruction of the program to be evaluated. In this case, the external terminals AC / PC should be set to "0" and RAPC set to "1" (at this time, the external terminals PM0 to PM11 output the contents of the program counter (7)) and the external terminals IM0 to IM7 should be evaluated. By switching to the program command, the data transfer command is applied, and in this state, the "1" pulse is applied to the step terminal STEP. This causes the transfer instruction to be executed and RAM
The data of (8) is transferred to the accumulator (10). At this time, since the control signal TSTP is output from the output mode control circuit (15), execution of the instruction causes the timer counter (12). Is not added and the count value remains t + 2. Next, set the external terminal AC / PC to "1".
By setting RAPC to “0”, the external pins PM0 to PM1
The data transferred to the accumulator (10) is output to 1. Then, when both the external terminals AC / PC and RAPC are set to "0", the next command of the program to be evaluated is applied to the external terminals, and the pulse of "1" is applied to the step terminal STEP, as described above, The instruction is executed, this time
"1" is added to the timer counter (12), and the count value becomes t + 3.

In this way, when an instruction different from the program to be evaluated is executed, the timer control circuit (16) sets the timer counter (12) by setting the external terminal AC / PC to “0” and RAPC to “1”. Since the counting operation of 1) is prohibited, there is no deviation from the timer count value in the actual program.

(F) Effects of the Invention As described above, according to the present invention, it is possible to perform a strict evaluation of a timer processing program, and thus there is an advantage that errors and malfunctions at the time of creating a timer processing program can be prevented.

[Brief description of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention, and FIG. 2 is a timing diagram showing an operation of the embodiment shown in FIG. (1) (2) (3) (4) …… I / O circuit, (5) ……
Instruction register, (6) ... Instruction decoder, (7) ... Program counter,
(8) …… RAM, (9) …… RAM address register, (1
0) …… Accumulator, (11) …… ALU, (12) ……
Timer counter, (13) …… bus, (14) …… switching circuit, (15) …… output mode control circuit, (16) …… timer control circuit, (17) …… break step control circuit.

Claims (1)

[Claims] 1. A microcomputer which operates based on the program data stored in an external storage device in order to develop or evaluate the program data to be written in a ROM incorporated in a mass-produced one-chip microcomputer. In the evaluation chip, a break input terminal to which a break signal for stopping the execution of the instruction corresponding to the program data is applied, and only one instruction execution when the execution of the instruction corresponding to the program data is stopped And a step input terminal to which a step signal for restarting the step is applied, and a program counter for identifying the state of the break signal and the step signal and accessing at least the external storage device when the break signal is generated. And an instrument for decoding the program data in the external storage device. And a break step control circuit for stopping the operation of the operation decoder and restarting the operations of the program counter and the instruction decoder by only one instruction when the step signal is generated, and applying the contents of the program counter and the plurality of registers. A switching circuit, a timer circuit that performs a counting operation each time an instruction corresponding to the program data is executed, and a plurality of control signals for controlling the switching operation of the switching circuit and the counting operation of the timer circuit. The plurality of input terminals to be applied and the states of the plurality of control signals are identified, and the contents of either the program counter or the plurality of registers are output from the plurality of output terminals via the switching circuit, A control circuit that stops the counting operation of the timer circuit, and before evaluation When the instruction corresponding to another program data from the program data is executed, the evaluation chip microcomputer is characterized in that to enable stopping the counting operation of the timer circuit.