JPS5832407B2 - sequence controller - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a sequence controller with a function of monitoring input/output elements, and its purpose is to perform input/output without using advanced equipment such as a computer and without requiring a special monitoring program. The objective is to provide a sequence controller that monitors elements.

With the development of sequence controllers that utilize computer technology, it has become possible to quickly and reliably discover faults in controlled objects using this sequence controller as an intermediary.

However, since a high-end computer is used, there are problems in that the equipment is not only expensive and expensive, but also requires a special program for monitoring.

The present invention was proposed in view of such problems, and by setting the start point memory address and end point memory address of the section to be monitored on the sequence control program, the control data read from the section can be specified. Store the on/off signal states of input/output elements in an auxiliary storage device;
Moreover, since the signal state is stored only during one scan of the sequence control program, it is possible to monitor a series of related signal states within a specific section after an abnormality occurs, and also to monitor the signal state. There is no need for any special program.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram showing a schematic configuration of the entire sequence controller, where 1 is a main memory circuit such as a core memory that stores sequence control data of sequence cycles programmed in advance, and 2 is a memory address of the main memory circuit 1. A program counter that sequentially reads specified control data; 3 is a memory data register that stores the control data read from the memory address specified by the program counter 2; 4 is a control stored in the memory data register 3; This is an instruction register in which data is set via the data bus DB, and a memory gate that controls setting of the control data to the instruction register 4.

The instruction word used as the control data is composed of an operation section that indicates the type of instruction, and an address section that specifies an address such as an address of an internal input/output element, a memory address of the main memory circuit 1, etc., which will be described later.

The types of instructions include on-off from internal input/output elements.
There are input/output test instructions that perform logical operations on OFF input signals, output instructions that turn on and off output elements among internal input/output elements based on the results of logical operations, and jump instructions that cause jumps based on the results of logical operations. .

Table 1 shows the types of command words and their meanings.

6 is an instruction decoder which decodes the operation part of the control data set in the instruction register 4 and issues various command signals.

Reference numeral 10 indicates an external input element 10a1, such as a limit switch or a push button switch, which is turned on and off by checking the operation of each operating element of the controlled device such as a machine tool, and an external input element 10a1 that instructs the operation of each operating element of the controlled device. On-
This is an external input/output element group consisting of external output elements 10b such as output relays and solenoids that are turned off.

Reference numeral 11 indicates a large number of internal input elements 11a1 which are paired with each external input element 10a, and which convert the OR, t operation state of the external input element 10a into an input signal in the form of an electrical signal at an internal level of the sequence controller, and each external output. element 10
A large number of output elements that form a pair with b and turn on and off the external output element 10b in response to an internal level output signal, and other output elements that do not directly exchange signals with the external input/output element group 10 but transmit internal level output signals. This is an internal input/output element group consisting of a large number of internal output elements 11b such as timer elements, relay elements, dummy elements, etc. that operate in response to the input signal.

Reference numeral 12 denotes an internal input/output element 11a at an address specified by the control data from among the internal input/output element group 11.

Input selector 12a1 output selector 1 to select 11b
2b, and the on/off state of the selected internal input/output elements 11a, 11b is determined by an input signal of +Hn when on and L'' when off.
The output signal sent from the output terminal of the input selector 12a onto the line IT, and especially if the control data is an output command, the output signal sent from the test flag circuit 14 via the line OT is the internal output element selected by the output selector 12b. 1 l
b.

The test flag circuit 14 receives various command signals decoded by the instruction decoder 6, and if the command signals are input/output test commands, the test flag circuit 14 receives various command signals from the internal input/output elements 11a and Ilb input via the line IT. testing whether the on-off input signal satisfies a test command condition, that is, performing a logical operation and storing the result;
If the command signal is an output command, an on-off output signal based on the stored test result is sent to the line OT.

15 is a control pulse generation circuit that generates clock pulses and control pulses for timing the execution of each instruction, etc.;
In this embodiment, as shown in FIG. 3, lock pulse CL, control pulse OP, and control pulses CL1 to CL6 are generated periodically, and the - command is executed after CL6 is issued after this control pulse OP is issued. It is supposed to be held in one cycle up to the end.

16 is a control circuit for the main memory circuit 1; 17 is a gate at a memory address specified by the program counter 2; 18 is a save register that stores the memory address of the program counter 2 when a jump instruction is given; 19-23 is a gate that is opened and closed by the control pulse to execute a predetermined command.

FIG. 2 shows an example of a sequence control program.

In this sequence control program, memory address 1
The control data of 00 to 1.gamma.7 (octal notation) is programmed to execute the starting circuit shown as an example of the sequence circuit in FIG.

80 is a starting point address setting circuit for setting the starting point memory address of the sequence control program to be monitored;
90 is an end point address setting circuit for setting the end point memory address of the sequence control program to be monitored;
100 is a monitoring circuit that monitors internal input/output elements specified by control data programmed between the memory address set in the start address setting circuit 80 and the memory address set in the end address connection circuit 90; , these details are shown in FIG.

In the starting point address setting circuit 80 of FIG.
1-n is the contact of the digital switch that sets the memory address, and the contact 81-1 is used to set the memory address in octal notation.
-81-n are divided into groups of eight, and each group has a receiver corresponding to each digit of the octal number.

82 is a conversion circuit that converts the octal value set at the contacts 81-1 to 81-n of the digital switch to a binary value;
The signals generated in the inverters 83-1 to 83-8 respectively
3-n.

In the end address setting circuit 90, 91-1 to 91-n are also contacts of digital switches for setting memory addresses, and contacts 91-1 to 91-n are used to set memory addresses in octal notation.
n is divided into groups of eight, and each group has a receiver corresponding to each digit of the octal number.

92 is a conversion circuit that converts the octal value set at the contacts 91-1 to 91-n of the digital switch to a binary value; The signals sent to each inverter 93-1 to 93-n
It is now input via the .

In the monitoring circuit 100, 101 is a comparator that compares the numerical value of the program counter 2 and the setting value of the starting point address setting circuit 80, and outputs a coincidence signal of H'' when the two numerical values match. The output of the conversion circuit 82 of the setting circuit 80 is input.

102 is a comparator that compares the value of the program counter 2 and the setting value of the end point address setting circuit 90 and outputs a match signal of H'' when the two values match; 92 outputs are input.

Reference numerals 104 to 106 denote a push button switch for successive counter clearing, a push button switch for successive counter addition, and a push button switch for external command to start monitoring.

107, the T terminal input is from 'H' (high level potential).
When changing to "L" (low level potential), if the J terminal input is H", it is set and the Q terminal output is H", and if the K terminal input is "H", it is reset to J-. In the flip-flop, the clock pulse CL is input to the T terminal, and the Q of the D flip-flop 110, which will be described later, is input to the J terminal.
The terminal output, the output (coincidence signal) of the comparator 101, and the control pulse CL2 are inputted via the AND gate 108, and the output (coincidence signal) of the comparator 102 and the control pulse CL5 are inputted to the K terminal via the AND gate 109. It is now input via the .

110 is unconditionally set when the S terminal input becomes 11 L 11, and the Q terminal output becomes "H" and the Q terminal output becomes "L".
Then, when the T terminal input changes from “L” to “H”, D
If the terminal input is L', the D flip-flop is reset, the S terminal receives the monitoring start external command signal generated by the push button switch 106, and the T terminal receives the signal from the JK flip-flop 107. The Q terminal output is input via impark 111.

112 is a light emitting diode for displaying a monitoring start command that lights up when the flip-flop 110 is set;
The Q terminal output of the flip-flop 110 is connected to the inverter 11.
It is designed to be input via 3.

115 becomes +1 when a pulse is input to the addition terminal UP.
When a pulse is input to the clear terminal CL, the counter is cleared and its contents become 0.The clear pulse signal generated by the push button switch 104 is input to the clear terminal CL, and the flip-flop 110 is input to the addition terminal UP. The 6-terminal output of the flip-flops 107 and the addition pulse signal generated by the pushbutton switch 105 are inputted via the AND gate 116 and the OR gate 117, and the Q terminal output of the flip-flops 107 and 110 and the control pulse C
The outputs of L6 and an inverter 127, which will be described later, are inputted via an analog gate 4118 and the OR gate 117.

A memory address display 119 externally displays the contents of the sequential counter 115, and the contents of the sequential counter 115 are inputted thereto.

120 is an input/output test instruction TNA of control data decoded by the instruction decoder 6;

Internal input/output elements 11a specified by control data set in the instruction register 4 by TFA, TNO, TPO, THE, and TFE.

11b and determines the on-off state of internal input/output element 1.
This circuit 120 is an input/output test circuit that outputs a signal of TH+1 as a test result if the on-off state of ia, 1 lb satisfies the conditions of the input/output test command, and outputs a signal of "L" if it does not satisfy the conditions of the input/output test command. The constituent Ant-game H21 has an internal input/output element 11a sent out on the line IT.
, 1ib are input, and the input/output test commands TNA, TNO, TNE are input to the OR gate 122.
The on-off signals of the internal input/output elements 11a and 11b are inputted to the AND gate 123 via the inverter 124, and the input/output test command T
FA, TPO, and TFE are input via ORG-4125.

The output of both ant gates N21 and 123 is the or gate 1
26 and is input to an inverter 127.

Reference numeral 130 denotes a memory circuit that stores the addresses of internal input/output elements 11a and 11b that do not satisfy the conditions of the input/output test command when the flip-flop 107 is set to J-.

In this embodiment, when the input to the read/write instruction terminal R/W is L91, the numerical data input to the data input terminal Din is written to the memory address specified by the address designation signal input to the memory number value input terminal ADD. , when the input to the reading instruction terminal R/W is H'', the numerical data written in the memory address specified by the address designation signal input to the memory address input terminal ADD is output to the terminal Dout.
A memory circuit such as a core memory that outputs to Pulse C
L4 and the output of the inverter 127 are ant-game.
131 and an inverter 132, and the instruction register 4 is input to the data input terminal Din.
The address part of the control data set in
It is designed to be input via D.

Reference numeral 134 denotes a display device for externally displaying the storage contents of the storage circuit 130, and the output of the data output terminal Dout of the storage circuit 130 is input thereto.

Next, the operation of the sequence controller configured as described above will be explained with reference to FIGS. 2 to 4. The content of the program counter 2 is incremented by 1 by the control signal UPI generated when the control pulse CL6 is generated, and the control pulse C.L.
The gate 11 is activated by the control signal MST generated at the time of occurrence of
is opened, and the control data at the memory address specified by the program counter 2 is read out and stored in the memory data register 3.

Then, the control signal G generated when the control pulse CL3 is generated
The memory gate 5 is opened by M, and the control pulse C
The instruction register 4 is opened by the control signal 5GISR generated when L3 is generated, and the control data stored in the memory data register 3 is set in the instruction register 4.

When the control data is set in the instruction register 4 in this way, the address signal set in the address field is sent onto the line AD, and the on-off state of the internal input/output elements 11aj and 11b at the address specified by the address signal is determined. , when it is on, it is sent out as an ``H'' signal, and when it is off, it is sent out on line IT as a l L j'' signal.

The control data set in the instruction register 4 is changed every time the control pulse CL3 is generated according to the program, and therefore the address signal sent out on the line AD and the on-off signal sent out on the life IT are controlled by the control pulse. It will be updated every time CL 3 occurs.

By controlling each circuit in this manner, the sequence control program shown in FIG. 2 is executed, and the device to be controlled is sequence-controlled.

When the controlled device is sequence-controlled in this way, if an abnormality occurs in the controlled device, the operator must use the internal input/output elements 11a,
llb monitoring will be carried out.

For example, if an abnormality occurs while the controlled device is in operation, such as when the startup status indicator lamp goes out and the controlled device stops operating, the startup circuit has an abnormality, and each input/output that makes up the startup circuit Just monitor the elements.

In this invention, monitoring is performed using a sequence control program without using a special program for monitoring.

For example, in the sequence control program, control data for executing the startup circuit, that is, control data for testing the on-off state of each input/output element making up the startup circuit, is programmed in memory addresses 100 to 117.
In the case of the above abnormality, the sequence control program at memory addresses 100 to 117 is used.

The operator checks the starting point memory address 100 and ending point memory address 117 of the program that executes the starting circuit in the comparison table of the enclosure, and then switches the digital switch 81- of the starting point address setting circuit 80.
1 to 81-n to 0100, and the end point address setting circuit 9
0 digital switches 91-1 to 91-n are set to 0117.

And a push button switch 106 for external command to start monitoring.
Press.

This causes flip-flop 110 to be set.

When the flip-flop 110 is set, the light emitting diode 112 for a monitoring start command is turned on.

In addition, the contents of the sequential counter 115 are set to O by pressing the sequential counter clear push button switch 104 in advance.

Therefore, when the sequence control program is executed and the content of the program counter 2 becomes 0100, the comparator 101 outputs an H'' match signal, so the control pulse CL2
When , the J terminal input of flip-flop 107 becomes ``''.
When the clock pulse CL falls, the flip-flop 107 is set.

Then, control data TNAOOOI at memory address 100 is read out by control signal 5GISR.

As a result, the data input terminal Din of the memory circuit 130 receives numerical data 00 specifying the input/output address of the internal input/output element.
01 is input, and the test circuit 120 receives the test command TN.
A and the on-off signal of internal input/output element LS2 at input/output address 1 are input.

If the internal input/output element LS2 is on (normal), it satisfies the test conditions and the test circuit 120 outputs an "H"signal; if it is off (abnormal), the test conditions are not satisfied and the test circuit 120 outputs an "H" signal. 120 outputs an "L+1" signal.

If the output of the test circuit 120 is L'', the control pulse CL
4 occurs, the read/write instruction terminal R/W of the memory circuit 130
Since the input becomes L'', the numerical take 0001 is written to the memory address 0 specified by the sequential counter 115, and when the control pulse CL6 is generated, a pulse signal is input to the addition input terminal UP of the sequential counter 115, and the sequential counter The contents of 115 are increased by +1 to become 1.

However, if the output of the test circuit 120 is H'', neither of the analogues 1-131 and 118 is opened, so the numerical data 0001 is not written to the memory circuit 130 and the sequential counter 115 is not incremented by +1.

Next, by reading the control take TFAOOOO2 at memory address 101, numerical data 0002 is input to the data input terminal Din of the memory circuit 130, and the test command TFA and the internal input/output element at input/output address 2 are input to the test circuit 120. The on-off signal of LS3 is input.

If the internal input/output element LS2 is off (normal), the test condition is satisfied, and the test circuit 120 outputs an "H"signal; if it is on (abnormal), the test condition is not satisfied, so the test circuit 120 outputs an "H" signal. 120 outputs an ``L'' signal.

If the output of the test circuit 120 is L'', the control pulse C
When L4 occurs, the input to the reading instruction terminal R/W of the memory circuit 130 becomes L'', so numerical data 0002 is written to the memory address specified by the sequential counter 115, and the control pulse CL6 is generated to write the numerical data 0002 to the memory address specified by the sequential counter 115. A pulse signal is input to the addition input terminal UP, and the counter 1
The contents of 15 are increased by +1.

However, if the output of the test circuit 120 is "H1+", neither of the gates 1131 and 118 is opened, so the numerical data 0002 is not written to the memory circuit 130 and the sequential counter 115 is not incremented by +1.

In this way, the control data is read out sequentially, and only the input/output addresses of internal input/output elements that do not satisfy the test conditions of the input/output test command are written in order from memory address 0 of the storage circuit 130.

When the content of the program counter 2 reaches 117, the comparator 102 outputs an H'' match signal, so when the control pulse CL5 is generated, the terminal input to the flip-flop 107 becomes H'', and at the falling edge of the clock pulse CL. Flip-flop 107 is reset, thereby also resetting flip-flop 110, and light-emitting diode 112 is turned off.

Therefore, no monitoring is performed on the control data after memory address 120.

Note that even when the above monitoring is being performed, the test flag circuit 14 is operating, and the original sequence control by the sequence control program is continued.

The operator presses push button switch 1 for external command to start monitoring.
When it is confirmed that the light emitting diode 112 that was turned on by pressing 06 is turned off, the monitoring result is displayed externally.

First, the sequential counter clear push button switch 104 is pressed to set the content of the sequential counter 115 to O.

The input of the read/write instruction terminal R/W of the memory circuit 130 is H″
Therefore, when the contents of the sequential counter 115 reach 0, the numerical data stored at memory address 0, that is, the input/output address of the first internal input/output element that did not satisfy the conditions of the test instruction, becomes the data output terminal. Dout, and its input/output address is displayed on the display 134.

Next, when the push button switch 105 for sequential counter addition is pressed, the contents of the sequential counter 115 are incremented by 1 and become 1, and the input/output address of the second internal input/output element that did not satisfy the test conditions becomes the take output terminal Dout. The input/output address is displayed on the display 134.

In this way, each time the push button switch 105 for sequential counter addition is pressed, the contents of the sequential counter 115 are incremented by 1, and the input/output addresses of internal input/output elements that do not satisfy the conditions of the test command stored in the memory circuit 130 are sequentially Display 134
will be displayed.

The operator can know which internal input/output element system has an abnormality based on the input/output address displayed on the display 134.

In addition, if an abnormality occurs that causes the unit advance to be interrupted during the unit advance of the controlled device, the start point memory address and end point memory address of the program that executes the unit advance cycle circuit in the sequence control program. Starting point address setting circuit 80, ending point address setting circuit 90
to monitor each input/output element that makes up the unit advance cycle circuit.

FIG. 6 shows another embodiment of the monitoring circuit 100.

The program counter 2, starting point address setting circuit 80, and ending point address setting circuit 90 shown in FIG. 6 are exactly the same as those shown in FIG.

Further, the components of the monitoring circuit 100 shown in FIG. 6 that have the same reference numerals as those in FIG. 5 have the same functions as the components in FIG. 5.

In this FIG. 6, 140 is a flip-flop 107
This is a storage circuit that stores the addresses of internal input/output elements 11a and 11b that do not satisfy the conditions of the input/output test command when the input/output test command is in the set state.

In this embodiment, when a pulse is input to the load signal input terminal, numerical data input from the data input terminal is stored, and when a pulse is input to the reset terminal H, the numerical data is reset from a plurality of registers 140-1 to 140n. The address part of the control data is connected to the data input terminal of each register 140-1 to 140-n on the line A.
D, and the outputs of the anime game-1-141-1 to 141-n are input to the load signal input terminal.
A pulse generated by a push button switch 104 for successive counter clearing is input to the reset terminal R.

143 is a selector that decodes the content of the sequential counter 115 and selects the AND gates 141 to 141-n; when the content of the sequential counter 115 is O, the selector selects the AND gates [4];
1-1 is enabled, and when it is 1, AND gate 141-
2, . . . n-i, the anime game H41-n is enabled.

The output of the AND gate 131 is input to one input terminal of each of the AND gates N41-1 to 141n.

144 is a display circuit for externally displaying the memory contents of the memory circuit 140, and each register 1401 to 140 of the memory circuit 140
A plurality of indicators 144-1 to 144-1 to which the output of -n is input.
It is composed of 4-n.

Therefore, according to this embodiment, flip-flop 107
is set, only the input/output addresses of internal input/output elements that are tested by the input/output test circuit 120 and do not satisfy the conditions of the input/output test instruction are sequentially stored in the registers 140-1 to 141-n of the storage circuit 140. At the same time, those input/output addresses are stored in each of the display devices 144-1 to 144-1 of the display circuit 144.
144-n for external display.

According to this embodiment, unlike the embodiment shown in FIG. 5, there is no need to sequentially operate the counter addition push button switch.

In addition, the test flag circuit 14 includes an internal input/output element 1.
The on-off status of 1atllb is determined by each input/output test command T.
NA, TFA, TNO, TPO.

Since a test circuit for determining based on THE and TFE is provided, the input/output test circuit 120 is not provided in the monitoring circuit 100, and the output of the test circuit provided in the test flag circuit 14 is used. It's okay.

Furthermore, in the above embodiment, the input/output addresses of internal input/output elements that do not satisfy the conditions of the input/output test command are stored and displayed, but all determination results are displayed. Good too.

To do this, in FIG. 5, the output of the inverter 127 is not input to the AND gates 118 and 131, but the output of the inverter 127 is input to the data input terminal Din of the memory circuit 130 together with the address part of the control data. , the input/output addresses of all internal input/output elements determined by the input/output test command and the determination results may be sequentially stored in the storage circuit 130 and displayed on the display 134.

As is clear from the above description, the present invention has a starting point address setting circuit that sets a memory address of a program, an end point address setting circuit that sets a memory address of a program, and a starting point address setting circuit that sets a memory address of a program. It is equipped with a monitoring circuit that stores and displays the on/off signal state of the input/output element specified by the control data programmed up to the memory address set in the end point address setting circuit. According to the present invention, it is possible to monitor input/output elements over a certain section of memory addresses using only a sequence controller without using advanced equipment such as a computer, and moreover, it is possible to monitor input/output elements over a certain section of memory addresses without using a special program for monitoring. It can be monitored by using a control program.

In particular, since the section to be monitored is specified by a memory address, a series of signal states that are to be controlled and are closely related to each other can be captured, which has the effect of facilitating the investigation of the cause of a failure.

[Brief explanation of the drawing]

The figures show an embodiment of the present invention, and FIG. 1 is a schematic block diagram of a sequence controller according to the present invention, and FIG.
The figure is a schematic diagram of a program sheet in which a sequence control program is written, Figure 3 is a timing chart of control pulses, Figure 4 is a sequence circuit diagram, and Figure 5 is the first circuit of circuits 80, 90, and 100 in Figure 1. Embodiment Detailed Diagram FIG. 6 is a second embodiment detailed diagram of the circuits 80, 90, 100 in FIG. 1...Main memory circuit, 2...Program sheet, 4...Instruction register, 6...Instruction decoder, 10.
...External input/output element group, 11...Internal input/output element group, 12...Input/output selection circuit, 80.
...Start address setting circuit, 90...End point address setting circuit, 100...Monitoring circuit, 1
01・102・・・Comparator, 107・・・・・・
Flip-flop in J-, 110...D flip-flop, 115...Sequential counter, 12
0...Input/output test circuit, 130/140...
...Memory circuit, 134...Display device, 143
...Selector, 144...Display circuit.

Claims (1)

[Claims] 1 The sequence control program is sequentially read by a program counter that specifies a memory address, input signals from input elements specified by the read control data are taken in, logical operations are performed, and outputs specified by the read control data are obtained. In a sequence controller that sequentially controls a controlled object by giving an output signal based on the result of the logical operation to an element, a starting point address setting circuit that sets a memory address of a starting point of an interval to be monitored on the sequence control program; , an end point address setting circuit that sets a memory address of the end point of the section to be monitored, and a second point that compares the memory address specified by the program counter with the memory address set in the start point address setting circuit and outputs a match signal. a second comparator that compares a memory address specified by the program counter with a memory address set in the end point address setting circuit and outputs a match signal; and a match signal from the first comparator. set by the second
A flag circuit that is reset by the match signal of the comparator, and a signal state of an input/output element or this signal state specified by control data that is enabled in the set state of this flag circuit and read out in the interval to be monitored. and an auxiliary storage means for storing the corresponding input/output signal element number; and a display means for displaying the signal state of the input/output element stored in the auxiliary storage means or the corresponding input/output element device number together with this signal state. A sequence controller characterized by comprising: