JPS6112281B2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a sequence controller, and more specifically, operation data such as AND, OR, jump, and timer, and data specifying step conditions such as input signal status, count value, and time. This system has a built-in program memory that stores output designation data for each process step, specifying whether each of multiple output terminals is on or off, and the program advances to the next step when the step condition is met. The present invention relates to a so-called step-by-step stored program sequence controller.

Conventional sequence controllers set programs using pinboards, so
Even if a large-sized programming device is used, the number of programming steps cannot be increased to a large extent, and many digital switches must be installed in parallel for data setting.

In contrast, the present inventor has developed a step-by-step process sequence system that uses a microprocessor and memory, allows program settings to be made from the keyboard to the memory, and also scans all steps of the data storage memory at high speed. A controller has already been proposed.

An object of the present invention is to further improve the step-by-step sequence controller using the above-mentioned microprocessor and memory, and to provide a sequence controller that can process multiple steps in parallel. be.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows the configuration of a front panel according to an embodiment of the present invention. An input display 1 for displaying the input signal status with a lamp is provided at the upper left stage, and an output display 2 for displaying the output signal status using a lamp at the upper right stage. In the middle stage, step indicators 3A, 3B, and 3C are provided to display the step signals of three process counters, respectively. ), JMP (jump) RPT (repeat), NOP
An operation display 4 is provided to display the type of operation such as (no operation) with a lamp, and to the right of the operation display 4, there is a two-digit numerical display for displaying data specifying step conditions. Three data displays 5, 6, and 7 are arranged in parallel.

A function key group 8 for inputting the type of operation and a numeric input key group 9 for inputting numerical data are provided in the lower center, and a mode selection switch 10 and a power switch are provided in the lower right. A switch 11 and the like are provided. The mode selection switch 10 can arbitrarily select a program mode "P" for setting a program from the keyboard, a monitor mode "M" for monitoring the program, and a calculation mode "L" for performing calculations according to the set program. can. Also, step number displays 3A, 3B, 3C and data displays 5, 6, 7 corresponding to a plurality of process counters are provided.
The corresponding contents are displayed by switching the process channel display mode.

The contents of function key group 8 indicating the type of operation include a key "INT" indicating an interrupt command, a key "END" indicating the end of a program,
Key "NOP" indicating no operation,
The key "NOT" indicates negative logic, the key "RPT" indicates program repetition, the key "JMP" indicates program step jump, the key "CNT" indicates input pulse counting, the key "TIM" indicates timer, AND Key indicating logic "AND", 2-
The key "2AND" indicates AND logic, the key "OR" indicates OR logic, the key "2OR" indicates 2-OR logic, the key "P-SET" indicates process set, the key "OUT" indicates output, There is a key "W" that instructs writing. Furthermore, the up key "↑" and down key "↓" of the function keys are used to control the process counters 25A, 25B, 25C under the control of the central processing unit CPU in the program mode.
Add “+1” or “-1” to the arbitrary process step of
Furthermore, when a tape deck of cassette-type magnetic tape is externally connected, it has a function of controlling writing or reading thereof.

A process channel display mode selection switch 12 is provided at the lower left of the front panel, allowing selection of channel 1, 2, or 3. The input display 1, the output display 2, the operation display 4, and the data displays 5, 6, and 7 are configured to display the contents of the channel selected by the display mode selection switch 12.

FIG. 2 shows a circuit block diagram of an embodiment of the present invention. The input signals from the function key 8 and numerical input key 9 are introduced into the central processing unit CPU.
It is mainly used for creating programs in program mode. Mode selection switch 1
A 0 signal is also introduced to the CPU, and the operation of each circuit section is switched depending on the selected mode. The CPU has a built-in clock signal generator and frequency divider, which can function as a time control clock, and is used when the timer "TIM" is specified as the operation. Among the input signals introduced into the input signals I ₁ to _{I 32} , the one designated by the CPU is selected by the data selector 21 and becomes the input signal I ₀ , which is sent to the counting counters 23A, 23B, 23C or the process counter 2 via the gate circuit.
It is input to 5A, 25B, and 25C. The process counters 25A, 25B, and 25C are up-down counters that control the step of the process, and the AND gates 26A, 26B, and 26C are connected to the CPU's conditional step signals C _1A , C _1B , and C _1C when selected. _{“ + _ _}
In addition to "1", it also becomes "-1" due to the CPU's backward signal.
You can also. Counter 23A, 23
B, 23C are AND gates 22A, 22B, 22
The number of pulse signals of the input signal I ₀ is counted by C on the condition that the CPU's counting commands C _3A , C _3B , and C _3C are output, and the contents are transferred to a register in the CPU.

The memory 26 includes a CPU processing program memory 27 for storing CPU processing procedures, and a data storage memory 28 for storing predetermined data for each step of a plurality of process counters. The data storage memory 28 stores steps 1 to n related to channel 1.
A data area 28A for storing data from step 1 to step n regarding channel 2, a data area 28B for storing data from step 1 to step n regarding channel 3, and a data area 28C for storing data from step 1 to step n regarding channel 3 are provided. The type of operation, data 1 to data 3, and an output signal instructing the state of the output signal to be on or off are written in each step area.

The input display 1 displays the number of the input signal terminal selected by the data selector 21, the output display 2 displays the number of the output signal terminal designated to be output on, and the step display 3A, 3B, 3C
are step process counters 25A, 25B, 25C
Display the status of. Further, the operation display 4 and the data displays 5, 6, and 7 display the contents of the operation data, data 1, data 2, and data 3 in the data storage memory 28, respectively.
If monitor mode is selected,
Each display is configured to display the program contents of the process being monitored, regardless of the execution contents of the calculations, by the memory of the latch circuit.

FIG. 3 shows a flowchart of a portion of the CPU processing program relating to the characteristic portion of the present invention. First, at 31, the CPU reads the operation data written in, for example, channel 1, step 1 of the data storage memory 28, and selects the routine program, and then at 32 and 33, It executes the contents of the routine program and processes the output program. Next, in step 34, it is determined whether or not the contents of the operation are established, and if they are established, the process proceeds to step 35, where the process counter 25A is incremented and the next step 36 is performed.
If it is not established, skip step 35 and proceed directly to step 36. At step 36, the channel counter consisting of a ternary ring counter built into the CPU is incremented, and processing from channel 1 to channel 2 is performed.
At step 37, the content of the process counter corresponding to the state of the channel counter, that is, the program content corresponding to process 1 of the process counter of channel 2, that is, the content of channel 2, step 1, is stored by the CPU for data storage. Take in from memory 28 and return to original 31. In this way, first step 1 of channel 1 → step 1 of channel 2
→The contents of the data storage memory are loaded into the CPU one after another in the order of step 1 of channel 3, and the contents are executed, and only in the step of the channel where the step condition is satisfied, the operation corresponding to the next process is executed in the order of the step number. Data is loaded into the CPU, and the steps of channels for which the step condition is not satisfied do not change, and operation data corresponding to the same process is loaded into the CPU for each scan, and the operation data is updated for each channel. The contents of are executed. When the final step is completed, the process returns to step 1 and the scanning is repeated. The time required to scan the entire memory is at most one hundredth of a second;
On the other hand, in the case of a phenomenon to be controlled by a sequence controller, the content of the operation may be established only after several hours in the case of a long period of time, and even in the shortest case, it can be suppressed by the response speed of the relay (several tens of milliseconds). Since the control time is much longer than the computer control time, there is virtually no control error due to an increase in the number of channels. Next, an example of the operation based on the above embodiment will be described with respect to an AND or OR operation.

At process step K of process counter 25A, for example, the contents of channel 1 step K of the data storage memory indicate the operation type "AND".
"11" is written to data 1, "12" is written to data 2, and "13" is written to data 3. As output data, output number 1 is ON, 2 is ON, 3 is ON, and the remaining numbers 4 to 32 are
Assume that it is specified as OFF. Therefore, the step display 3A for channel 1 is displaying the numerical value K. Here, if the process channel display mode selection switch 12 selects the process counter 25A, the "AND" lamp lights up on the operation display 4, and the data display 5,
6 and 7 display "11", "12" and "13" respectively, output display 2 lights up the output number "1", "2" and "3" lamps, and the output terminal status is in process channel display mode. Regardless of the selection of O ₁ , O ₂ ,
_O3 is turned on.

In this state, the input signal terminals I ₁₁ ,
When the signals arrive at all the terminals I ₁₂ and I ₁₃ , the "AND" operation is established and the process counter 25A increments from K to K+1. Simultaneously with the step, each display content and input control are switched to those corresponding to the K+1 process.

In parallel with the operation "AND" in the K process of the process counter 25A described above, the operation "OR" is specified in the K process of the process counter 25B, and data 1 is "13" and data 2 is
It is assumed that "14" is written in "14" and "15" is written in data 3, and output numbers 4 and 5 are designated as ON as output data. In such a case, since the process channel display mode selection switch 12 has selected channel 1, the operation display,
Both the data display and output display are process counter 2.
Although the contents of the K process of 5A are displayed, if the process channel display mode 12 is switched to 2 channels, a display corresponding to the contents of the m process of the process counter 25B will be made. Calculations are executed regardless of the display, and output terminals O ₄ and O ₅ are turned on.

Therefore, when a signal arrives at either the input signal terminal _I13 or _I14 , the "OR" operation is established and the process counter 25B increments from the m process to the m+1 process.

In this way, by providing a plurality of process counters, each process counter can be incremented independently of each other according to the respective calculation contents, and simultaneous parallel control can be performed.

Therefore, if three mechanical devices were to be controlled by different programs, conventionally three sequence controllers and a program for communicating with each controller would be required, but according to the present invention, only one sequence controller is required. This not only makes it possible to control three mechanical devices with one sequence controller, but also eliminates the need for input/output devices for sending and receiving control signals to synchronize each device, improving control reliability. The control device is also made smaller and lighter.

Further, according to the present invention, a channel counter for controlling channels and a plurality of process counters for controlling processes for each channel are provided, and while the channel counter is incremented for each scan of the program, the increment condition is A program is set up that increments the process counter only for processes that have been established.
In addition, the operation data in the step area corresponding to the contents of the process counter is loaded from the data storage memory into the CPU and all channels are executed in parallel at high speed, making it easy to create programs using input keys. It is easy and
Programs are executed on any channel without substantial time delay.

In addition, in the above embodiment, a process counter, a counting counter, an AND circuit related to these, an OR
Although the circuit has been explained as being provided outside the CPU, this is for convenience of explanation and is normally
This is done using a circuit built into the CPU.

[Brief explanation of drawings]

FIG. 1 is a configuration diagram of the front panel of the embodiment of the present invention;
FIG. 2 is a circuit block diagram of the above embodiment, and FIG. 3 is a flowchart showing a program of the CPU of the above embodiment. 1...Input display, 2...Output display, 3A...
... Process indicator related to channel 1, 3B... Process indicator related to channel 2, 3C... Process indicator related to channel 3, 4... Operation indicator,
5, 6, 7... Data display, 12... Process channel display mode selection, 25A... Process counter related to channel 1, 25B... Process counter related to channel 2, 25C... Process counter related to channel 3, 26...Memory, 28A...
Data storage memory related to channel 1, 28B...
...Memory for data storage related to channel 2, 28C
...Memory for storing data related to channel 3.

Claims (1)

[Claims] 1. Operation data storage that stores a plurality of input signal terminals, a plurality of output signal terminals, data specifying the type of operation, step conditions, and output command data for each process step. function keys and numerical input keys for writing operation types, data values, etc. into the operation data storage memory;
In a sequence controller that is equipped with a central processing unit (CPU) and in which the program advances to the next step when step conditions are met, a channel counter consisting of a ring counter corresponding to the number of channels and a process step for each plurality of channels are used. In addition to providing a plurality of process counters for counting, the operation data is written to the operation data storage memory for each process step of the plurality of channels, and the CPU processing program memory is written for each scan. a command word that increments the channel counter, and increments the content of the process counter related to the channel when the content of the operation is established, and
A command word that does not increment the contents of the process counter related to that channel when the contents of the operation are not established, and operation data corresponding to the state of the process counter related to that channel are extracted from the data storage memory. Instruction words are written to be read into the CPU and executed, and each of the process counters is controlled independently of each other in synchronization with the scanning of the operation data storage memory. A sequence controller characterized by: 2. The method according to claim 1, wherein the time required for one scan of the CPU processing program memory is set shorter than the phenomenon time (several tens of milliseconds to several hours) of the object to be controlled by the sequence controller. sequence controller.