JP2526894B2 - Programmable controller arithmetic unit - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an arithmetic unit of a programmable controller capable of achieving a high arithmetic speed.

<< Outline of the Invention >> According to the present invention, a plurality of user program memories are provided corresponding to each divided area when the virtual ladder diagram space of M rows × N columns is equally divided into a plurality, and each user program memory is provided with a user. When each unit ladder diagram on the ladder diagram corresponding to the specifications is expanded in the virtual ladder diagram space, each circuit element information that should exist in the divided area is sequentially stored, and each circuit is stored from the plurality of user program memories. Element information is read in parallel at the same time, and logical operations for one unit ladder diagram specified by the read circuit element information are collectively processed. << Prior art and its problems >> Conventional ladder The arithmetic unit of the figure input type programmable controller is generally configured as follows.

That is, the ladder diagram corresponding to the control specification of the user is converted into a predetermined command word string and stored in one user program memory. This instruction word is composed of an operation code such as LD, AND, OR, OUT and an operand which is an I / O number.

When executing a user instruction, each instruction word is sequentially read from the user program memory and sequentially processed by a 1-bit pool arithmetic unit composed of a microprocessor. The calculation result by the instrument is written to the corresponding output area of the I / O data memory.

In order to increase the operation speed in such an operation device, a dedicated hardware circuit is adopted as a 1-bit Boolean operation unit, or a high-speed readable element is adopted as a user program memory. Is being done.

However, such a measure for increasing the operation speed still depends on the basic configuration of sequentially reading out the instruction word sequence forming the user program word by word and processing it by the 1-bit Boolean operation unit. There is a limit to speeding up by changing the design, and adoption of a high speed element has a problem that temperature rise and power consumption increase.

<< Object of the Invention >> An object of the present invention is to realize a programmable programmable controller capable of achieving a high operation speed without depending on a high-speed element.
It is to provide an arithmetic unit for a controller.

<< Structure and Effect of the Invention >> In order to achieve the above object, the arithmetic unit of the programmable controller according to the present invention corresponds to each divided area when the virtual ladder diagram space of M rows × N columns is divided into N columns. Circuit element information that should be present in the divided area when the unit ladder diagrams on the ladder diagram corresponding to user specifications are expanded in the virtual ladder diagram space are stored in sequence. A plurality of user program memories, a program reading means for simultaneously reading in parallel each circuit element information from the user program memory in the previous N rows, and a logical operation for each column of N rows by the read circuit element information. An arithmetic circuit capable of collectively performing parallel processing and simultaneously performing a logical connection for one unit ladder diagram by cascade-connecting each of the parallel-processed N columns. Characterized in that it.

With such a configuration, the user program is divided into N columns as it is in the ladder diagram and distributed and stored in a plurality of memories, while the arithmetic circuit is configured so that the user programs are simultaneously read in parallel from the N columns of the user program memory. The logical operations are collectively performed in parallel for each of the N columns by the circuit element information obtained, and the parallel operations of the N columns are performed in a cascade connection to collectively perform the logical operations for one unit ladder diagram. Since it is possible to process the data, it is possible to dramatically improve the operation speed as compared with the conventional device without adopting a memory element or the like capable of high-speed operation.

<< Description of Embodiments >> FIG. 1 is a hardware block diagram showing an embodiment of an arithmetic unit according to the present invention.

As is well known, the basic operation required for a programmable controller is a program write operation for writing a user program created by a predetermined key operation in a user program memory, and I / O for input data input from the outside.
Input update operation to write to O data memory, while reading each instruction word from user program memory sequentially, perform specified logical operation on specified input / output data, and output final operation result to I / O data memory A logical operation that writes to the area, an applied operation that performs processing equivalent to a timer or a counter, an output update operation that sends the output data of the I / O data memory that has been rewritten by executing all instructions to the outside, is specified. Read the input / output data from the I / O data memory, overlay this on the user program, and
There are monitor operations displayed on the screen etc. and other various system service operations.

Of these operations, the range covered by the arithmetic unit shown in FIG. 1 is mainly a logical operation operation, and other operations are executed by a general-purpose microprocessor (hereinafter referred to as MPU) as before.

First, the configuration of the arithmetic unit shown in FIG. 1 will be schematically described for each circuit element.

This arithmetic unit has five user program memories 11 to
15,4 I / O data memories 21-24, 4 instruction decoders 31
~ 34,4 conditional translation circuits 41 ~ 44, 4 column-unit arithmetic circuits 51
~ 54, 3 inter-column arithmetic circuits 61 ~ 63, timing generation circuit 70
And a program counter 80.

Each of these circuit elements is the timing generation circuit 70.
Are controlled by timing signals T _{1 to} T ₄ , step signal STEP, processing reset signal RST, and write timing signal WT.

The details of each timing signal will be described later with reference to FIG.

The user program memories 11 to 15 store user programs for each column of the ladder diagram, as will be described later.
The address bus terminals are address bus switches AS11 to AS15.
The connection can be switched between the program counter 80 side and the MPU bus side via.

Further, the data bus terminals of each user program memory 11 to 15 are switch-connected to the instruction decoders 31 to 34 and the I / O data memories 21 to 24 side and the MPU bus side via the data bus switching devices DS11 to DS15. Has been made possible.

Therefore, address bus switching units AS11-A can be controlled by the MPU.
If both S15 and data bus switchers DS11 to DS15 are switched to the MPU bus side, each user program memory 1
1 to 15 can be individually accessed, and program write operation, monitor operation, etc. are performed using this.

In addition, the address bus switch AS11-AS15 is switched to the program counter 80 side, and the data bus switch DS
11 to DS15 for instruction decoders 31 to 34 and I / O data memory 21
To 24 side, the respective user program memories 11 to 15 are simultaneously accessed by the output of the program counter 80 to read the instruction words stored in the respective memories in parallel, and the instruction words 31 to 34 and I / O Data memories 21 to 24 can be supplied.

Next, the I / O data memories 21 to 24 store the states of the external input terminals in association with each I / O number, and the address bus terminals are stored by the user via the address bus switchers AS21 to AS24. The program memories 11 to 15 side and the user program memory 15 in the fifth column can be switched and connected to the data bus and MPU bus sides.

The data bus terminals of the respective I / O data memories 21-24 are connected to the condition translation circuits 41-44 and the output side of the column unit arithmetic circuit 54 of the fourth column and MP via the data bus switches DS21-DS24.
Switching connection is possible with the U bus side.

Therefore, if both the address bus switches AS21-AS24 and the data bus switches DS21-DS24 are switched to the MPU bus side, M
The I / O data memories 21 to 24 can be accessed from the PU bus side, and the input update operation, the output update operation, the monitor operation, etc. are performed using this.

Also, while connecting the address bus switcher AS21-AS24 to the lower digit of the data bus of the user program memories 11-14,
If the data bus switches DS21 to DS24 are connected to the conditional translation circuits 41 to 44, the I / O data memories 21 to 2 will be operated by the operands of the instruction words read from the user program memories 11 to 15.
4 can be accessed and the read input / output data (on / off data) can be given to the condition translation circuits 41 to 44.

Further, each of the address bus switching units AS21 to AS24 responds to the operation code "OUT" being read from the user program memory 15 in the fifth column, and in response to reading the operation code "OUT" from the user program memories 11 to 15 in the fifth column user program memory 15. The condition translation circuits 41 to 44 are switched in response to the operation code “OUT” being read from the fifth column user program memory 15 in the same manner as for the data bus switches DS21 to DS24 while switching to the operand data line side. From the side to the output side of the fourth-row row unit arithmetic circuit 54.

Therefore, in response to the operation code “OUT” being read from the fifth column user program memory 15, each I / O data memory 21 is accessed by the operand read from the fifth column user program memory 15, and the access The output data of the fourth-column-column arithmetic circuit 54 is written for the generated address.

The instruction decoders 31-34 include user program memories 11-
The operation code of each instruction word read from 15 is decoded into 6 types of signals. It should be noted that only the instruction decoder 31 in the first column is adapted to decode the END instruction in addition to the above 6 types of signals.

Then, the MPU detects the END decode signal to determine the end of the logical operation operation.

In the condition translation circuits 41-44, the instruction decoders 31-34 and I /
The circuit conditions for one column of the ladder diagram are respectively recognized based on the four decode signals and the on / off data which are sent from the O data memories 21 to 24 in four time series.

Then, after the recognized circuit conditions are further translated into a form convenient for logical operation, they are supplied to the subsequent column unit arithmetic circuits 51 to 54 and the inter-column arithmetic circuits 61 to 63.

The column-by-column arithmetic circuits 51 to 54 and the inter-column arithmetic circuits 61 to 63 function as an arithmetic circuit capable of collectively processing a ladder diagram of 4 rows × 5 columns as a whole, and are given from the condition translation circuits 41 to 44. The entire ladder diagram for 4 rows × 5 columns is recognized according to the circuit condition for each column, and the logical operation corresponding to this is collectively processed.

Then, the operation result obtained from the output side of the column unit operation circuit 54 of the fourth column is written in parallel to all the I / O data memories 21 to 24 as described above.

In this way, while executing the user program for each unit ladder diagram (ladder diagram for one output relay),
When the END instruction is decoded in the instruction decoder 31,
The control right is handed over to the MPU, and thereafter, the input update operation, the output update operation, various system service operations, etc. are performed as usual.

Next, the operation of the above-described arithmetic device will be described in more detail with a more specific example.

First, the operation of creating a user program based on the ladder diagram and dividing and storing the user program in each of the user program memories 11 to 15 will be described.

In this case, the operator draws a ladder diagram corresponding to the user specifications on the CRT screen 92 while operating the keyboard 91, as shown in FIG.

The keyboard 91 includes a normally open contact key 911, a normally open contact key 912 with short line spacing, a normally closed contact key 913, a normally closed contact key with short line spacing.
In addition to the symbol keys such as 914, short-circuit key between rows 915, short-circuit key between columns 916, etc., a numeric keypad 917 and a cursor key 918 are provided, and by operating these keys appropriately, the CRT can be displayed using a well-known editor. A desired raster diagram is drawn on the screen 92.

Note that the hardware configuration and editor configuration for performing this type of drawing processing are programmable
Since it is well known to the controller engineer, detailed description will be omitted.

In this way, when the ladder diagram corresponding to the control specifications of the user is completed, it is applied to the ladder diagram data compiler thus obtained, and the data is organized in column units.

That is, the compiler first reads the obtained ladder diagram data from the beginning to read the ladder diagram data for the unit ladder diagram, and as shown in FIG. 6, the virtual ladder diagram space of 4 rows × 5 columns is read. Expand to the top.

Then, in the compiler, as shown in FIG.
Ladder diagram data for a unit ladder diagram is arranged and stored for each column of the virtual ladder diagram space shown in FIG.

Next, the obtained ladder diagram data for each column is sequentially stored in the user program memories 11 to 15 shown in FIG. 1 as shown in FIG. 8 under the control of the MPU.

As described above, when writing this program, MP
Address bus switcher AS11 to AS15 controlled by U
And, the data bus switching devices DS11 to DS15 are all switch-connected to the MPU bus side.

Next, the program execution operation will be specifically described.

When the RUN key (not shown) is operated while the ladder diagram data is written in the user program memories 11 to 15 as shown in FIG. 8, the address bus switching units AS11 to AS15 are programmed by the MPU under the control. Switched to the counter 80 side, and at the same time for the data bus switches DS1 to DS15, the instruction decoders 31 to 34 and the I / O data memories 21 to 2
Switched to the 4 side.

In this state, when the execution start signal START is given from the MPU, the prohibition of the step signal STEP is released in the timing generation circuit 70, and the program counter 80 receives the step signal STEP as shown in FIG. The step is started.

Then, the user program memories 11 to 15 are simultaneously addressed by the output of the program counter 80, and an instruction consisting of a predetermined opcode and an operand is formed on the data bus terminals of each user program memory 11 to 15 as shown in FIG. Words are sequentially read in parallel.

Then, the operation code of the instruction word is sent to the instruction decoders 31 to 34, and the operand is passed through the address bus switches AS21 to AS24 to the I / O data memory 2
Sent to the address input of 1.

At this time, the data read from the user program memory 15 in the fifth column serves as a switching control signal for the opecode address bus switch AS24 and the data bus switch DS24, and the operand is each address switch AS21 to AS24.
It becomes the address input to.

However, in this state, the address bus switch AS21 to AS24
Are switched and connected to the user program memories 11 to 14 side, the operand read from the fifth column user program memory 15 is not supplied to the address input of the I / O data memories 21 to 24.

Thus, when the operands read from the user program memories 11-14 are supplied to the address inputs of the I / O data memories 21-24, the respective I / O data memories 21-2
On / off data of the I / O number designated by the operand is read from 4 and supplied to the condition translation circuits 41-44 via the data bus switches DS21-DS24.

Further, when the opcodes read from the user program memories 11 to 14 are similarly supplied to the instruction decoders 31 to 34, each of the instruction decoders 31 to 34 outputs six decode signals which are decoding results of the opcodes. , These decode signals are supplied to the condition translation circuits 41 to 44.

In each of the condition translation circuits 41 to 44, the instruction decoder 31
~ 34 and I / O data memory 21 ~ 24 recognizes the circuit status for each column based on the decoded signal and ON / OFF data sent in four times, and translates this into a convenient form for calculation. Column-unit arithmetic circuits 51-54 and inter-column arithmetic circuits 61-63.
Supply to.

An example of the condition translation circuit 41 is shown in FIG. The feature of this conditional translation circuit is that each circuit element represented by six decode signals and one on / off data is translated into a circuit element using normally open contacts.

That is, six types of decode signals (normally open contact signal, normally closed contact signal, normally open contact signal with row short circuit, normally closed contact signal with row short circuit, column short circuit signal, row short circuit signal) are obtained from the instruction decoder 31. At the same time, one piece of on / off data is obtained from the I / O data memory 21, but the circuit element information represented by these decode signals and on / off data is all a simple normally open contact signal, one above It is translated into three types of signals, that is, an inter-row short-circuit presence / absence signal indicating a short-circuit with the line and ON / OFF data.

For example, when the content of the decode signal is a normally closed contact and the content of on / off data is on, the content of the decode signal is “normally open contact”, the content of on / off data is “off”, and the content of the inter-row short-circuit presence / absence signal is “ Translated as "no line short circuit".

In addition, the content of the decode signal is "normally closed contact with short circuit between rows".
And the content of the on-off data is "off", the content of the decode signal is "normally open contact", the content of the on-off data is "on", and the content of the line short-circuit presence / absence signal is "line short-circuited".
Is translated as

Then, such a translation process is performed in the translation unit 4111 composed of the logic gate shown in FIG.

In FIG. 2, the on / off data signal, the inter-row short circuit presence signal, and the normally open contact signal obtained from the translation unit 4111 are supplied in parallel to the four latch circuits 4121 to 4124.

The latch circuits 4121 to 4124 are supplied with the initial reset signal RST in parallel and the timing signals T _{1 to} T ₄ individually.

Here, as shown in FIG. 9, each timing signal
T ₁ through T ₄ may, I / O data Data to the data bus of the memory is set to produce the respective "1" pulse at the early time points of the state that is stable, also the initial reset signal
The RST generates a "1" pulse slightly later than the timing when the operation code OUT is read from the user program memory 15 in the fifth column.

Accordingly, the timing signals T ₁ to
When T ₄ arrives in order, the latch circuits S121 to 4124 are sequentially latched by the circuit element information of the first row, the second row, the third row, and the fourth row for the data of the first column. .

Of course, this circuit element information is the on / off data signal which is the above-mentioned translation result, the inter-row short-circuit presence / absence signal, and the normally open contact signal.

In this way, the ON / OFF data signals, inter-row short-circuit presence / absence signals, and normally open contact signals output from each of the condition translation circuits 41-44 are stored in the column unit arithmetic circuits 51-54 and the inter-column arithmetic circuit 61.
~ 63.

The on / off data obtained from the condition translation circuit 41 in the first column is directly supplied to the column unit arithmetic circuit 51 without passing through the inter-column arithmetic circuit.

The details of the column unit arithmetic circuit are shown in FIG. As shown in the figure, the column-unit arithmetic circuit 51 includes four row lines L _{1 to} L _4.
And four inter-row shorting lines l _{1 to} l ₄ are provided.

And gates 5111 to 5114 are provided on each row line L _{1 to} L _4.
A logical product of the normally open contact signal and the on / off signal is supplied via the.

Further, the row lines L _{1 to} L ₄ and the inter-row short-circuit lines l _{1 to} l ₄ are connected via diodes 5121 to 5124.

Therefore, when one of the circuit elements for one column is turned on by the normally open contact, "H" is always generated in the row short-circuit line corresponding to this, that is, the output line.

In addition, adjacent short-circuit lines, namely l ₁ and l ₂ , l
_{Between 2} and l ₃ and l ₃ and l ₄ , there are interposed AND gates 5132 to 5134 which are opened only when the content of the inter-row short-circuit presence / absence signal is “inter-row short-circuit present”.

Then, when these AND gates 5132 to 5134 are opened, a conduction path passing through the diodes 5142 to 5144 and the diodes 5162 to 5164 and a conduction path passing through the diodes 5152 to 5154 and the diodes 5172 to 5154 are formed. The short-circuit lines l ₁ and l ₂ are electrically connected to each other, l ₂ and l ₃ are electrically connected to each other, and l ₃ and l ₄ are electrically connected to each other.

Therefore, assuming that the circuit elements on the first row are normally open contacts and on, and the circuit elements on the second row are normally open contacts and off, and there is an inter-row short circuit, the first inter-row short circuit line l ₁ “H” is diode 5142, ANDGADE 5132, diode 51
The line appears on the _second line short-circuit line l ₂ via 62, and as a result, so-called parallel circuit operation is automatically performed.

As described above, the column-unit arithmetic circuits 51 to 54 can simultaneously process the parallel arithmetic operations for one column at a time.

Next, details of the inter-column arithmetic circuits 61 to 63 are shown in FIG. A feature of the inter-column arithmetic circuits 61 to 63 is that the column-unit arithmetic circuits that are adjacent to each other are cascade-connected.

That is, as shown in FIG.
Is the on / off data of the 2nd column 1st row to the 2nd column 4th row and the 1st column 1
Obtaining the logical product of the on-off data in the 1st row to 4th row of the row 4
It is composed of individual AND gates 6211 to 6214.

Therefore, even if the on / off data of the 2nd column, 1st row to 2nd column, 4th row is “on”, as long as the on / off data of the 1st column, 1st row to 1st column, 4th row is not “on”, the corresponding row number The on / off data of is not turned on, and the slave connection function is achieved.

The column-unit arithmetic circuits 51 to 54 and the inter-column arithmetic circuit described above
As shown in FIG. 10, the function of the entire arithmetic circuit formed by alternately arranging 61 to 63 as shown in FIG. 1 has a configuration equivalent to that of a programmable ladder diagram in which wiring is possible by software. is there.

That is, the ladder diagram shown in FIG. 10 consists of 16 normally open contacts and a fixed wiring portion shown by a solid line, and the other portions can be arbitrarily changed in wiring.

When the unit ladder diagram described above with reference to FIG. 6 is applied to this programmable ladder diagram, if the contents of the input / output data are in the state shown in FIG. 11, as shown by the dotted line in FIG. By wiring and setting ON / OFF, a circuit equivalent to the unit ladder diagram of FIG. 6 can be constructed.

Thus, the column-by-column arithmetic circuits 51-54 and the inter-column arithmetic circuits
According to the entire arithmetic circuit composed of 61 to 63, logical operations corresponding to a ladder diagram of 4 rows × 5 columns can be simultaneously processed in a batch.

On the other hand, as described with reference to FIG. 8, the operation code “OUT” is written in every fourth row in the user program memory 15 in the fifth column. At the same time as reading the data in the 4th row from
The address bus switches AS21 to AS24 are all connected to the operand data line read from the user program memory 15 in the fifth row, and the data bus switches DS21 to DS24 are all output lines of the column unit arithmetic circuit 54 in the fourth column. Connected to.

Further, as shown in FIG. 9, the write timing signal WT is output from the timing generation circuit 70 slightly after the operation code “OUT” is read from the user program memory 15 in the fifth column. The write timing signal WT is supplied in parallel to each I / O data memory 21-24.

As a result, the data in the fourth row is read from each of the user program memories 11 to 15, and the column-unit arithmetic circuit 54 is correspondingly read.
When the output data which is the final calculation result is output from, the output data is written in parallel to the corresponding addresses of all the I / O data memories 21 to 24.

Then, as shown in FIG. 9, when this writing is completed, the initial reset signal RST is output with a slight delay due to this, and the initial reset signal RST causes the latch circuits 4121- 4124 will be cleared.

In this way, each user program memory 11-15 to 4
Each time a command word corresponding to a ladder diagram for rows is read in parallel, logical operations equivalent to a ladder diagram for 4 rows × 5 columns are simultaneously processed in a batch, and the I / O data memory 21 ... 24 output data is rewritten.

When the END instruction is read from the user program memory 11 in the first column while repeating the above, the END signal is obtained from the instruction decoder 31, and the MPU side detects this END signal to complete the loop of the user program. It is determined that the execution is completed.

Then, the control right is transferred to the MPU side, and in the MPU, the address bus switching units AS21 to AS24 and the data bus switching units DS21 to DS are
Switch 24 to the MPU bus side.

Then, after performing the output update operation to send the output data of the I / O data memories 21-24 to the outside, write the input data fetched from the outside to the corresponding area of the I / O data memories 21-24. Performs input update operation from Japan.

Thereafter, the monitor process, various system service processes, etc. are executed, and the execution start signal START is given again to the timing generation circuit 70.

Then, in the same manner as described above, the prohibition of the step signal STEP is released, the program counter 80 is restarted, and the above-mentioned instruction execution operation is repeated.

As described above, according to the arithmetic unit according to the present embodiment, the five user program memories 11 to 15 are associated with each column when the virtual ladder diagram space of 4 rows × 5 columns is equally divided into 5 columns. Is provided, and each unit ladder diagram of the ladder diagram corresponding to the user specification is sequentially stored with each circuit element information that should be present in the corresponding column when the unit ladder diagram is expanded in the virtual ladder diagram space. Each circuit element information is read from the program memories 11 to 15 simultaneously in parallel by the program counter 80,
Maximum of 4 rows specified by the read circuit element information x 5
A logical operation corresponding to a unit ladder diagram for columns is collectively processed by an arithmetic circuit including column-unit arithmetic circuits 51 to 54 and inter-column arithmetic circuits 61 to 63.

Therefore, a unit ladder diagram corresponding to a virtual ladder diagram for a maximum of 4 rows × 5 columns can be collectively executed at four read timings, and the operation speed can be dramatically improved without using a high-speed memory or the like. It is possible.

Although the unit ladder diagram that can be collectively executed has a size of 4 rows × 5 columns in the above embodiment, it is needless to say that a larger scale ladder diagram can be easily implemented.

Further, in the above embodiment, the virtual ladder diagram space of 4 rows × 5 columns is equally divided into 5 columns, and the user program memory is allocated to each, but for example, this is equally divided into 16 vertical and horizontal areas,
If each user program memory is allocated, logical operations corresponding to a ladder diagram of 4 rows × 5 columns can be collectively processed by one read timing, and the operation speed can be further increased. it can.

Further, since the column unit arithmetic circuit and the inter-column arithmetic circuit shown in this embodiment are a combination of simple logic circuits, high integration can be easily achieved and the arithmetic unit can be miniaturized.

Further, in the above embodiments, the signal obtained from the instruction decoder and the I / O data memory is further translated into a simpler signal by the condition translation circuit, and then applied to the column unit arithmetic circuit and the inter-column arithmetic circuit. However, if the column-unit arithmetic circuit and the inter-column arithmetic circuit can be complicated, the conditional translation circuit can be omitted.

[Brief description of drawings]

FIG. 1 is a hardware block diagram showing an embodiment of a programmable controller arithmetic unit according to the present invention, FIG. 2 is a circuit diagram showing details of a condition translation circuit, and FIG. 3 is a column unit arithmetic circuit. FIG. 4 is a circuit diagram showing the details of the inter-column arithmetic circuit, FIG. 5 is an explanatory diagram showing the schematic configuration of the programming device, and FIG. 6 is a diagram on the virtual ladder diagram space.
FIG. 7 is an explanatory view showing a state in which a ladder diagram for a unit is expanded, FIG. 7 is an explanatory diagram showing a state in which the ladder diagram data shown in FIG. 6 is arranged in columns, and FIG. 8 shows the contents of each user program memory. A memory map shown in FIG. 9 is a time chart showing states of various signals obtained from the timing generating circuit,
FIG. 10 is an equivalent circuit of an arithmetic unit composed of a column unit arithmetic circuit and an inter-column arithmetic circuit, and FIG. 11 is an explanatory diagram showing an example of data in the I / O data memory. 11 to 15 …… User program memory 21 to 24 …… I / O data memory 31 to 34 …… Instruction decoder 41 to 44 …… Condition translation circuit 51 to 54 …… Column-by-column arithmetic circuit 61 to 63 …… Inter-column arithmetic Circuit 70 …… Timing generation circuit 80 …… Program counter AS11 to AS15 …… Address bus switcher AS21 to AS24 …… Address bus switcher DS11 to DS15 …… Data bus switcher DS21 to DS24 …… Data bus switcher

Claims (1)

(57) [Claims] 1. A unit ladder diagram on a ladder diagram provided corresponding to each divided area when a virtual ladder diagram space of M rows × N columns is divided into N columns and corresponding to user specifications. At the same time as a plurality of user program memories in which each circuit element information that should exist in the divided area is sequentially stored when expanded on the virtual ladder diagram space, and each circuit element information from the N column user program memories. Program reading means for reading in parallel and logical processing of N columns in parallel based on the read circuit element information are collectively processed in parallel, and the parallel processed N columns are connected in cascade. An arithmetic unit for a programmable controller, comprising: an arithmetic circuit capable of collectively processing logical operations for one unit ladder diagram.