JPS60206177A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To reduce ohmic contact resistance without damaging the effect of modulation doping, and to improve the characteristics of a semiconductor by heating the whole by the projection of energy rays and diffusing a second impurity having diffusion length larger than a first impurity while crossing over said first semiconductor layer. CONSTITUTION:A non-doped GaAs layer 12, in which Si is not doped to a hetero-junction interface with the GaAs layer 12 and Si is doped to other regions, and N type GaAs 14 to which Sn is doped are formed on a semi-insulating GaAs substrate 11 in succession. 12A represents a two-element electron gas. The whole is thermally treated through infrared flash. Tin doped to a GaAs/AlGaAs group semiconducltor base body is diffused excellent through infrared flash annealing, and N type regions 15 are shaped in depth in which the regions 15 cross an N type region in an AlGaAs layer 13, to which silicon is doped, and reach to the two-element electron gas 12A. A source electrode 16, a drain electrode 17 and a gate electrode 18 are disposed.

Description

[Detailed Description of the Invention] (IL) Technical Field of the Invention [JJ describes a method for manufacturing a semiconductor device, particularly a method for manufacturing a semiconductor device in which an impurity-introduced region is formed with a high degree of error without completely impairing the characteristics of modulation doping. Regarding the manufacturing method.

(b) Technical Background Currently, silicon (Si) semiconductor devices are the mainstay, but the speeding up of 81 semiconductor devices is limited by the physical properties of Si such as carrier mobility. Efforts are being made to achieve greater efficiency and lower power consumption by using compounds such as gallium arsenide (GaAs), which has a much larger degree of St.

In a semiconductor device using a conventional structure of a compound such as St or GaAs, carriers move between the layers where impurity ions are present. When the carriers move, they are scattered by lattice vibrations and impurity ions,
When the temperature is lowered to reduce the probability of scattering due to lattice vibration wJvc, the probability of ionized impurity scattering increases, thereby limiting carrier mobility.・
In order to completely eliminate this impurity scattering effect, the region where impurities are added and the region where carriers move are spatially separated to increase the mobility of carriers, especially at low temperatures. heterozygous F
Conventional technology and problems An example of a known heterojunction FET is shown in Figure 1 (a).
). A GaAs layer 2 and an aluminum gallium arsenide (AtGaAs) layer 3 having a lower electron affinity than the GaAs layer 2 are provided on a semi-insulating GaAs substrate 1, and the interface between the two layers completely forms a heterojunction. Silicon (81) is introduced into the AtGaAs layer 3 as a donor impurity and becomes n-type, and the GaAs layer 2 is non-doped and is L-type.

n-type AtGaAa I so 3 (referred to as electron supply layer) to l
A two-dimensional electron gas is generated near the heterojunction interface by the electrons transferred to the type GaAs layer 2 (referred to as the channel layer), and 70 electrons are generated at the source by controlling the voltage applied to the gate electrode 4. Electrode 5 and Shimiwi 11 Sagi 4
I can't wait. In this way, two two-dimensional electron gases, which are the channels of the hetero-sliding IT, are formed in the non-doped semiconductor 19, and furthermore, a non-doped sub+)- region is formed near the AtGaAs l@3 hedero junction. established,
High electron mobility has been obtained. , this heterojunction FE
The connection between the source electrode 5 and drain electrode 6 of T and the two-dimensional electron gas region 280) is characterized by a low resistance starvation. For this purpose, the applicant of the present patent previously proposed in Japanese Patent Application No. 56-77657 that AtQ
A semiconductor device is provided in which a GaAs layer 7 is formed as an output electrode connection layer on the Asl layer 3, and a source electrode 5 and a drain electrode 6 are provided on the GaAs ItW layer 7. This GaAs layer 7 is usually made of n-type silicon doped, and its concentration is 1 to 2 X l O" (cm
−”].This n W GaAs +=
All the ohmic electrodes were arranged using AuGe/Au% in 7, and an alloying process was performed at 450°C for about 5 minutes to form an ohmic electrode.
Because the carrier density in the n-type GaAs layer 7 is not high enough and there are variations in the depth of the alloy layer, there is only communication between the two-dimensional gas and the source and drain.
C and become insufficient.

Another conventional example of ohmic horisumi formation is shown in Figure 1 (C
), the source electrode 5 and the drain 1
Selenium C3e) *? For this reason, a method using ion implantation is needed. However, in order to prevent the silicon doped into the n-type GaAs electron assembly layer 3 from diffusing and reducing the mobility of the two two-dimensional electron particles (the activation of the implanted ions Heat-treated gum can reach up to 900°C
], is limited to infrared order JA etc. for about 10 seconds. For this purpose, the i-type GaA in region 8 obtained by this method is
s I so 2 hetero''
The drawback is that it is possible to obtain a sufficiently low ohmic a resistance of only about X 10 ''[ttn-').

(d) Purpose of the invention 4 - To the invention r3fJ if evening,) to flow junction F E
As in T, the modified doping of Ushijin body Kyoto body V-jin, the lack of effect and loss of the said dobinda, 19%, Memick payment)
The entire purpose of this invention is to provide a method of using a half-strength body 14 suitable for high carrier O exercise; For the purpose of the invention, a layer t- of the second half-boiled body containing the second impurity '#J is formed on one batch of the first half-boiled body containing the first impurity.
The selectively provided semi-attached substrate is heated by a force of 1'' by irradiation with energy rays, and the second impurity, which is more diffused than the first impurity, is spread over the three layers of the living monument of Kou 1. Diffusion half body 1fq: a) Achieve V by manufacturing method.

For example, infrared light is suitable as the Lugie wire, and when the first and second semiconductor layers are made up of the ■-■ group compound body, for example, the first impurity sound There is a combination in which silicon and the second impurity are tin. is a process j-B'ft diagram showing the applied qU set'/I' for the heterojunction FETVC.

p72 is a semi-insulating GaAs substrate ll referred to in 1(a). and grow it. 212 is a non-doped GaAs layer with a thickness of 0.5 [μm].
degree, 13 i′, LALo, 3 GaO, 7 As
The layer is dusty, the thickness is about 50 [old η], and the GaAs
6 (nm) from the heterozygotic interface with I fin 12 Table 1 -
Up to non-dope, 7 other meals (area I X I Q
The silicon is fully doped to the extent of "[tyn-"]. The thickness is, for example, 50[gr.
: nm]GfJ'e. Note that 12ArJ: indicates a two-dimensional 'c gas.

Figure 2 (See Figure 2) Selectively remove parts of the pond.
CCL2Ft) 'e etchant can be easily carried out by dry etching.

See FIG. 2(e), by an infrared flash from the top surface of the semiconductor substrate.
A heat treatment is performed at a temperature of 900 (°C) for a time of about 10 seconds.As shown in FIG. formed into G
The concentration near the heterojunction interface with the aAs layer 12 is 3
Figure 3 shows the tin redistribution profile (curve B) after infrared flash annealing at 4 degrees 900 [℃] for 2 hours and 10 seconds, and the tin redistribution profile (curve B) before annealing. This is a chart for comparison with the profile (curve A) of

Regarding non-experimental examples, the above-mentioned annealing value is equivalent to the value before annealing, and l
:No decrease in filtration was observed in Figure 2(d) Reference source ta16. Drain electrode &17 and gate electrode 18
to be placed. These electrodes can be formed by conventional techniques, and in some cases, for example, for source and drain electrodes, a total AuGe layer thickness of 50
(The total thickness of the Au layer is about 300 nm3, and an alloying process is performed at a temperature of about 450 [C] for about 5 minutes, and the gate electrode is formed using aluminum (A/!) e.

Heterojunction FE completed by the manufacturing method explained above
Regarding AT, the transition of two-dimensional electron gas is first shown in Figure 1 Φ
It is equivalent to the conventional structure heterojunction FET shown in Fig.
It was confirmed that the transconductance gm increased and the variation decreased compared to the conventional example shown in FIG. 1(c). , heterojunction FET7z
It is now possible to easily form a deep impurity-introduced region with high density in a semiconductor substrate containing any modulation doping without completely losing the effect of modulation doping, and it is possible to improve the characteristics of semiconductor devices such as reducing ohmic contact resistance. Can do 0

[Brief explanation of drawings]

Figures 1 (a) to (c) are cross-sectional views showing conventional examples of heterojunction FETs, Figures 2 (a) to (d) U heterojunction FE
FIG. 3 is a diagram showing an example of the 13-distribution of tin by infrared flash annealing. In the figure, 11 is a semi-insulating GaAs substrate, 12 is undoped GaAs His, and 13 is Si gold-doped A.
tGaAa II, l 4USnk doped Y, = Ga
As layer, 15 Sn diffusion region, 16 source-i, 17
18 indicates the drain electrode, and 18 indicates the gate electrode.

Claims (3)

[Claims] (1) A semiconductor substrate in which a second semiconductor layer containing a second impurity is selectively provided on a first semiconductor layer containing a first impurity is heated by irradiation with an energy beam,
A method of manufacturing a semiconductor device, characterized in that the second impurity metal is diffused over the first semiconductor layer with a diffusion length 'jtV greater than that of the impurity. (2) The method for manufacturing a semiconductor device according to claim 1, characterized in that the hlJ energy rays are infrared rays. (3) 11i] The first and second semiconductor layers are grooved with a ■-■ group compound, and the first impurity is silicon and the second impurity is tin. Claims IF! A method for manufacturing a semiconductor device according to Item 1 or @ Item 2.