JPS60206166A - Semiconductor device - Google Patents

Abstract

PURPOSE:To improve the degree of integration while increasing the speed of operation by forming the titled device in structure, in which a MOS type transistor is laminated and disposed to the upper section of a MOS type capacitor for storing a memory, and making a gate electrode common in both of the transistor and the capacitor. CONSTITUTION:An N-type diffusion region 103 is formed on substrate 101 region, and an N type semiconductor pattern 108, a P type semiconductor pattern 109 and an N type semiconductor pattern 110 in width narrower than the diffusion region 103 are shaped on the region 103 in succession. An outer circumferential section is coated with an oxide film, a word line 112 consisting of polycrystalline Si to which P is diffused is formed on the oxide film, and an SiO2 film 113 is shaped on the word line 112. A bit line 116 formed on the film 113 is in contact with an N type semiconductor pattern 110 as an uppermost layer through a contact-hole 114 shaped while penetrating the oxide film 113 and the word line 112 composed of polycrystalline Si. The inner circumferential surface of the contact-hole 114 is coated with the oxide film 114, and an electrical contact with the word line 112 of the bit line 116 is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a semiconductor device having one transistor and one capacitor type memory cell.

[Technical background of the invention and its problems] Semiconductor devices, especially semiconductor layer devices, are becoming larger and larger, and memory cells are becoming smaller and smaller.

As an example of a conventional semiconductor memory device, its cross-sectional view is shown in the first
As shown in the figure. In the figure, 11 is a P-type semiconductor substrate,
A field oxide film 12 is selectively provided on this semiconductor substrate 11 . On the surface of the island-shaped substrate 1 region (device region) separated by the field oxide film 12, n+ type diffusion regions 13 and 14 are provided electrically isolated from each other.

A gate electrode 16 made of, for example, a high melting point metal is provided on the surface of the substrate 11 including between these diffusion regions 13 and 14 with a silicon oxide film 15 interposed therebetween.

These n+ type diffusion regions 13.14. The oxide film 15, gate electrode 16, etc. form the rv+OS type 1 to transistor (M). Also, the n+ type diffusion layer region 1/I
A capacitor electrode 18 made of polycrystalline silicon is provided on the substrate between the field oxide film 12 and the field oxide film 12 with a silicon oxide film 017 interposed therebetween. Further, an insulating film 1 is formed on the entire surface including the gate electrode 16 and the capacitor electrode t (Ii 18).
9 is coated. This insulation 1! On 19, the above n
Via the +-type diffusion region 13 and the contacts 1 to 2o,
A bit line 21 for connection is provided. In a semiconductor layer 1fi device having such a configuration, information is stored as a charge in the inversion layer of the IVI OS type capacitor formed by the polycrystalline silicon electrode 18 containing a high concentration of impurities and the oxide film 17; N diffusion region 1 or 13 through transistor channel and contact 1-ball
It can be read and written through the aluminum bit line 19 which is in contact with the .

Incidentally, in a semiconductor memory device having such an element structure, the MOS + - transistor and the MO3 type capacitor are arranged in a plane, and therefore there is a limit to the improvement in the degree of integration. In order to overcome this drawback, a semiconductor device having a structure as shown in FIG. 2, for example, has been proposed.

That is, 21 in FIG. 2 is a P-type semiconductor, and on this substrate 21 there is a field 1-Ill as an element isolation region.
A chemical film 22 is provided. This field oxide film 22
A bit line 23 made of an N-type impurity diffusion layer is formed on the surface of the island-shaped base tli2 region separated by. On this Gila l-line 23 are N-type, P-type, and N-type semiconductor layers 24.
25 and 26 are sequentially stacked. These semiconductor layers 24
．． The exposed surfaces of 25 and 26 are provided with oxide lll1!27. Further, an electrode 28 made of polycrystalline silicon is provided on the N-type semiconductor layer 26 via the oxide lI 227. An oxide film 29 is provided around this electrode 28. Then, a word line 307'+X is installed (
]

A memory cell having such a structure has a word line 3o, an oxide film 27J3, and N, P, N type 4Q9 body layers 24, 25, 26 opposite to these, 14 transistors (14), and a capacitor. are polysilicon electrode 28, oxide film 27, and N-type semiconductor layer 26
J: Consists of MO8 structure consisting of:

As a result, the MO8 type capacitor and the MO8 type transistor are arranged three-dimensionally, thereby attempting to miniaturize the occupied area.

However, in this structure, since the bit line 23 is made by diffusing impurities into the semiconductor substrate 21,
Junction capacitance occurs in that region, and electrical resistance is also large. This causes a delay in the signal propagating through the bit line, which poses a major hindrance to increasing the speed of memory.

UObject of the Invention The present invention has been made in view of the above circumstances.
It is an object of the present invention to provide a semiconductor device in which cells can be highly integrated and the operating speed can be increased.

[Summary of the Invention] In order to achieve the above object, the present invention provides a semiconductor memory device in which a one-transistor/one-capacitor type memory cell is formed on a semiconductor substrate of a first conductivity type. an impurity region of two conductivity types, a first semiconductor layer of at least a first conductivity type, and a second semiconductor layer of a second conductivity type, each having an area smaller than the region and successively laminated on the impurity region.
two semiconductor layers, and an electrode provided via an insulating film so as to cover the exposed surface of the first region and the peripheries of the first and second semiconductor layers and connected to a word line. , and a bit line provided on an insulating layer covering these and in contact with the second semiconductor layer through a contact hole provided through the insulating film, and an impurity having a conductivity type opposite to that of the semiconductor substrate is diffused. A semiconductor layer of a desired conductivity type is laminated on the impurity region using epitaxial technology in an area narrower than this impurity region, further covered with an oxide film, a bit line is wired on the upper surface, and a semiconductor layer is formed by penetrating the above insulating film. MOS type 1 to transistor, by connecting to the epitaxial semiconductor layer through the provided contact hole.
MO3 type capacitor (with a negative layer on the west side, which improves the space factor and improves the pitch) - wires are placed on the top surface so that metal wiring material with low electrical resistance can be used, and By making contact with the train area on the side, the joint capacitance M of the H- line is suppressed, signal delay is suppressed, and high speed is achieved.

[Embodiments of the Invention] Hereinafter, embodiments of the present invention will be described together with the manufacturing process thereof with reference to the manufacturing process diagram shown in FIG.

First, a field oxide film 10 is formed on a P-type semiconductor substrate 101.
2 for example as LOCO3 (LocalQXidtiOn
of' 3ilicon) method. Next, island-shaped substrates 10 separated by this field oxide film 102
An N-type diffusion layer 103 is formed on one region (element region) by thermal diffusion or ion implantation (as shown in FIG. 3(a)).

Next, after forming an N-type semiconductor layer 104, a P-type semiconductor layer 105, and an N-type semiconductor layer 106 on the entire surface by epitaxy cell technology, a silicon nitride pattern 107 is formed (as shown in FIG. 3(b)). Next, using the silicon nitride film 107 as a mask, the N-type semiconductor layer 106. The P-type semiconductor layer 105 and the N-type semiconductor IH 104 are etched to form an N layer narrower than the diffusion region 103 from the substrate 101 side.
A type semiconductor pattern 108, a P type semiconductor pattern 109, and an N type semiconductor pattern 110 are sequentially formed. Then, thermal oxidation treatment is performed to form a silicon oxide film 1 on the exposed surfaces of each of the patterns 108 to 110 and the exposed surface of the diffusion region 103.
11 is formed.

(Illustrated in FIG. 3(C)).

Next, a polycrystalline silicon layer is deposited to form a word line, and phosphorus is further diffused into this polycrystalline silicon layer to reduce the layer resistance. Next, this is patterned to form a word line 112, and S is formed on the word line 112 by CVD.
An i02 film 113 is formed.

Next, all of the 5102 film 113 corresponding to the N-type semiconductor pattern 110 is selectively removed to open the contact ball 114. Subsequently, a thermal oxidation process is performed to form an oxide film 115 on the surface of the word line 112 made of polycrystalline silicon exposed on the inner surface of the contact hole 114 (as shown in FIG. 3(d)). . In that case, please contact Contact 1.
The drain region of the MOS transistor that was exposed at the bottom of the hole 114 is covered with an oxide film 115, but after this, by rotating RIE with a strong lending property, the contact 1 and the side wall of the hole 114 are covered with an oxide film 115. Leaving the oxide film behind,
Only the bottom oxide film can be removed.

Next, after depositing aluminum, patterning was performed for 11
Then, a bit line 116 connected to the N-type semiconductor pattern 110 via the contact 1-hole 114 is wired.
(Illustrated in FIGS. 3(e) and 4). Note that FIG. 4 is a partial plan view of FIG. 3, and this figure shows an example of the arrangement of four adjacent memory cells. Note that 117 indicates an element region of a memory cell formed on this substrate 101.

In the memory cell of the present invention, as shown in FIG. 3(e) and FIG.
3 is formed, and an N-type semiconductor pattern (n-type epitaxial layer>108 is formed on this N-type semiconductor pattern 108 in an area narrower than this N-type diffusion region 103, and a P-type semiconductor pattern is formed on this N-type semiconductor pattern 108). The pattern (p-type epitaxial layer) 109 further forms this P-type semiconductor pattern 1.
N-type semiconductor pattern (N-type epitaxial layer) on 09
It has a laminated structure provided with 110. The outer periphery of these is covered with an oxide film, and on top of that is a word line made of low resistivity polycrystalline silicon with phosphorus diffused.
12 is provided, and an SiO2 film 11 with a thickness of 13 is formed thereon. Further, a human line 116 made of aluminum is provided on the oxide film 113 of the opening, and bit 1!116 is connected to this oxide film 113 and the word line 1 made of polycrystalline silicon.
It is in contact with the uppermost layer N-type semiconductor pattern 110 through a contact hole 114 formed using the uppermost layer 12 . Further, the inner peripheral surfaces of the contacts 1 to 114 are covered with an oxide film 114, and the hit line 11G is connected to the word 1i! 112
This prevents electrical contact with the

According to such a configuration, the MO8 type transistor 1 uses the oxide film 111 as the gate oxide film, the word line 112 in the portion facing the oxide film 111 as the negative electrode, and the N-type semiconductor pattern 110 as the drain electrode. , with the N-type semiconductor pattern 108 as a source. Also, IV
The IOS type capacitor is formed of a region protruding from the N-type semiconductor pattern 10B and a portion opposing the word line 112, and the capacitance of this opposing portion becomes the capacitance of the oscillator. That is, this device has a structure in which an NIO3 type transistor is stacked on top of an MO8 type capacitor for memory N product, and this stacked transistor is surrounded by a ring-shaped polycrystalline silicon. The electrode 1~ is formed as a common electrode for both the transistor and the capacitor. Then, when the voltage of the goo 1~electrode is made high enough, the P-type semiconductor pattern 109
A channel is generated at the interface between the gate oxide film (the region facing the P-type semiconductor pattern 109 in the oxide film 111 and its vicinity), and the information (charge) stored in the MoS-type capacitor part is transferred to the pin 1- is read out through line 116 and (
+5 is written (charge is stored) and the memory
Functions as a cell.

This device has a structure in which MOS type transistors are stacked on top of an MO8 type capacitor for memory storage, and the gate electrode is shared by both the transistor and the capacitor. Therefore, since it has a three-dimensional structure, high integration can be achieved.

In addition, as shown in Fig. 2, 1 [the conventional laminated structure is M
This is because the S-type capacitor is formed with its surface parallel to the semiconductor substrate 101, and furthermore, this capacitor is disposed so as to face the pit l-m23 region formed of the diffusion layer. , the area of the junction capacitance in the bit line 23 region is structurally at least comparable to the area of the MO8 type capacitor.

However, in the semiconductor device of the present invention, the pin 1-line 11
6 is the uppermost N-type semiconductor pattern 1 which becomes the drain region.
Since -C is disposed on top of the capacitor 10 through a thick oxide film 113, such junction capacitance is only that of the drain region of the MO8 type l-transistor, which is considerably smaller than the area of the IVI OS type capacitor. Therefore, the capacitance of the C and pin 1 wires can be made smaller than that of the conventional one, and since metal is used as the pin 1 wire material, the electrical resistance is also low, and the signal propagation speed can be increased. .

It goes without saying that the semiconductor device according to the present invention can be manufactured by a method different from the manufacturing method described above, and can also be manufactured by a method as shown in FIG.

That is, the basic structure of FIG. 5b is the same as that shown in FIG. 3(e), but the first epitaxy n-type layer (
The N-type semiconductor layer 104) is omitted. In this case, M.O.
Since the 8-type capacitor is formed only on the surface of the n-type layer diffused on one P-type substrate, it is slightly disadvantageous in terms of area compared to the previous embodiment, but the effect of the previous technique on the conventional technique Ki is as follows. The advantage is that the process is simplified since it is omitted.

[Effects of the Invention] As detailed above, in the present invention, the MO8 type capacitor has the following effects:
For example, an n+ type diffusion region formed in the active region of a P type semiconductor substrate and an n+ type region formed above it are formed on the front and side surfaces, respectively, and an MO8 type transistor is formed in a stacked manner on top of the n+ type diffusion region. Compared to conventional planar structures, this structure allows the memory element to occupy a smaller area and allows for higher integration.Moreover, the bit line is formed with a metal layer on the top surface across a thick oxide film. (Since it is formed by laminating and patterning, the junction capacitance is lower than the conventional laminated structure in which at least a human line is made by diffusing impurities into the semiconductor substrate, an N10S transistor is formed on top of it, and a capacitor is formed on it.) The electrical resistance can be drastically reduced,
Therefore, it is possible to provide a semiconductor device having the effect of reducing the delay of signals propagating through the pill-tilt.

[Brief explanation of the drawing]

1 to 2 are cross-sectional views of a conventional semi-nine-body device with different terives. FIG. 4 is a plan view showing an example of the planar configuration of a semiconductor device according to the invention with respect to four adjacent memory elements, and FIG. 5 is a sectional view showing another embodiment of the invention. 101...P type semiconductor substrate, 102...n+ type diffusion region, 103...field oxide film, 108.110
...N type semiconductor pattern, -109...P type semiconductor pattern, 111...Oxide film, 112...Word line, 113...Thick oxide film, 116...Bit line. Applicant's representative Patent attorney Takehiko Suzue Figure 2 Figure 3 Figure 3 Figure 4 Figure 5

Claims (1)

[Claims] In a semiconductor layer 1 device in which a memory cell of 11 helangisters and 1 capacitor type is formed on a semiconductor substrate of a first conductivity type, an impurity region of a second conductivity type formed on the semiconductor substrate and an impurity region of the second conductivity type formed on the semiconductor substrate are successively formed. at least two semiconductor layers, a first semiconductor layer of a first conductivity type and a second semiconductor layer of a second conductivity type, each having an area smaller than the laminated region;
an electrode provided via an insulating thin film so as to cover the exposed surface of the first region and the peripheries of the first and second semiconductor layers and connected to a word line; an insulating film provided on the electrode; , a contact hole that is opened through the insulating film and the electrode, and has an insulating film formed on the exposed surface of the electrode;
1. A semiconductor device comprising a pin wire provided on the insulating crotch and in contact with the M2 semiconductor layer via the contact 1 to the hole.