JPS60205620A - System for decreasing output terminal - Google Patents

Abstract

PURPOSE:To decrease the number of output terminals by grouping signals which are outputted simultaneously and signals which are not outputted simultaneously and providing a selector for switching those signals, and thus sharing output terminals. CONSTITUTION:Output signals CA**1 and CB**1 of a control system are selected by the selector 3 and a signal CC**1 is outputted as an output signal. Further, a signal CID1 which determines the selector output is supplied to a high-priority board 1 as it is and to a low-priority board 2 while inverted through an inverter 4. In this case, a signal generated only by the board 1 is specified as the signal CA**1 and a signal generated only by the board 2 is specified as the signal CB**1. Then, logic 0 is determined for the board 1 and logic 1 is for the board 2; and the signal CID1 is fixed at 0, thereby eliminating output terminals which becomes unnecessary as a result of bit slicing. Namely, the CB**1 of the board 1 and the CA**1 of the board 2 are fruitless signals and they are not sent to output terminals and selected by the selector to decrease the number of output terminals.

Description

[Detailed Description of the Invention] [Technical Field of the Invention] The present invention copes with the increase in the amount of input/output information to and from the outside, which increases with the increase in the degree of logic integration within a unit area. This invention relates to an output terminal reduction method that can cope with the physical limitation on the number of output terminals on a board.

[Technical background of the invention]

At present and in the future, the degree of logic integration within a unit area will continue to improve. In such a case, the amount of information input and output to and from the outside increases as the amount of logic increases. However, there is a physical limit to the number of external input/output terminals. Therefore, we reduced the number of input/output terminals by bit slicing the logic and creating a multi-configuration, and furthermore, for the reduced terminals,
It has been put into practical use to utilize the 9-beat rate.

FIG. 1 shows an example of a conventional bit slice, which consists of an upper board (1) and a lower board (2). Output signals DDOO from boards (1) and (2)
I^DD311 is the data system output signal, CA sansho 1 and C
B-)-1 shows the output signal (16 bits) of the control system. However, CB-11 of the upper board (1)
1 is an output signal that is valid only on the lower board, the lower board (2
CA -%-% 1 of ) is an output signal valid only for the upper board, and there is no need to output it to the outside of the board, and each becomes NC (No Connect mode). Upper board (1) and lower board (2) in Figure 1
are bit sliced and both have the same logic.

As shown in the example, a 32-bit data signal can be converted into 16-bit, 16-bit DDOO by bit slicing.
It is divided into I to DD151 and DD161 to DD311, and the number of output terminals for each board can be halved. However, the control system signal C141,011+1 required the same number of output terminals for the upper and lower boards.

[Problems with background technology]

Conventionally, as described above, the target of pit slicing was the data system, so the number of input/output terminals could be easily reduced. However, as the degree of logic integration increases, the number of control signals increases and it becomes difficult to fit them within the physically limited number of input/output terminals.

[Purpose of the invention]

In view of the above, an object of the present invention is to provide an output terminal reduction method that can cope with the increase in control system signals that increase as the logic density increases within the range of the physically limited number of input/output terminals. do.

[Summary of the invention]

The present invention is designed to unify output terminals for control signals that are generated redundantly on each board by bit slicing, for example.

[Embodiments of the invention]

Figure 112 shows an embodiment of the present invention.

The features of the present invention are that C allocation 1 and CB←1 of the control system output signal are selected by the selector (8FfL) (3), and Cnl (16 bits) is output as the output signal, and the selector output is determined. The CIDI signal is sent to the upper board (
1) and the lower board (2) are inverted through the inverter (IJ (4). In this second factor,
Data system signals are the same as in FIG. Control signals are selected by selectors on the board, so the number of output terminals is limited. In this case, for example, the upper C
A signal generated only by the upper board is assigned to the A*+1 signal, and a signal generated only by the lower board is assigned to the lower cn-x+i signal. And 10# on the top board
, 11” for the lower board, and CI
By fixing the DI signal to ``0#'', it is possible to reduce duplicate output terminals caused by pit slicing.In other words, the output signals of CB++1 on the upper board and CA arrow +1 on the lower board in Fig. 1 are useless output signals, and NC Therefore, it is not output to the output terminal from the board, but is selected by the selector on the board, reducing the number of output terminals.

FIG. 3 shows another embodiment of the present invention, in which logical bit slicing is not performed. CA++1 and C13 in the board
The signal 1f-1 is assigned a signal that cannot be output simultaneously. and selector control signal C3EL1
By switching with , either CA % 1 or C 11 % 1 is output. This method also allows the number of output terminals to be reduced.

〔Effect of the invention〕

The present invention is as described above, and has the effect of being able to cope with an increase in the number of control signals that increases with the increase in logic density by adding more output terminals.

[Brief explanation of drawings]

FIG. 1 is an explanatory diagram of a conventional system, FIG. 2 is an explanatory diagram of one embodiment of the present invention, and FIG. 3 is an explanatory diagram of another embodiment of the present invention. CAAl1, CB++1: Control system τ3:
selector. Figure 1 Figure 2 Figure 3

Claims (1)

[Claims] Among control signals, signals that are not output at the same time are placed in separate signal groups, and signals that are output at the same time are grouped together into one group.
An output terminal reduction method characterized in that the number of terminals is reduced by sharing output terminals by providing a selector and switching each of these signal groups.