JPS60202961A - Charge transfer type solid state image sensor element - Google Patents

Abstract

PURPOSE:To prevent the yield of an after image, by improving the plane structure of a transfer gate so as not to generate a threshold voltage due to a narrow channel effect under the transfer gate. CONSTITUTION:A photodiode 1 is formed by an N type impurity layer. Polycrystalline silicon 2-1 at the first layer forms a vertical charge transfer element (CCD) 2-3 and a transfer gate electrode 7. The channel width W of a transfer gate is the same in any place in the transfer gate region 7. A potential (y) at the time of reading under the transfer gate is constant phiT at any place. Therefore a potential barrier is not yielded under the transfer gate. All the signal charges QS, which are stored in the photodiode during one field period (one frame period), are normally read and written into the vertical CCD through the transfer gate. At the same time when the reading of the charges is finished, the potential of the photodiode is reset at phiT, and the signal charges to the next field are stored.

Description

Detailed Description of the Invention [Field of Application of the Invention] The present invention provides a photoelectric conversion element on a semiconductor substrate and a charge transfer element (Charge Co., Ltd.) for extracting optical information from each element.
ul) led device, hereinafter abbreviated as CCD. ) is related to a solid-state image sensor using

[Background of the invention]

Solid-state imaging devices must have the resolving power of the imaging electron tubes used in current television broadcasting.
Therefore, there are 500 pieces in the vertical direction and 800 to 10 pieces in the horizontal direction.
A matrix of 00 picture elements (photoelectric conversion elements) and a corresponding scanning element are required. Therefore, the solid-state image sensing device is manufactured using MO8 large-scale circuit technology that requires high integration, and generally uses COD (MOS) transistors or the like as a component. FIG. 1 shows the basic configuration of a CCD type solid-state image pickup device featuring low noise tl. Reference numeral 1 designates a light conversion element such as a photodiode, and 2 and 3 designate a vertical COD shift register and a horizontal shift register for outputting optical signals accumulated in the photoelectric conversion element group to an output terminal 4. Reference numerals 5 and 6 are clock pulse generators that generate clock pulses for driving the vertical shift register and horizontal shift register, respectively. Although a two-phase clock pulse generator is illustrated here, either a four-phase or three-phase clock format may be adopted. Also,
Reference numeral 7 indicates a transfer gate that sends the charge accumulated in the photodiode to the vertical shift register 2. In its current form, this device becomes a black and white image sensor, but if a color filter is laminated on top, each party diode becomes a sicolor image sensor with color information.

As is well known, solid-state imaging devices have many advantages over electron tubes, such as being small, lightweight, maintenance-free, and low power consumption, and are expected to have a promising future as the next generation imaging device.

However, current CCD type elements produce afterimages due to the element structure, resulting in deterioration of image quality.

Despite the fact that solid-state devices did not produce afterimages compared to electron tubes, which was the claim from the beginning of the development of solid-state devices,
In reality, afterimages occur, and improvement is currently a major issue. Two methods have recently been proposed as means for preventing this afterimage. One is to lower the impurity concentration of the impurity layer for the photodiode (for example, lower it from the conventional no to n-).
, the impurity layer is completely depleted when reading charges (N.

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e Lag Pt1todiodeS1ructur
e in Ihe Interline ccI) Engineering imageSensor I ''' 1982IED, M
Tech, Dig, pp324-327). One more
One is that the photodiode is not a junction type as mentioned above, but an MIS structure (Metal Insulator Semi-COnd).
In this method, the diode (LICtOr) is completely depleted. Although it has become possible to reduce afterimages (unread charges) to some extent by these methods, it has been found that afterimages still occur and that there is a need to reduce this amount to a non-problematic level. The cause of this afterimage will be explained using FIG. 2, taking as an example a DDC element employing a junction type photodiode. FIG. 2(a) is a diagram showing the most commonly implemented planar layout configuration of the element shown in FIG. 1. 1 is a photodiode region, 2 is a transfer gate region, 2-1 is an electrode forming a vertical CCD (for example, the first layer of polycrystalline silicon), 2-2 is another electrode (for example, 2
layer of polycrystalline silicon). FIG. 2(b) shows one pixel of the layout shown in FIG. 2(a), and its new and old structures are shown in FIG. 2(C). 1 is a layer with a thin impurity concentration (for example, n-type) for the photodiode, 8 is a substrate (for example, p-type), and 2-4 is an impurity layer for making the COD a buried type (for example, n-type, making the COD a surface type). 9 is a thick oxide film that provides insulation separation between the painters (
For example, 8i0z). FIG. 2(d) shows the potential formed in each region of the structure shown in FIG. 2(C) when signal charges are read out. The signal charge (Qs + QR) accumulated in the junction capacitance of the photodiode during one field period (one frame period may also be used) is caused by the high voltage pulse applied to the transfer gate, and the potential under the transfer gate is lowered to the vertical CCD side. flows into. A part of the transfer gate extends to the photodiode side, so the channel width is W.

Wb is narrow in the 7-a region and wide in the 7-b region. Therefore, in the region 7-a where the channel width is small, an increase in the threshold voltage occurs due to the narrow channel effect, and the threshold voltage becomes higher than in the region 7-b (the increase in threshold voltage tΔV? do). As a result, even though the entire charge (Ql + QB) must be transferred to the CCD side during readout, the aforementioned potential wall ΔV
The charge (Q,) that cannot be transferred due to T remains on the photodiode side, and this remains @! wo occurs. This unread amount QR depends on the channel width W, and if the number of pixels increases in the future (that is, if you try to increase the resolution)
W will inevitably have to be made narrower than it is now, and Q will become larger and larger. Therefore, this problem will become even more severe in the future than it is now, and solving this problem will be a major challenge for the practical application of solid-state devices.

[Purpose of the invention]

An object of the present invention is to prevent the occurrence of afterimages, that is, to improve the device structure shown in FIG.

[Summary of the invention]

In order to achieve the above object, the present invention improves the planar configuration of the transfer gate so that changes in the threshold voltage due to the narrow channel effect do not occur under the transfer gate, and potential walls that cause unread charges are generated. This is to ensure that this does not occur.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in detail using examples.

In the CCD type element of the present invention, whether the photodiode is a junction type or an MI
The planar configuration differs slightly depending on whether it is S type or not. Further, the structure differs slightly depending on whether the electrodes constituting the transfer gate are shared with the vertical COD or formed independently. Therefore, these four cases will be classified and explained in the following embodiments.

1. In case of junction type photodiode.

1) When the transfer gate electrode is shared with the vertical CCD electrode.

FIG. 3 shows an example of the planar configuration of the CCD type element of the present invention and the potential under the transfer gate during readout. 1 is a photodiode made of, for example, an n-type impurity layer; 2-
Reference numeral 1 is, for example, a first layer (or, for example, a second layer) of polycrystalline silicon, which forms the vertical CCD 2-3 and the transfer gate electrode 7. The channel width W of the transfer gate is the same at any location in the transfer gate region 7, and the potential under the transfer gate at the time of reading is constant φd at any location. Therefore, in the device having the planar configuration of the present invention, no potential barrier is generated under the transfer gate, and the signal charge Q8 accumulated in the photodiode during one field period (-!1 frame period) is not generated. All vertical C through the transfer gate
Read out into CD. At the same time as the readout of charges is completed, the potential of the photodiode is reset to φd, and signal charges for the next field (or frame) are accumulated.

FIG. 4 shows another example of the planar configuration of the CCD type element of the present invention. The transfer gate electrode is formed by the first and second layer electrodes 2-1 and 2-2, which are shared with the vertical COD electrode, and the channel width is the same W everywhere. Therefore, the signal charge Q8 is 2-1 and 2-2
All the signals are read out into the vertical CCD at a low potential φV through the transfer gate 7 formed by φV. After the readout is completed, the photodiode potential is reset to the potential φte under the transfer gate at the time of readout, and the signal 4 for the next field (or frame) is reset.
(, 4 loads start to accumulate.

FIG. 5 shows another example of the flat-strike configuration of the CCD type element of the present invention. The transfer gates are vertical + a, C as in the case of Fig. 3.
1st rv shared with OD! However, the electrode that forms the transfer gate does not extend to the photodiode region (the wide part) and stops at the narrow part. Therefore, 1' including the narrow width region is the n-impurity layer for the photodiode, and the channel width is the same value W at any point θ in the transfer gate region.
will be prepared. As a result, the signal charge Qs can be placed above the transfer gate and read out vertically into the CCD.

11) When the transfer gate is configured with poles separate from the vertical CCD.

FIG. 6 shows a case where the electrode forming the transfer gate is formed vertically COD' independently of the pole, and the transfer gate electrode is formed of, for example, the third layer of polycrystalline silicon. In this case vertical C
The 0Dt pole will be formed by the first J- and second layer polycrystalline silicon. Here, the figure (a) is the third
In the case of Figure 4, the same figure (b) is the case of Figure 4, the same figure (C)
corresponds to the case in FIG. The element structure in this configuration is shown in FIG. 10(d), taking the case of FIG. 10(a) as an example.

(al, (bL (cl) In either configuration, the channel width forming the transfer gate is constant W. Therefore, as in the read operation shown in FIGS. 3 to 5, the signal charge QII is Everything can be read out into the vertical CCD through the transfer gate 7' (the potential at the time of readout is shown in FIGS. 3, 4, and 5).
It is the same as b), so it is omitted).

2. In case of MIS type photodiode.

The transfer gate electrode may be shared with the vertical COD or may be independent. Here, in order to avoid duplication of drawings of the same type, a case will be shown in which the transfer gate electrode is shared with the vertical COD% pole.

Fig. 7 corresponds to the above-mentioned Fig. 3;
This is an example (planar configurations corresponding to FIGS. 4 and 6 are omitted). The figure (a) shows a planar configuration, and the transfer gate has a constant value Wt in any field 9. 1"-1 indicates a region where a photodiode is formed, and as shown in the structure of the same figure (b), a thin oxide film 1
Transparent poles 1''-2 are formed on the entire surface through 0.

When a predetermined t-pressure vL is applied to the transparent electrode 1''-2, a depletion layer 1''-3 spreads on the surface of the semiconductor substrate 8, and signal charges Q8 are accumulated in this portion. When accumulating a signal, the potential under the multi-photodiode is set to φb by applying the voltage Vs, and when reading out the signal, the potential under the transfer gate is lowered to φb, and at the same time, by applying vH to the transparent electrode, the potential under the multi-photodiode is set to φb. The lower potential rises to φE. As a result, all signal charges Qs can be read out into the vertical CCD via the transfer gate.

In the case of an MIS type photodiode, a planar configuration corresponding to FIG. 4 can be obtained, but a planar configuration corresponding to FIG. 5 cannot be obtained. This is because a potential wall as explained in Fig. 2 occurs and unread charges occur.As an alternative to the planar configuration equivalent to Fig. 5,
17 configurations are possible. In the configuration shown in the figure, the layout is such that the end of the transfer gate electrode on the photodiode side matches (exists on the same line) the end of the photodiode on the vertical CCD side. However, W is the same, so no potential wall is generated, and the accumulated charge Qs of the photodiode can be completely taken into the vertical CCD via the transfer gate 7.

〔Effect of the invention〕

According to the present invention, unread signal charges can be completely eliminated, and the present invention is extremely valuable in preventing the occurrence of afterimages. Furthermore, as mentioned above, the present invention also has a planar configuration of the element (
Since this can be realized by improving the layout (layout), it can be manufactured using the same process as the conventional method, and there is no concern that the yield D' will decrease.

Further, according to the present invention, the following secondary effects can be obtained, and the performance of the CCD type image sensor can be greatly improved.

(Since the alignment accuracy of the photomasks used to manufacture the 11 elements is much looser than in the past, it is possible to shorten the manufacturing time and improve the manufacturing yield.

In addition, uniform characteristics can be obtained regardless of whether the bonding is successful or not.

(2) Since the area of the photodiode can be increased (that is, the signal frost and load storage capacity of the photodiode can be increased), the dynamic range of the element for incident light can be expanded, or A stone that can reduce pixel size (improve resolution). However, the fifth
As for the embodiments shown in Fig. 7 and Fig. 7, this effect is not so strong.
This is about the same as in the case of conventional elements.

(Since the channel width becomes practically larger, the charge readout time can be shortened. Also, the voltage at the time of readout can be lowered. (In conventional elements, a high voltage is applied to the transfer gate at the time of readout.) (This obstructs lower voltage.)

(4) Since the shape of the photodiode is simple and the perimeter length of the edge is shortened, the dark current generated in the photodiode section can be reduced. Wow, that's about the same as in the case of the conventional element.

[Brief explanation of drawings]

FIG. 1 is a diagram showing the basic configuration of a conventional CCD type image sensor.
FIG. 2 is a diagram showing the pixel configuration of a conventional CCD type image sensor and blocking points therebetween, FIG. 3, and FIG. 5, 6, 7 and 8 are CCDs of the present invention.
FIG. 2 is a diagram showing a pixel configuration of a type image sensor and a complete readout operation of charges. 1... Photodiode, 2-1... Polycrystalline silicon,
2-3... Vertical CCD electrode, 7... Transfer gate electrode, W(C) (d) vi Z Figure 3 s'fJ4 Figure 2-/'fJ 5 Figure 2-+ tth 7th Figure Z-/

Claims (1)

[Claims] 1. On the same semiconductor substrate, a group of photodiodes and a vertical CO
A group of D shift registers, a transfer gate that reads out the signal charges accumulated in the photodiodes to the vertical COD, and a horizontal CC that outputs an excessive amount of the signal charges sent by the vertical CCD group to the output.
A charge transfer type solid-state image sensor integrated with a D shift register, characterized in that the channel width of the channel region in which the transfer gate is formed is the same at any location in the transfer gate region. Solid-state image sensor. 2. The charge transport type solid-state imaging device according to claim 1, characterized in that the transfer gate is composed of electrodes of a plurality of layers that are shared with electrodes of a plurality of layers forming the vertical COD shift register. Charge transfer solid-state image sensor.