JPS60202956A - 回路モジユ−ル - Google Patents

回路モジユ−ル

Info

Publication number
JPS60202956A
JPS60202956A JP59058240A JP5824084A JPS60202956A JP S60202956 A JPS60202956 A JP S60202956A JP 59058240 A JP59058240 A JP 59058240A JP 5824084 A JP5824084 A JP 5824084A JP S60202956 A JPS60202956 A JP S60202956A
Authority
JP
Japan
Prior art keywords
circuit module
fins
heat dissipation
heat
dummy
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP59058240A
Other languages
English (en)
Inventor
Bunichi Tagami
田上　文一
Yutaka Watanabe
裕 渡辺
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP59058240A priority Critical patent/JPS60202956A/ja
Publication of JPS60202956A publication Critical patent/JPS60202956A/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
    • H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
    • H01L23/367—Cooling facilitated by shape of device
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/03—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes
    • H01L25/10—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers
    • H01L25/105—Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2225/00—Details relating to assemblies covered by the group H01L25/00 but not provided for in its subgroups
    • H01L2225/03—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00
    • H01L2225/10—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers
    • H01L2225/1005—All the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/648 and H10K99/00 the devices having separate containers the devices being of a type provided for in group H01L27/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/10—Details of semiconductor or other solid state devices to be connected
    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
    • H01L2924/15312—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a pin array, e.g. PGA
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/153—Connection portion
    • H01L2924/1532—Connection portion the connection portion being formed on the die mounting surface of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/161—Cap
    • H01L2924/1615—Shape
    • H01L2924/16152—Cap comprising a cavity for hosting the device, e.g. U-shaped cap

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Chemical & Material Sciences (AREA)
  • Materials Engineering (AREA)
  • Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。

Description

【発明の詳細な説明】 〔発明の利用分野〕 本発明は集積回路モジュールを冷却するのに好適な放熱
フィンの取り付けた回路モジュールに関する。
〔発明の背景〕
最近、リードレスチップキャリア（ＬＣＣ）等によシ集
積回路用パッケージの小型化が図られている。それに伴
ない、複数の集積回路素子を搭載した回路モジュールの
実現が可能となってきた。
通常、かような回路モジュールは第１図の如き構造を有
する。１は回路素子を搭載する配線基板、２はＬＣＣ等
のパッケージ、３はパッケージに取シ付けた放熱フィン
、４はモジュールを他のレベルと接続するだめのリード
である。
ここで、部品搭載数が多くなってくると、予め用意され
た位置線てに搭載されるとは限らず、未搭載部が生じる
場合がある。放熱フ・ｆンは個個のパッケージに取り付
けるので、未搭載部にはフｆンが無いことになる。この
状態を示したのが第２図である。
搭載する素子により発熱量が違う場合には、発熱量の大
きい方から小さい方へ熱の流れが生じ、発熱量の小さい
方の放熱フィンは大きい方の熱の放散にも寄与している
ことになる。配線基板にセラミック基板等の熱伝導率の
小さい基板を用いた場合には上記の効果がとくに顕著と
なる。ここで未搭載部品が生じた場合、とくに発熱量の
小さい部品を搭載しなかった場合には未搭載部に相当す
る放熱フ、ｆンの熱放散効果が期待できなくなり、搭載
した半導体素子のジャンクション温度の上昇を招き、ひ
いては装置の信頼性を損なうことになる。
また、放熱フＣンが無い部分は風の抵抗が小さくなるた
め、風がフ、【ンの無い部分に集中す。
る。このことは、熱を放散させたいフｆンに十分な風が
当らないことを意味しており、冷却性能が損なわれる結
果となる。
〔発明の目的〕
本発明の目的は、放熱フ・ｆンと付けた複数の回路部品
よシ成る回路モジュールにおいて、部品搭載可能領域の
一部にしか部品を搭載しない場合でも、十分に熱放散性
が良い回路モジエールを提供することにある。
〔発明の概要〕
本発明は、複数の集積回路素子を搭載する回路モジュー
ルにおいて、部品を搭載しない部分にも放熱フィンを取
９つけることを特数とするものである。
〔発明の実施例〕 以下、本発明の一実施例を第６図によシ説明する。第３
図において、１はセラミック配線基板、２は半導体集積
回路素子を実装したチップキャリア、３はチップキャリ
アに取シつけた放熱フ・１ン、４は信号の接続および電
源の給電のためのリード、１０は部品の代シに搭載した
ダご一フィンである。各素子で発生した熱は主に放熱フ
ィン３から放散されるが、一部分は配線基板１を伝わっ
てダミーフィンから放散される。
とくに、大電力素子では後者の割合が高くなる。
従来の様に部品が搭載されない場合にはフＣンも取り付
けられない場合においては、大電力素子の熱放散の一部
を担っていたフＣンを取り除く場合が生じ、放熱面積の
減少を招いていた。
本発明に従がい、部品が搭載されない部分にも放熱フィ
ンを椴シ付けることで、放：Ａ面積の確保が可能となり
安定した冷却性能を得ることができる。このことは、半
導体素子のジャンクション温度を一定限度以下に保つこ
とが可能であることを意味しておシ、装置の信頼性の確
保に効果がある。
第４図は、他の実施例の断面図を示している。
第４図において、５は配線基板１に直接取り付けた半導
体素子チップである。チップは金シリコン共晶等によシ
基板にロウ付されておシ、素。
子５で発生した熱は基板を介して反対面の放熱フィンか
ら放散される。このような構造の回路モジュールでは、
本発明の効果がより一層顕著となる。
〔発明の効果〕
本発明によれば、複数の半導体素子からなる回路モジュ
ールにおいて、部品の未搭載領域が発生する場合でもダ
ミー放熱フィンを取り付けることで十分な放熱面積を確
保することができるので、装置の信頼性を確保する上で
十分低いジャンクション温度に設定できる効果がある。
【図面の簡単な説明】
第１図は複数の素子から成る回路モジュールで第１図１
ａ＋が平面図、（Ａ）が正面図、第２図は未搭載領域が
生じた回路モジュールの平面図、第３図は発明の一実施
例を示す平面図、第４図は本発明の他の実施例を示す断
面図である。 １・・・配線基板　２・・・パッケージ６・・・放熱フ
ーｆン　４・・・リード５・・・半導体チップ　１０・
・・ダミー放熱フ・ずン 代理人弁理士　高　橋　明　夫 第　１　図 第２　図 第３　図 箋　４−　図

Claims (1)

    【特許請求の範囲】
  1. 放熱フィンを取シ付けた複数の半導体集積回路部品を基
    板上に搭載して成る回路モジュールにおいて、部品搭載
    可能領域の一部にしか部品を搭載しない場合にも、空き
    領域には放熱７ｃンを取シ付けたことを特徴とする回路
    モジュール０
JP59058240A 1984-03-28 1984-03-28 回路モジユ−ル Pending JPS60202956A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59058240A JPS60202956A (ja) 1984-03-28 1984-03-28 回路モジユ−ル

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59058240A JPS60202956A (ja) 1984-03-28 1984-03-28 回路モジユ−ル

Publications (1)

Publication Number Publication Date
JPS60202956A true JPS60202956A (ja) 1985-10-14

Family

ID=13078577

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59058240A Pending JPS60202956A (ja) 1984-03-28 1984-03-28 回路モジユ−ル

Country Status (1)

Country Link
JP (1) JPS60202956A (ja)

Cited By (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600590A1 (en) * 1992-12-03 1994-06-08 International Computers Limited Cooling electronic circuit assemblies
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6624507B1 (en) 2000-05-09 2003-09-23 National Semiconductor Corporation Miniature semiconductor package for opto-electronic devices
US6642613B1 (en) 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US6707140B1 (en) 2000-05-09 2004-03-16 National Semiconductor Corporation Arrayable, scaleable, and stackable molded package configuration
US6710443B1 (en) * 2002-12-20 2004-03-23 Texas Instruments Incorporated Integrated circuit providing thermally conductive structures substantially horizontally coupled to one another within one or more heat dissipation layers to dissipate heat from a heat generating structure
US6765275B1 (en) 2000-05-09 2004-07-20 National Semiconductor Corporation Two-layer electrical substrate for optical devices
US6767140B2 (en) 2000-05-09 2004-07-27 National Semiconductor Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired ceramic) technology
US6916121B2 (en) 2001-08-03 2005-07-12 National Semiconductor Corporation Optical sub-assembly for optoelectronic modules
US6973225B2 (en) 2001-09-24 2005-12-06 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package
US7023705B2 (en) 2001-08-03 2006-04-04 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US7156562B2 (en) 2003-07-15 2007-01-02 National Semiconductor Corporation Opto-electronic module form factor having adjustable optical plane height
US7269027B2 (en) 2001-08-03 2007-09-11 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules

Cited By (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0600590A1 (en) * 1992-12-03 1994-06-08 International Computers Limited Cooling electronic circuit assemblies
US6084308A (en) * 1998-06-30 2000-07-04 National Semiconductor Corporation Chip-on-chip integrated circuit package and method for making the same
US6838317B2 (en) 2000-05-09 2005-01-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US7199440B2 (en) 2000-05-09 2007-04-03 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US6707140B1 (en) 2000-05-09 2004-03-16 National Semiconductor Corporation Arrayable, scaleable, and stackable molded package configuration
US7432575B2 (en) 2000-05-09 2008-10-07 National Semiconductor Corporation Two-layer electrical substrate for optical devices
US6765275B1 (en) 2000-05-09 2004-07-20 National Semiconductor Corporation Two-layer electrical substrate for optical devices
US6767140B2 (en) 2000-05-09 2004-07-27 National Semiconductor Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired ceramic) technology
US6624507B1 (en) 2000-05-09 2003-09-23 National Semiconductor Corporation Miniature semiconductor package for opto-electronic devices
US7247942B2 (en) 2000-05-09 2007-07-24 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US6642613B1 (en) 2000-05-09 2003-11-04 National Semiconductor Corporation Techniques for joining an opto-electronic module to a semiconductor package
US7086786B2 (en) 2000-05-09 2006-08-08 National Semiconductor Corporation Ceramic optical sub-assembly for opto-electronic module utilizing LTCC (low-temperature co-fired ceramic) technology
US7086788B2 (en) 2001-08-03 2006-08-08 National Semiconductor Corporation Optical sub-assembly for opto-electronic modules
US7023705B2 (en) 2001-08-03 2006-04-04 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US6916121B2 (en) 2001-08-03 2005-07-12 National Semiconductor Corporation Optical sub-assembly for optoelectronic modules
US7269027B2 (en) 2001-08-03 2007-09-11 National Semiconductor Corporation Ceramic optical sub-assembly for optoelectronic modules
US6973225B2 (en) 2001-09-24 2005-12-06 National Semiconductor Corporation Techniques for attaching rotated photonic devices to an optical sub-assembly in an optoelectronic package
US6710443B1 (en) * 2002-12-20 2004-03-23 Texas Instruments Incorporated Integrated circuit providing thermally conductive structures substantially horizontally coupled to one another within one or more heat dissipation layers to dissipate heat from a heat generating structure
US7156562B2 (en) 2003-07-15 2007-01-02 National Semiconductor Corporation Opto-electronic module form factor having adjustable optical plane height

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