JPS60201781A - Display device - Google Patents

Abstract

PURPOSE:To make good display using simple constitution by generating clock signals of specified frequency basing on synchronizing signals separated from video signals and controlling reading of a memory by this clock. CONSTITUTION:Horizontal synchronizing signals from a separating circuit 4 are supplied to a phase detector 13, an LPF14 and a variable frequency oscillator (VCO), and frequency signals equal to horizontal synchronizing signals from the VCO15 are supplied to the second PLL circuit consisting of a phase detector 5, an LPF6, a VCO7, a frequency dividing circuit 8 and a control circuit 9. Sensitivity of the VCO15 that forms the first PLL is set small, and the phase detector 13 is constituted to have sensitivity only for phase, and the phase detector 5 is made to have sufficient sensitivity not only for phase but also for frequency. Thus, output of the second PLL becomes very stable, and good display is made by reading the memory by this picture clock.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention superimposes images such as characters from a so-called microcomputer onto the screen of a bidet No. 118 from the outside.
The present invention relates to a display device for displaying images.

BACKGROUND TECHNOLOGY AND PROBLEMS When displaying images such as characters from a so-called microcomputer on a screen of a video signal from the outside, it is necessary to extract a synchronization signal from the original video signal and extract this signal. Random access memory (V-RAM) for the output video of the microcomputer in conjunction with the synchronization signal
and mix it into the original video signal.

In Figure 1, an external video signal is input to the input terminal (1
), and this signal is taken out to the output terminal (3) through the switch circuit (2). In addition, the signal from the input terminal 11) is supplied to the sync separation circuit (4) and the vertical (V)
, horizontal (H)- synchronization signals are separated. This horizontal synchronization signal is supplied to the phase detector (5), and this detection output is passed through the low-pass filter (6) to generate variable frequency oscillation m (V
CO)+71. A signal having a frequency corresponding to a pixel clock for reading from the memory, which will be described later, is formed from this vCO(7). This number is supplied to a 1/)1 frequency dividing circuit (8) to form a character clock corresponding to each character, and this signal is supplied to a control circuit (9). This control circuit (9) divides the frequency of the above-mentioned signal,
An address signal corresponding to a position on the screen of one frame is formed. Further, a signal corresponding to the horizontal synchronizing signal is formed in the control circuit (9), and this signal is supplied to the phase detector (5) to apply so-called phase lock. Furthermore, a vertical synchronization signal from the separation circuit (4) is supplied to the reset terminal of the control circuit (9).

Also, the central processing circuit of a microcomputer (CCP U)
The code signal of the display character from the shout is ■-RAM (11)
and written to the desired address. This VR
AM (11) is read by the address signal from the control circuit (9).

A conversion circuit (12) converts this read data into a video signal.
and vc to this conversion circuit (12).

A pixel clock from (7) is supplied to form a ``C'' video signal. This signal is supplied to the switch circuit (2). Each display Il! from V-RAM (11) is also displayed. li
A signal corresponding to the prime period is supplied to the switch circuit (2), and a signal from the conversion circuit (12) is taken out to the output terminal (3) during this period.

In this way, images such as characters can be displayed superimposed on the screen of the external video signal.

However, in this device, the output frequency of the VCO (71) is from the current number to the number Mllz.On the other hand, since the frequency of the horizontal synchronization signal is as low as 15.73kHz, the stability of the phase-locked loop (PLL) This is especially true when the external video signal is the playback output of a VTR, and when still playback or double-speed playback is performed on this VTR, the PLL operation may be affected due to the occurrence of noise bars. There was a risk that the display would be disturbed and Masatomi would not be able to display it properly.

OBJECTS OF THE INVENTION In view of these points, it is an object of the present invention to provide an excellent display with a simple configuration.

Summary of the Invention The present invention provides a display device that displays an image from a memory by superimposing it on a video signal from an external source.
A synchronization signal separated from the video signal is supplied via a first PLL whose output frequency is equal to the synchronization signal to a second PLL whose output frequency is a predetermined clock frequency, and a clock from the second PLL is supplied. This is a display device in which a signal drives a circuit for controlling readout of the memory described above. According to this device, a good display can be performed with a simple configuration.

Embodiment In FIG. 2, a horizontal synchronizing signal from a separation circuit (4) is supplied to a phase detector (13), and the detected output is supplied to a VCO (15) through a low-pass filter (14). This VCO (15) generates a 4tR signal with a frequency equal to the above-mentioned horizontal synchronization f signal, and this signal is supplied to the phase detector (13) to be phase-locked. The signal is detected by the phase detector (5)
supplied to

In this device, a phase detector (13), a low-pass filter (14), and a VCO (15) are connected to the first (7) PLL.
is composed of a phase detector (5) and a low-pass filter (6).
), V CO (71, frequency divider circuit (8), control circuit (91
A near second PLL is configured. In this case, the VCO (15) constituting the first PLL is designed to have low sensitivity so that the frequency does not change easily, and the phase detector p (13) has only sensitivity to the phase, and is designed to be sensitive to the frequency. It has no sensitivity and is composed of, for example, an exclusive OR circuit or an analog multiplier. On the other hand, PL of 9A2
The phase detector (5) constituting L is assumed to have sufficient sensitivity not only to phase but also to frequency.

Therefore, in this device, the first PLL has no frequency sensitivity and is therefore less susceptible to external influences.
Even if there is a dropout of the synchronization signal due to a noise bar, the signal is stably output, and this signal has only information about the phase fluctuation of the synchronization signal. By using this signal to form a pixel clock in the second PLL, it is possible to obtain an extremely stable pixel clock, and this signal can be used to continuously read out the 'ζV-RAM (11). can.

In this way, it is possible to display images such as °C characters superimposed on the white surface of the video signal, but according to the above-mentioned device, the first PLL can generate a synchronization signal that is not affected by dropouts, etc. formed, and the second PL using this (No. 3)
Extremely stable I at L! II elementary clock can be obtained. In other words, in the conventional device, the PLL is 1 (Ilil), and the human input frequency and the output frequency are significantly different.
As mentioned above, PLL has no sensitivity to frequency fluctuations.
Although it is difficult to configure, according to the above-mentioned device,
By dividing the PLL into two, the input and output frequencies of the first PLL are made equal to realize a PLL that has no sensitivity to frequency fluctuations, and this output signal is used to create a stable PLL in the second PLL. It can obtain high frequency output.

Effects of the Invention According to the present invention, it has become possible to perform good display with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a diagram for explaining a conventional device, and FIG. 2 is a configuration diagram of an example of the present invention. (4) is a synchronous separation circuit, +51. +71 is the second PL
The phase detector and VCOl (9) constituting L are the control circuit, (11) is the V-RAM, (13) and (15) are the second
These are the phase detector and VCO that make up the PLL.

Claims (1)

[Claims] In a display device configured to display an image from a memory on the white side of an external video signal, a synchronization signal separated from the video signal is transmitted through a first PLL whose output frequency is equal to the synchronization signal. a second PLL whose output frequency is a predetermined clock frequency;
A display device in which a clock signal from L drives a circuit for controlling successive loading of the memory.