KR19990010447A - Time base correction device of video signal - Google Patents

Abstract

The present invention discloses an apparatus for calibrating time axis of an image signal. An apparatus for correcting a time axis of an image signal according to the present invention for correcting a time axis error of a complex video signal reproduced from an image reproducing apparatus includes a horizontal synchronization signal separator, a write clock generator, a read clock generator, an analog-digital converter, and a line memory. do. The horizontal synchronizing signal separator separates the horizontal synchronizing signal from the composite video signal. The recording clock generating unit inputs the horizontal synchronizing signal as a reference signal, and outputs a signal of a first frequency whose phase is synchronized with the reference signal as the recording clock. The read clock generator outputs a signal of a second frequency whose phase is synchronized with the reference signal as a read clock. The analog-digital converter converts a composite video signal into a digital signal using the recording clock as the sampling clock. The line memory stores the output of the analog-to-digital converter in response to the write clock, and outputs an image signal corrected for a time axis error in response to the read clock.

Description

Time base correction device of video signal

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to jitter attenuation of video signals, and more particularly, to an apparatus for correcting time axis of a video signal for correcting time axis error of a composite video signal reproduced from a video reproducing apparatus.

In general, the video signal reproduced from the video reproducing apparatus includes time axis fluctuations caused by the rotational stain of the drum or the running stain of the disk or tape. Therefore, when such a video signal is displayed on the screen as it is, the horizontal shake of the screen or the change in chromaticity occurs. A time base correction apparatus is a device that corrects a time base error of an image signal by synchronizing with a predetermined recording clock and a read clock when an unstable image signal is written to or read from the memory.

FIG. 1 is a block diagram illustrating a conventional time-base calibration apparatus used for a laser disk player (LDP), which is an analog-to-digital converter (ADC) 104, a horizontal synchronization signal. (HSYNC: Horizontal Synchronous signal) separator 106, phase-locked loop (PLL) 108, servo controller 110, and line memory 112.

Referring to FIG. 1, the composite video signal reproduced by the image reproducing apparatus 102 is stored in the line memory 112 via the analog-to-digital converter 104. At this time, the image signal is written to the line memory 112 in response to the write clock WCK, and is read from the line memory 112 in response to the read clock RCK.

Here, the write clock WCK is generated via the horizontal synchronizing signal separator 106 and the phase synchronizing loop 108. In brief, the horizontal synchronizing signal separator 106 separates the horizontal synchronizing signal HSYNC from the composite video signal output from the analog-digital converter 104. The phase locked loop 108 inputs a horizontal sync signal HSYNC as a reference signal and outputs a signal of a constant frequency whose phase is synchronized with the reference signal, where the constant frequency is, for example, 4 of the color subcarrier frequency fsc. 4fsc. The output of the phase locked loop 108 is used as the above described write clock WCK. In addition, the read clock RCK uses a signal of 4fsc 'output from an external crystal oscillator (not shown).

In addition, the servo controller 110 shown in FIG. 1 compares the above-described horizontal synchronization signal HSYNC and the phases of the reference horizontal synchronization signal REF_HSYNC input from another phase synchronization loop (not shown), and compares the phase differences. Correspondingly, a horizontal synchronization error signal HSYNC_ERR is generated. The horizontal synchronizing error signal HSYNC_ERR is outputted to the video reproducing apparatus 102 again to synchronize with the whole by adjusting the rotational speed of the disc.

According to the conventional time-base calibration apparatus described above, the write and read clocks WCK and RCK of the line memory 112 are each made and used independently of the phase locked loop 108 and the crystal oscillator (not shown). The limitation of this time base calibration device is that it is expensive in price. That is, it is expensive to use for other video reproducing apparatus as a time base correcting apparatus used for LDP. In addition, the servo controller 110 is operable only when it is a master, and has a disadvantage in that it is difficult to operate as a slave when applied to a video tape recorder and a camcorder.

SUMMARY OF THE INVENTION The present invention has been made in an effort to provide a device for correcting a time axis of an image signal, which can be reduced in cost by a simple circuit configuration and applicable to not only a specific image reproducing apparatus but also a general image reproducing apparatus.

1 is a block diagram for explaining a conventional time base correction apparatus used in a laser disc player.

2 is a block diagram of a preferred embodiment of an apparatus for correcting a time base of an image signal according to the present invention.

3 is a detailed block diagram of the first phase locked loop shown in FIG.

FIG. 4 is a diagram illustrating frequency characteristics of the first phase locked loop shown in FIG. 2.

FIG. 5 is a diagram illustrating frequency characteristics of the second phase locked loop shown in FIG. 2.

In order to achieve the above object, a time axis correction apparatus of a video signal according to the present invention for correcting the time axis error of a composite video signal reproduced from a video reproducing apparatus includes a horizontal synchronization signal separator, a recording clock generator, a read clock generator, an analog- It is preferably composed of a digital converter and a line memory. The horizontal synchronizing signal separator separates the horizontal synchronizing signal from the composite video signal. The recording clock generating unit inputs the horizontal synchronizing signal as a reference signal, and outputs a signal of a first frequency whose phase is synchronized with the reference signal as the recording clock. The read clock generator outputs a signal of a second frequency whose phase is synchronized with the reference signal as a read clock. The analog-digital converter converts a composite video signal into a digital signal using the recording clock as the sampling clock. The line memory stores the output of the analog-to-digital converter in response to the write clock, and outputs an image signal corrected for a time axis error in response to the read clock.

Hereinafter, a configuration and an operation of an apparatus for calibrating a time base of an image signal according to the present invention will be described with reference to the accompanying drawings.

FIG. 2 is a block diagram of a preferred embodiment of an apparatus for correcting a time base of an image signal according to the present invention, in which a first phase locked loop (first PLL) used as a horizontal sync signal (HSYNC) separator 202 and a write clock (WCK) generator is shown in FIG. 204, a second phase locked loop (second PLL) 206 used as a read clock (RCK) generator, an analog-to-digital converter (ADC) 208, and a line memory 210.

The time axis correcting apparatus shown in FIG. 2 inputs a composite video signal reproduced from an arbitrary image reproducing apparatus (not shown) through the input terminal IN. Here, any video reproducing apparatus is a video tape recorder, for example, the composite video signal is reproduced by the rotation of the drum and the running of the tape, and when the rotation of the drum is changed, the speed of the tape is changed, and the data is read from the tape. Various factors, such as the change of position of, cause deviation in the time axis and do not have a constant period. In the concept of frequency, it means that the frequency of a signal representing information of one pixel, one horizontal synchronization, or one field changes. If such a composite video signal is displayed on the video screen as it is, it causes a shake of the screen, thereby degrading the picture quality.

Therefore, the composite video signal passes through a time axis correction apparatus as shown in FIG. 2 as a preprocessing step for improving image quality before being displayed on an image screen.

Referring to FIG. 2, the analog-digital converter 208 inputs a composite video signal reproduced through the input terminal IN, and converts the signal into a digital signal in response to a sampling clock. Here, the sampling clock uses a signal of 4fsc output from the first phase locked loop 204 which will be described later.

The digitalized composite video signal is stored in the line memory 210 in response to the write clock WCK, and then read out from the line memory 210 in response to the read clock RCK. Here, the write clock WCK is generated at an inequal interval because the composite video signal having a time axis fluctuation must be stored in the line memory 210 without loss, whereas the read clock RCK is a complex stored in the line memory 210. It is generated at equal intervals so as to substantially eliminate the time axis variation of the video signal.

The line memory 210 shown in FIG. 2 may use dual port random access memory (RAM) or two single port RAMs selected by a multiplexer.

The horizontal sync signal separator 202 separates the horizontal sync signal HSYNC from the composite video signal. At this time, since the horizontal synchronizing signal HSYNC is separated from the composite video signal reproduced during recording on the recording tape, the horizontal synchronizing signal HSYNC is an unstable signal whose period is not constant like the composite video signal.

The first phase synchronization loop 204 inputs the above-described horizontal synchronization signal HSYNC as a reference signal, and outputs the signal of the first frequency whose phase is synchronized with the reference signal as the above-described recording clock WCK. Here, the first frequency 4fsc has a bandwidth wide enough to track the frequency of the horizontal synchronization signal HSYNC in consideration of the fact that the period of the horizontal synchronization signal HSYNC is not constant.

In addition, the second phase lock loop 206 inputs a horizontal sync signal HSYNC as a reference signal, similarly to the first phase lock loop 204, and describes a signal of a second frequency whose phase is synchronized with the reference signal. It outputs as a read clock RCK. Here, the second frequency 4fsc 'has a relatively narrower bandwidth than the aforementioned 4fsc.

The first and second phase locked loops 204 and 206 will now be described in detail.

FIG. 3 is a detailed block diagram of the first phase locked loop 204 shown in FIG. 2 with a phase detector 302, a loop filter 304, a voltage controlled oscillator (VCO) 306 and a clock divider. Period 308.

The phase detector 302 shown in FIG. 3 inputs a horizontal synchronizing signal HSYNC separated from the reproduced composite video signal as a reference signal, and the signal divided by the clock divider 308 to be described later as a comparison signal. Enter it. Phase detector 302 compares the phases of the two signals and generates an error voltage corresponding to the compared phase difference. That is, the larger the phase difference, the higher the voltage value is output, otherwise the relatively low voltage value is output. The loop filter 304 inputs the above-described error voltage and passes only a predetermined frequency or less.

The voltage controlled oscillator 306 outputs a signal of 4 fsc as the above-described write clock WCK in response to the output of the loop filter 304. Here, 4fsc is a frequency obtained by multiplying the horizontal frequency of the horizontal synchronization signal HSYNC input to the first phase synchronization loop 204 by a predetermined multiplication factor.

The clock divider 308 divides 4fsc at a predetermined frequency division to match the frequency with the reference signal of the phase detector 302 in feeding back the output of the voltage controlled oscillator 306 as a comparison signal of the phase detector 302. do. That is, the clock divider 308 is a frequency divider dividing 4fsc by the multiple of the output frequency of the first phase locked loop 204 by the multiple of the input frequency.

As described above, the first phase locked loop 204 has a bandwidth wide enough to output a signal of 4fsc. That is, it has a wide locking range by adjusting the characteristics of the loop filter 304 and the voltage controlled oscillator 306.

Since the horizontal sync signal HSYNC input to the first phase lock loop 204 is an unstable signal separated from the composite video signal, its horizontal frequency f _HSYNC is actually f _H ± Δf ₁ (where f _H is NTSC). In this case, 15.7 KHz, Δf ₁ , which is a normal horizontal frequency, may be represented by a variation component). A first phase locked loop (204) and outputs a signal 4fsc of a multiplier 910 to a horizontal frequency (f _HSYNC), reflecting a fluctuation component of such a horizontal frequency (f _HSYNC) as a writing clock (WCK). Therefore, the frequency f _WCK of the reference clock WCK may be represented by 910 (f _H ± Δf ₁ ).

Thus, when the write clock WCK is used as the sampling clock of the analog-to-digital converter 208 and used as the write clock WCK of the line memory 210, there is no loss of the composite video signal.

In addition, since the configuration of the second phase locked loop 206 is the same as the detailed block diagram of the first phase locked loop 204 shown in FIG. 3, the drawings are omitted. However, the 4fsc 'signal output from the second phase locked loop 206 has a relatively narrow bandwidth than 4fsc from the first phase locked loop 204. That is, it has a narrow locking range by adjusting the characteristics of the loop filter and the voltage controlled oscillator.

Since the horizontal synchronizing signal HSYNC input to the second phase synchronizing loop 206 is an unstable signal separated from the composite video signal like the first phase synchronizing loop 204, the horizontal frequency f _HSYNC is f _H ± Δf ₁ (where f _H is 15.7 KHz, Δf ₁ is a variation component) which is a normal horizontal frequency in the case of NTSC. The signals of the two phase-locked loop 206 first without substantially reflecting the variation component of the phase-lock the horizontal frequency (f _HSYNC) as compared to the loop 204, a horizontal frequency (f _HSYNC) to 910 multiply the 4fsc ' It outputs as a read clock RCK. Accordingly, the frequency f _RCK of the read clock RCK may be represented as 910 (f _H ± Δf ₂ ), where Δf ₂ is a stable frequency with less fluctuation than the aforementioned Δf ₁ .

Accordingly, when the digitalized composite video signal stored in the line memory 210 is read out in response to the read clock RCK of stable frequency by the above-described write clock RCK, the video signal from which the time axis error is removed is output. do.

4 is a diagram illustrating a frequency characteristic of the first phase locked loop shown in FIG. 2, and FIG. 5 is a diagram illustrating a frequency characteristic of the second phase locked loop shown in FIG. 2.

4 and 5, the characteristics of the first and second phase locked loops 204 and 206 can be clearly seen. In Figs. 4 and 5, the portions marked A and B, respectively, conceptually represent the locking range.

As illustrated in FIG. 4, the first phase synchronization loop 204 may be designed to have a wider locking range so that the frequency of the input horizontal synchronization signal HSYNC can be tracked as it is. It has a locking range of 15.7KHz ± 0.01KHz (f _H ± Δf ₁ ).

On the other hand, as shown in Figure 5, the second phase locked loop 206 can be designed to narrow the locking range so that only the center frequency can be obtained, the locking range is the locking of the aforementioned first phase locked loop 204 It has a value smaller than the range. Here, the center frequency refers to the center frequency of the reproduced horizontal synchronization signal HSYNC. The signal of 4fsc 'obtained by using the second phase locked rope 206 having the locking range shown in FIG. 5 has a constant frequency, so that an image signal output from the line memory 210 has a period of one horizontal synchronization. It is a constant signal.

In other words, in generating the read clock RCK, a time-base error caused by an unstable horizontal synchronizing signal during image display is eliminated by removing the variation component of the frequency included in the horizontal synchronizing signal HSYNC and making it a signal having a constant frequency. I can eliminate it.

As described above, the apparatus for calibrating the time base of an image signal according to the present invention generates the write and read clocks of the line memory by using two PLLs having the same input signal, thereby reducing the cost with a simple circuit configuration and providing an arbitrary image. There is an advantage applicable to the playback apparatus.

Claims (4)

An apparatus for correcting a time axis error of a complex video signal reproduced from an image reproducing apparatus, the apparatus comprising: a horizontal sync signal separator for separating a horizontal sync signal from the complex video signal; Recording clock generating means for inputting the horizontal synchronizing signal as a reference signal and outputting a signal of a first frequency at which phase is synchronized with the reference signal as a recording clock; Read clock generation means for outputting, as a read clock, a signal of a second frequency whose phase is synchronized with the reference signal; An analog-digital converter for converting the composite video signal into a digital signal using the recording clock as a sampling clock; And a line memory configured to store an output of the analog-digital converter in response to the write clock, and output an image signal corrected for a time axis error in response to the read clock. The method of claim 1, wherein the first frequency has a bandwidth wide enough that the composite video signal can be processed without loss in response to the recording clock, and the second frequency can correct a timebase error of the composite video signal. And a bandwidth narrower than the first frequency as much as possible. 2. The apparatus of claim 1, wherein the recording clock generating means comprises: a first phase detector for comparing a phase of the horizontal synchronization signal and a first divided signal and generating an error voltage corresponding to the compared phase difference; A first loop filter for filtering a DC component of the error voltage to output a control voltage; A first voltage controlled oscillator for generating a signal of the first frequency in response to the control voltage; And a first clock synchronizing loop for dividing the signal having the first frequency at a predetermined division rate and outputting the first divided signal. 2. The apparatus of claim 1, wherein the read clock generation means comprises: a second phase detector for comparing the phases of the horizontal synchronization signal and the second divided signal and generating an error voltage corresponding to the compared phase difference; A second loop filter for filtering a DC component of the error voltage and outputting a control voltage; A second voltage controlled oscillator for generating a signal of the second frequency in response to the control voltage; And a second clock divider for dividing the signal having the second frequency at a predetermined division rate and outputting the second divided signal. 2.