JPS60200350A - Memory control system - Google Patents

Abstract

PURPOSE:To mount memory elements different in type of performance into the same memory device and also to increase the memory capacity, by providing the function to a control circuit to change the memory access time according to the address information on a memory access. CONSTITUTION:A central controller CC receives the information on the write or read data to a memory MM. A memory control circuit MMC supplies an access to a memory circuit MEM via a bus MBO. When an access is fed to an extended memory EM, an access is fed to the memory circuit MEM of the memory EM from the circuit MMC via a bus MBO and an interface circuit IFO and then an interface circuit IF1 and a bus MB1. Therefore, the access time is increased by an amount equivalent to the intervention of interfaces IF0 and IF1 in comparison with a case where an access is supplied to the MEM of the MM. This difference of access time is detected by a control circuit MMC of the MM to change the access time.

Description

DETAILED DESCRIPTION OF THE INVENTION (Technical Field) The present invention relates to a memory control method for a memory device used in an information processing system.

(Prior Art) Memory devices used in conventional information processing systems operate with a fixed access time and have a fixed maximum memory capacity. For this reason, when expanding the memory capacity of a memory device, a method has been adopted in which a new memory device is added.

However, with this method, a new control circuit is added to account for the addition, and a memory device selection circuit and the like are added on the processing device side, resulting in a cine economy.

In addition, as a method that does not involve a control circuit,
One possible method is to add only the memory circuit to the memory device using a memory circuit expansion interface, but since conventional control circuits can only operate with one fixed access time, only the path delay and element delay associated with expansion are required. It had to be replaced with a new control circuit that increased access time.

On the other hand, in systems, there is a demand for data that does not require high speed to be stored in low speed but inexpensive memory elements, and data that requires high speed to be stored in expensive but high speed memory elements. This is aimed at making the memory device, which accounts for a large portion of the system cost, more economical. Conventionally, this requirement has been met by connecting a plurality of memory devices each equipped with memory elements of different performance and having different access times.

However, the only difference between the memory devices is that the access time of the control circuit is different; logically, they are exactly the same, so replacing the entire memory device for each type of memory element is only for the replaced memory device. The disadvantage is that the number of control circuits is increased, and a memory device selection circuit is also added on the processing device side, resulting in a cine economy.

(Purpose of the Invention) The present invention was made to solve these drawbacks, and by providing a control circuit with a function of changing memory access time based on memory access address information, memory elements with different performance can be used in the same manner. The memory capacity can be easily expanded within the same memory device by accommodating changes in access time depending on the mounting position of the memory element. This will be explained in detail below.

(Structure of the Invention) A memory device comprising a memory circuit for storing information and a memory control circuit for controlling data writing or reading with respect to the memory circuit, wherein the memory device receives address information for memory access from a central control unit. This is a memory control method characterized by the fact that the memory device operates at various memory access times set in advance.

(Embodiment) FIG. 1 is a block diagram of a first embodiment of the present invention. In FIG. 1, CC is a central control unit, MM is a memory device,
MMC is memory control circuit, MEM is memory circuit, MBO
is the memory/JS in the memory device, Ill is an interface circuit that connects the memory/JS of the memory device to the expansion memory device, EM is the expansion memory device, and F1 is an interface circuit that connects the expansion memory device from the memory device. ,M
Bl is a memory space within the expanded memory device. The central control unit CC sends address information, write data information, and activation signals to the memory device MM. It sends out a write signal or the like to perform a write operation, or it sends out address information, a start signal, a read signal, etc. to receive read data information.

The memory control circuit MMC creates various memory control timings and accesses the memory circuit MEM i of the memory device MM via the memory path MBO. When accessing the extended memory device EM, the memory path MBθ and the interface circuit I are connected from the memory control circuit MMC of the memory device MM.
Interface circuit F1 of expansion memory device EM via FOf, expansion memory device E via memory path MB1f
The memory circuit MEM of M is accessed.

Note that when accessing the memory circuit MEM of the expanded memory device EM, the interface circuit I of the memory device MM is used.
FO and expansion memory device EM interface circuit I
Since the access is made via F7f, the access time becomes longer by the amount of access via the interface circuits IF+7 and IFIf compared to when accessing the memory circuit MEMi of the memory device MM.

In the present invention, this difference in access time is calculated from the memory device MM.
The memory access time is detected by the memory control circuit MMC, and the memory access time can be varied.

The operation of memory control circuit MMC will be explained using FIG. 2. FIG. 2 shows a part of the memory control circuit MMC.

In FIG. 2, 1 is the memory path MBO of the memory device MM.
7°, 2 and 3 are flip-flops for sending the memory response signal DACK' (z) back to the central controller CC, and 4 is a column address strobe signal (CAS).
), 5 is a refresh counter, 6 is an address multiplexer, and 7 is a memory access time determination circuit.

Next, the operation of the circuit shown in FIG. 2 will be explained. First, when the memory access activation signal ADS is sent from the central control unit CC together with address information and data information, it is latched by the memory access activation signal ADSi, and the memory Send RAS signal and CAS signal to path MBO.

The RAS signal is also sent to the memory access time determination circuit 7 at the same time. The memory access time determination circuit 7 determines the memory access time set in advance based on the difference in mounting position from the memory address information, and
A memory access completion signal MOK is sent out according to the memory access time determination value from the signal.

When the memory access completion signal MOK is sent out, the 7 lip-flops 2 and 3 are set and send back the memory response signal DACKi to the central control unit CC.

Figure 3 shows the time chart of the present invention.
(1) in the figure is a time chart of the minimum memory access time. Here, the memory device operates with four clocks having the same clock cycle (herein referred to as e).

Also, these four clocks are used here as ill, II[.

It is expressed as ■.

Access to the memory circuit MEM of the memory device MM shown in FIG. 1 operates according to the time chart shown in FIG. 3(1).

The time chart shown in (2) in FIG. 3 is a time chart in which the memory access takes one clock cycle (1e), and the access to the memory circuit MEM in the expansion memory device EM shown in FIG. 1 is shown in FIG. It operates according to the time chart in (2).

FIG. 4 shows an embodiment in which the memory capacity is further expanded. The expansion memory device EM1 has an interface circuit IF.
The memory can be easily expanded by connecting it to the interface circuit IF (7) via the extended memory bus EMBOf or by connecting it to the interface circuit IF7 via the extended memory path EMB1'.

At this time, access to the expanded memory device FMJ can be performed using the same time chart shown in FIG. 3 (2) as described above.

FIG. 5 is a block diagram when n expansion memory devices are connected. EMo-EMn is an expansion memory device that allows a plurality of expansion memory devices to be connected from the interface circuit of the memory device MM.

The other components are the same as those described in connection with the configuration of FIG.

Even in the case shown in FIG. 5, the memory mounting position is determined based on the address information from the central control unit CC in the same manner as described above, and if the access device is an expanded memory device, the memory device M is
By lengthening the access time for M by one clock cycle (1e), it is possible to sequentially connect extended memory devices to memory device MM.

FIG. 6 is a block diagram showing a second embodiment of the present invention. In FIG. 6, MEM. .about.MEM are memory circuits having different access times.Other components are the same as those described in FIG. 1. Similarly to the first embodiment, the memory control circuit MMC determines the access time based on address information and controls the access time, thereby making it possible to mount memory cards with different access times in the same memory device. It is.

By adopting the control method described above, it is possible to apply multiple memory elements with different speeds in the same system with a small amount of additional hardware without having to install new memory devices, and the overall capacity expansion is possible. It can be easily done. This has the advantage that it is possible to easily store data that requires high speed in a high speed memory element, and to store data that requires low speed in a low speed memory element, thereby making it possible to construct an economical system.

(Effects of the Invention) The present invention relates to a memory control method for memories with different access times, and has the advantage that memory elements can be selected according to the required data speed, and that memory elements with different performances can be installed in the same memory device. It has the advantage that the memory capacity can be easily expanded within the same memory device by responding to changes in access time depending on the mounting position of the memory element, so it can be used for memory control of processing systems such as general electronic computers.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the connection of the memory device and expansion memory device of the present invention, FIG. 2 is a diagram showing a part of the memory control circuit of the present invention, and FIG. 3 is a time chart showing the operation of the memory control circuit of the present invention. ), Figures 4 and 5 are expansion memory device connection block diagrams showing one embodiment of the present invention, and Figure 6 is a block diagram showing another embodiment of the present invention when different speed memories are mounted in the same memory device. figure. CC...Central control unit, MM...Memory device, MM
C...Memory control circuit, MBO...Memory path in memory device, MEM...Memory circuit, IFO, IFI
, IF2...interface circuit, MBl...memory path in extended memory device, EM...extended memory device, ADS...memory access activation signal, DACK...
・Memory response signal, MOK,...Memory access completion signal, MEMo-MEMn...Memory circuits with different access times, 4...Delay circuit, 5...Refresh circuit, 6...Address multi-branch Fusa circuit, 7...Memory access time determination circuit. Patent applicant Okinemiki Kogyo Co., Ltd. Nippon Telegraph and Telephone Public Corporation 1 Display of the case 1982 Patent Application No. 055292 2 Name of the invention Memory control method 3゜Relationship with the case of the person making the amendment Patent applicant 6 The amendment Contents (1) rRAs'J on page 6, line 8 of the specification is corrected to r RAS J. (2) Correct the drawing “Figure 5” as shown in the attached sheet.

Claims (1)

[Claims] In a memory device comprising a memory circuit that stores information and a memory control circuit that controls data writing or data reading with respect to the memory circuit, the memory device has a memory access control circuit that controls memory access address information from a central control unit in advance. A memory control method characterized by operating at various set memory access times.