JPS60198895A - Method of producing multilayer printed circuit board - Google Patents

Method of producing multilayer printed circuit board

Info

Publication number
JPS60198895A
JPS60198895A JP5654484A JP5654484A JPS60198895A JP S60198895 A JPS60198895 A JP S60198895A JP 5654484 A JP5654484 A JP 5654484A JP 5654484 A JP5654484 A JP 5654484A JP S60198895 A JPS60198895 A JP S60198895A
Authority
JP
Japan
Prior art keywords
resist
plating
multilayer printed
electroless plating
electroless
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5654484A
Other languages
Japanese (ja)
Inventor
岡村 寿郎
▲つる▼ 義之
昭士 中祖
魚津 信夫
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Lincstech Circuit Co Ltd
Original Assignee
Hitachi Chemical Co Ltd
Hitachi Condenser Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd, Hitachi Condenser Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP5654484A priority Critical patent/JPS60198895A/en
Publication of JPS60198895A publication Critical patent/JPS60198895A/en
Pending legal-status Critical Current

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  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】[Detailed description of the invention]

(産業上の利用分野) 不発明は多層印刷配線板の製造法に関する。 (従来技術) 多層印刷配線板に1例えば待公昭38−14977号に
示さrtゐよりに1両面VC配線パターンを重子基板と
プリプレグを父互に東ね甘ぜ積層プレスし、槓虐俊孔を
囲けて、全面に化学銅めっきと電層銅めっ@r厖し、そ
の飲エッテンクレジス)k塗布し不安の銅層てエツチン
グして層迄している◇この7j1f:でに、両面に配線
パターンを1丁基板を用いるため、内層回路パターンの
凹凸によりプリプレグで多層化接層する除パターン間の
気帛が外に抜けきらず、接層ボイドが発生する欠点があ
る。 この問題を解決丁/8ものとして、特開昭52−111
66C1r公報に提案さn/b刀法がある〇こnに第1
図に示すように絶縁基材1を活性化処理
(Field of Industrial Application) The invention relates to a method for manufacturing multilayer printed wiring boards. (Prior art) One double-sided VC wiring pattern is applied to a multilayer printed wiring board by laminating and pressing a double-sided board and a prepreg with each other in the same manner as shown in, for example, 14977. Enclose, chemical copper plating and electric layer copper plating are applied to the entire surface, and the uneasy copper layer is etched to the layer ◇This 7J1F: Now, wiring on both sides Since a single pattern board is used, the unevenness of the inner layer circuit pattern prevents the air between the removed patterns connected to the multi-layered prepreg from being removed, resulting in contact layer voids. As a solution to this problem, JP-A-52-111
There is a n/b sword method proposed in the 66C1r publication.
Activation treatment of insulating base material 1 as shown in the figure

【行い(a)、
基材1あるいはプリプレグと同種の感光性樹脂2を形成
しくb)露光現像し内ノー回路の逆パターンに照光性樹
脂5を残しくC)、無電廣めっき4電行い(d)%プリ
グレグ忙用いて槙鳩接j;ij?1−行い多層印刷配腺
板r製造す6 (eJものである。 しかしこの方法では、活性化処理tした俊に。 内層回路の逆パターンに感光性@I)h 2形成してい
るため、基材と逆パターンの感光性情脂との曲に活性剤
(M媒)が残v1尚密度配憩パターンになjLば、杷峠
抵抗が問題となゐ0又、プリプレグτ用いて、槓)@接
涜【行つものでめゐため大型の製造袈1ぼが心安となり
コスト低減にも限界がある。 (発明の目的) 本発明にこのような点に鑑みてなさnたもので%市宣度
パターンに通す多ノー印刷配緋板の製ilX法f提供丁
心ものである。 (発明の構成) A発明は次の工程を含む多層印刷配線機の製造法である
◎すなわち。 A、触媒人V杷は基板に眉媒入9懐漸刑増を形b5cす
ゐ。 B、無11L841めっきレジストを形成丁ゐOC0接
涜剤J−τ粗化すゐ。 D、無電解めっ@柩に浸漬し、レジストが形成さfして
い、iLn−Mに黒゛亀所めつ@を竹うOE、全表面に
無゛亀屏のつきレジストと回置の永久レジスト13表曲
ゐ。 F、全衣囲に触媒入V候眉沖」を塗布すゐOG、接漕剤
盾を粗化するO H8無14t714=めっきレジストを形瓜丁ゐ。 1、スルーホールで明けOo J、無電解めり@敵に浸漬し、レジストが形成さrして
いない画用に無電解めつさτ行うO以下第2図に基いて
本発明を説明する0パラジウム、白笛%銅等無−解銅の
つきに対す/)触媒が混入さn罠績盾伍11Vこ度媒人
り接虐斉IJ + 2 >、(塗布し7こ基板τ準備す
ゐ(aJ、このものに、水入めっきマスク+3に印刷′
j−心。こfLけ無電解鋼めりきにヌ1するレジストて
あゐ(b)。 化学粗化畝にL9接接層τ祖化丁心(cJ O無電解鋼
めっ@欣に反演し、レジスト16が形成さnていない山
内に無電解鋼めっき14を行う。このめっき表面は粗面
であるので多層化の脣膚力に優n、均−厚さで内層回路
厚さが壮意に設定出来、又、レジスト表面と回路表面の
簡さがはソ間一平面であり、上達D’v、容易にしてお
91更に、スルーホールのz L/′1簡/iへのめり
@なので、銅ふり、めっきボイドか少なく、めりきが各
局でるる◎ 次に全表面に無電解鋼めっきレジストと問責の永久レジ
ス)15r!布する。レジスト16とIc’J賀のもの
τ塗布子ゐので、V層不艮の問題はなくなる。レジスト
13表曲と回路表面の尚さがはソ同一平面であるため、
この永久レジス)1bH,プレスなしの塗布筐たrJホ
ットロール等でル成し侍る〇 次に触媒入り依屓剤16i塗布丁ゐ0この接虐削も、産
イ1】筐たa、ホットロール等の大型プレスr必安とし
ない方法で形成し得る。 化字租化lKで粗化τ行い(f几しジλト17τ形成し
くg)、スルーホール18に開ける(旬。この揚会、ス
ルーホール開け→レジスト形成→粗化でも良い。 スルーホール忙開けるのね、パンチで行う。 パンチ穴形状に、複雑であり1電気めっきの場谷にめっ
きボイドが発生しやすいが、無IL解銅めっ@σつ@”
tvり性が良く、低コスト、スミア処理がない利点もあ
る。スルーホールにドリルで開けることも出来る〇 次に、無電解鋼めっ@液に反潰し、レジストが形成さn
ていない、スルーホール、及びその周辺に無′14i、
屏めっ@19τ行う0以上4層の揚会を示したが、6膚
及び5層以上も製造5J舵である。 (発明の幼果) 以上説明した不弁明により次の効果が達成ざf′Lる0 (1)絶縁基板表面に触媒が何涜していないので。 回路パターン間の絶線抵抗に′vn、而密度面が可能と
なる〇 (2)プレス槓/*に行なわないので低コストが町能と
なる。 (6) 杷鍼τがね友接看犀」ノ曽【壮怠の厚さに出来
るりで、インピータンス制御が容易である0
[Act (a),
Form a photosensitive resin 2 of the same type as the base material 1 or prepreg.b) Expose and develop to leave a luminous resin 5 in the reverse pattern of the inner no circuit.C) Perform 4-electrode electroless plating.(d) Use % pregreg. Te Makihato contact j;ij? 1 - Manufacture multilayer printed wiring board R6 (eJ) However, in this method, the activation process is performed immediately.Since the photosensitive @I) h2 is formed in the reverse pattern of the inner layer circuit, If the activator (M medium) remains in the pattern between the base material and the photosensitive resin in the opposite pattern, the loquat resistance becomes a problem. @Sacrilege [Since it is a lot of things to do, one large manufactured robe is safe and there is a limit to cost reduction. (Object of the Invention) The present invention has been devised in view of the above points, and provides a method for manufacturing a multi-no printed scarlet board that passes through a commercial pattern. (Structure of the Invention) Invention A is a method for manufacturing a multilayer printed wiring machine including the following steps. A, Catalyst V loquat is shaped b5c with 9 eyebrows added to the board. B. Forming 11L841 plating resist without using OC0 disinfectant J-τ roughening. D. Immerse in electroless plating, resist is formed, iLn-M is coated with black kame place OE, the whole surface is covered with non-glare resist and the resist is formed. Permanent resist 13 songs. F.Apply catalyst-containing V-coat to the entire coating area.OG, Roughen the coating agent shield. 1. Through-hole opening Oo J, Electroless drilling @ Immersion into the target, electroless drilling τ for images where no resist is formed O Below, the present invention will be explained based on Fig. 2. 0 palladium, white whistle% copper, etc. No - against copper decomposition /) Catalyst is mixed n trap result shield 5 11V this time mediator attack IJ + 2 >, (coated 7 boards τ preparation (aJ, printed on this thing, water-filled plating mask + 3'
j-heart. This resist is applied to the electroless steel plate (b). Electroless steel plating 14 is applied to the ridges where resist 16 is not formed. Since the surface is rough, it has excellent flexibility in multi-layering, and the uniform thickness allows the inner layer circuit thickness to be set boldly.Also, the resist surface and circuit surface are simple, and the thickness is one plane between the resist surface and the circuit surface. , Improve D'v, make it easy 91 Furthermore, since it is addictive to z L/'1 simple/i of the through hole, there are few copper filling, plating voids, and plating appears at each station ◎ Next, there is nothing on the entire surface. Electrolytic steel plating resist and permanent resist) 15r! to clothe Since the resist 16 and the Ic'J layer are coated with τ, the problem of the V layer not being printed is eliminated. Since the resist 13 surface curve and the roughness of the circuit surface are on the same plane,
This permanent resist) 1bH, coating case without press rJ, hot roll, etc. 〇 Next, apply the catalyst-containing dependent agent 16i, etc. It can be formed by a method that does not require a large press such as. Perform roughening τ using the cursive process lK (f ㇠ji λ t 17τ formation g), and open through hole 18. It is opened with a punch.The shape of the punch hole is complicated and plating voids are likely to occur in the holes of electroplating, but IL-free copper plating @σtsu@”
It has the advantages of good TV resistance, low cost, and no smear treatment. You can also drill through holes.Next, crush it in electroless steel plating solution to form a resist.
There is no through-hole, and there is no hole around it.
Although we have shown the lifting of 4 layers of 0 or more to be carried out at 19τ, 6 layers and 5 or more layers are also manufactured 5J rudders. (Effects of the Invention) The following effects cannot be achieved due to the above-mentioned lack of explanation. (1) Since the catalyst is not contaminated on the surface of the insulating substrate. 〇(2) Pressing is not required, so the cost can be reduced. (6) Loquat acupuncture τgane friendly care ``noso'' [It is possible to achieve the thickness of laxity, so impedance control is easy0

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は促米法でボ丁U「面図、第2図は本発明の方法
’vy]<す−「面図であゐ◎符号の説明 11、触媒入り槓ノ曽板 12、触媒入り埃盾剤 16、レジスト 14、無′亀ys銅めっき 15、永久レジスト 16、触4南り人!フ接之瀾−′メ賞り17、レジスト 1aスルーホール 19、無電解銅めっき 代理へ升埋士 看 林 邦 彦 第1図 ] 第1頁の続き ■発明者魚津 信夫 栃木県芳賀郡二宮町久下田41旙地 日立コンデンサ株
式会社%
Figure 1 is a top view of the rice promotion method, and Figure 2 is a top view of the method of the present invention. Containing dust shielding agent 16, resist 14, non-copper plating 15, permanent resist 16, contact 4 south person!Fuction connection-'me award 17, resist 1a through hole 19, electroless copper plating agent Figure 1] Continuing from page 1 ■ Inventor Nobuo Uozu 41 Kugeta, Ninomiya-cho, Haga-gun, Tochigi Hitachi Capacitor Co., Ltd.

Claims (1)

【特許請求の範囲】 1、 次の151a−営む多層印刷配線板の製造法。 A、P!Ji妹人V杷鰍基絶縁肛婉入り艦盾ハリ虐を形
成する。 B、無電解めっきレジストを形成するOC−伎盾創虐τ
祖化する。 D−勲′鴫mめつさ醋に6を碩し、レジストが形成ざ2
’していないl1Il内に無電解のっきτ行う。 E21次面Vこ無′也屏めっさレジストと回負の永久レ
ジストを堡布丁ゐ〇 ド、竺衣囲に触媒人り扱腐Aすを堕イliすゐ・G、憬
ま駐ノーi11リノ曽?=イ↓l化すべ一〇ロー 無電
解めっさレジスIr形凧すゐ。 ■、スルーホールkklJける。 J、無電解めりき歇には偵し、レジストか形成さrして
いない薗B+Vこ無1解めっきτ行う。 ム4#トレ4(/JII−1;1111+i3=w、k
s4
[Claims] 1. A method for manufacturing a multilayer printed wiring board comprising the following 151a. A, P! Ji sister person V loquat base insulation anal enters the ship shield Hari brutality is formed. B. OC-Kidun Sosaku τ forming electroless plating resist
Become an ancestor. Add 6 to D-Kun'Metsuna and the resist is formed 2
' Perform electroless plating τ in l1Il. E21st side V Kon'ya, the permanent resist of the negative and the negative permanent resist, and the catalytic person in the coat, the rotten A is fallen. i11 Reno So? =I↓L should be changed to 10L Electroless Messa Regis Ir type kite Sui. ■Through-hole kklJ. J. During electroless plating, perform plating on B+V without resist formation. M4#Tre4(/JII-1;1111+i3=w,k
s4
JP5654484A 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board Pending JPS60198895A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5654484A JPS60198895A (en) 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5654484A JPS60198895A (en) 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS60198895A true JPS60198895A (en) 1985-10-08

Family

ID=13030029

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5654484A Pending JPS60198895A (en) 1984-03-23 1984-03-23 Method of producing multilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS60198895A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856386A (en) * 1981-09-29 1983-04-04 日立化成工業株式会社 Method of producing printed circuit board
JPS58161760A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum substrate
JPS58161759A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum base plate

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5856386A (en) * 1981-09-29 1983-04-04 日立化成工業株式会社 Method of producing printed circuit board
JPS58161760A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum substrate
JPS58161759A (en) * 1982-03-18 1983-09-26 Matsushita Electric Ind Co Ltd Method for plating on aluminum base plate

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