JPH10163629A - Manufacture of multi-layer printed wiring board - Google Patents

Abstract

PROBLEM TO BE SOLVED: To omit a plating pretreatment, by forming a multi-layer by repeating such process as a via hole is formed on an insulation layer comprising a plating catalyser on an insulation substrate where the first circuit layer is already formed and then copper is plated on the surface of insulation layer and on the inside wall of via hole, in this order. SOLUTION: An insulation layer 3 comprising a plating catalyst is formed (b) on an insulation substrate 2 where the first circuit layer 1 is already formed (a), and a via hole 4 for connecting the first circuit layer 1 and the second circuit layer 5 together is formed on an insulation layer 3 (c). The second circuit layer 5 is formed in the same manner as the first circuit layer 1 (e), to provide a 3-layer printed wiring board comprising a power source layer and/or a ground layer G, the first circuit layer 1, and the second circuit layer 5. For further multiplication in layers, processes starting with formation of insulation layer, (b)-(e), are repeated. As a result, a plating pretreatment can be omitted, thus the cost for multi-layer printed wiring boards by build-up method is significantly reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a method for manufacturing a multilayer printed wiring board.

[0002]

2. Description of the Related Art Recently, as a method of manufacturing a multilayer printed wiring board, a method of manufacturing a multilayer printed wiring board by a build-up method has attracted attention because the wiring density can be increased.
This method of manufacturing a multilayer printed wiring board by the build-up method is a method of alternately stacking circuit layers and insulating layers on an insulating substrate. The method of manufacturing a multilayer printed wiring board by the build-up method includes the following steps. An insulating layer is formed on the insulating substrate on which the al circuit layer is formed. b. Via holes are formed in the insulating layer. c. Copper plating is applied to the surface of the insulating layer and the inner wall of the via hole to form an interlayer connection by the second circuit layer and the via hole. To further form a multilayer, the above steps a to c are repeated after forming an insulating layer on the second circuit layer.

The step c is subdivided into a roughening step for the surface of the insulating layer, a pre-plating step and a plating step. The pre-plating step further includes a conditioner step for facilitating adsorption of the plating catalyst, The plating step is subdivided into a seeding step of adsorbing the plating catalyst and an activation step of the plating catalyst adsorbed on the insulating layer surface in the seeding step, and the plating step is subdivided into an electroless plating step and an electrolytic plating step.

[0004]

Heretofore, in a method of manufacturing a multilayer printed wiring board by a build-up method, the pre-plating treatment step of the c step has been the most bottleneck. In this pre-plating process, it is necessary to perform a water washing process between each process process in addition to the three process processes of a conditioner process process, a seeding process process, and a plating catalyst activation process process. This is because it is necessary to immerse and process. SUMMARY OF THE INVENTION It is an object of the present invention to eliminate a plating pretreatment step and shorten the steps in a method for manufacturing a multilayer printed wiring board by a build-up method.

[0005]

According to the present invention, there are provided (a) a step of forming an insulating layer 3 containing a plating catalyst on an insulating substrate 2 on which a first circuit layer 1 is formed, and (b) a step of forming a via in the insulating layer 3. Forming a hole 4 and (c) applying a copper plating 6 to the surface of the insulating layer 3 and the inner wall of the via hole 4 to form a second circuit layer 5.
And a step of forming an interlayer connection by the via hole 4 in this order is repeated once or twice or more to form a multilayer structure.

[0006]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A description will be given below with reference to FIG. First, the insulating substrate 2 on which the first circuit layer 1 is formed (FIG. 1A)
An insulating layer 3 containing a plating catalyst is formed thereon.
b).

As the insulating substrate 2 used in the present invention,
There is no particular limitation as long as it can be used as a substrate for a printed wiring board. For example, a glass cloth substrate epoxy resin laminate, a phenol resin laminate, and the like can be given. Usually, a first circuit layer 1 is formed on one side of a double-sided copper-clad laminate by a known subtractive method, and the other side is formed with a power supply layer and / or
Alternatively, a ground layer G is used.

The insulating layer 3 is made of a thermosetting resin, a photosensitive resin,
Alternatively, it is formed using both a photosensitive resin and a thermosetting resin. The insulating layer 3 needs to have plating solution resistance, heat resistance and insulation properties. Specific examples of a material that can form such an insulating layer 3 include a composition in which a thermal initiator and / or a photoinitiator is mixed with an epoxy resin, an epoxy acrylate, an acid-modified epoxy resin, a phenol resin, and the like. However, the present invention is not limited to this.

As a plating catalyst, Group 8 of the Periodic Table of the Elements
A metal belonging to Group 1B or 2B, for example, palladium;
Adsorbed salts or oxides of rhodium, platinum, copper, silver, gold, zinc, cadmium, etc. on inorganic fillers such as silica, alumina, aluminum hydroxide, aluminosilicate, hika, mica and talc Is used. The plating catalyst serves as a deposition nucleus for electroless plating. If the amount of the plating catalyst is too small, the required plating deposition property cannot be obtained, and if the amount is too large, the insulating property of the insulating layer decreases. From such a viewpoint, the content is preferably 2 to 25% by weight, more preferably 5 to 10% by weight in the insulating layer. If the particle size of the inorganic filler for adsorbing the plating catalyst is too large, heat resistance and insulation properties are reduced. Therefore, it is preferable to use one having an average particle size of 5 μm or less. Further, it is preferable to roughen the surface of the insulating layer 3 prior to the subsequent plating. In order to improve the roughening property of the surface of the insulating layer 3, the surface of the insulating layer 3 is more roughened than the organic component in the insulating layer 3. An inorganic filler such as hardly soluble alumina, silica, aluminosilicate or the like, or calcium carbonate which is more soluble in the roughening liquid than the organic component in the insulating layer 3 may be added. These inorganic fillers for improving the roughening property have a particle size of 0.1 to obtain a dense roughened shape.
It is preferably from 5 to 10 μm. Further, it is preferable that the inorganic filler is blended so as to be 10 to 50% by weight in the insulating layer.

As a method for forming the insulating layer 3, any method of applying a liquid material by a method such as roll coating or curtain coating, or a method of laminating using a filmed material can be adopted. Before forming the insulating layer 3, in order to enhance the adhesiveness of the insulating layer 3, the conductor surface of the first circuit layer 1 is oxidized to form irregularities. The reduction is preferably performed using an alkaline reducing agent such as sodium or dimethylamine borane.

Next, via holes 4 for connecting the first circuit layer 1 and the second circuit layer 5 are formed in the insulating layer 3 (FIG. 1C). As a method of forming the via hole 4, a photo method is used when a photosensitive resin is used as a material of the insulating layer 3, and a laser is used when a thermosetting resin is used.

After the surface of the insulating layer 3 is treated with a known oxidizing roughening solution, a copper plating layer 6 is formed (FIG. 1-d). The copper plating layer 6 is formed by depositing copper to a thickness of about 0.5 to 1 μm on the surface of the insulating layer 3 and the inner wall of the via hole 4 by electroless plating, and then by electrolytic plating until the desired thickness is obtained. Is formed by precipitation.

Finally, the second circuit layer is formed in the same manner as the first circuit layer 1.
Is formed (FIG. 1-e). Thereby, a three-layer printed wiring board including the power supply layer and / or the ground layer G, the first circuit layer 1 and the second circuit layer 5 is obtained. When this is further multilayered, formation of an insulating layer and subsequent steps b to b in FIG.
The step e may be repeated.

[0014]

【Example】

Example 1 A double-sided copper-clad laminate of glass cloth base epoxy resin having a 35 μm-thick double-sided roughened copper foil on both sides (using MCL-E-67 (trade name) manufactured by Hitachi Chemical Co., Ltd.) A first circuit layer was formed on one side by a subtractive method. A liquid insulating layer forming material was applied by roll coating on the first circuit layer, and dried at 80 ° C. for 10 minutes to form an insulating layer having a thickness of 50 μm. The composition of the insulating layer forming material was the same as the composition 1 of the insulating layer forming material. Composition 1 of Insulating Layer Forming Material Phthalic Acid-Modified Novolak-Type Epoxy Acrylate (R-5259 (trade name), manufactured by Nippon Kayaku Co., Ltd.) 70
Parts (parts by weight, hereinafter the same), 20 parts of acrylonitrile butadiene rubber (PNR-1H (trade name) manufactured by Nippon Synthetic Rubber Co., Ltd.), alkylphenol resin, (Hitanol 2400 (trade name) manufactured by Hitachi Chemical Co., Ltd.) 3 parts; photoinitiator (Circa Geigy, Irgacure 651 (trade name) used) 7 parts; plating catalyst (Hitachi Chemical Co., Ltd., Cat # 14 (trade name) used) 5
10 parts of aluminum hydroxide (using HYGILIGHT H-42M (trade name) manufactured by Showa Denko KK).

Next, an exposure amount of 400 mJ / cm ² is applied through a photomask in which a shielding portion is provided at a portion to be a via hole.
The insulating layer was irradiated with the ultraviolet ray, and immersed in a developing solution (1% by weight aqueous solution of sodium carbonate) kept at 30 ° C. for 2 minutes to dissolve and remove unexposed portions to form via holes. Thereafter, the entire insulating layer was irradiated with ultraviolet rays having an exposure amount of ² J / cm ² .

Next, at 50 ° C. to roughen the surface of the insulating layer.
For 3 minutes. As a roughening liquid,
Using an aqueous solution of KMnO ₄ : 60 g / l and NaOH: 40 g / l, after immersion of the roughening solution, SnCl ₂ : 30 g / l, H
Cl: neutralized by immersion treatment in 300 ml / l aqueous solution for 3 minutes.

Next, it is immersed in an electroless copper plating solution (CUST201 (trade name), manufactured by Hitachi Chemical Co., Ltd.) at room temperature for 25 minutes, washed with water, and further subjected to electrolytic plating using a copper sulfate solution. Forming a copper plating layer having a thickness of 20 μm,
Annealed at 150 ° C. for 30 minutes.

Next, an etching resist is formed on the entire surface on the side opposite to the first circuit layer and on the copper plating layer so that a predetermined circuit can be formed. In this order, the second circuit layer and the interlayer connection by the via hole were formed to obtain a three-layer printed wiring board.

Example 2 An insulating layer was formed in the same manner as in Example 1 except that the composition of the material for forming an insulating layer was the same as the composition 2 of the material for forming an insulating layer.
Annealed at 160 ° C. for 60 minutes. Composition of insulating layer forming material 2 Bisphenol A type epoxy resin (Epicoat 1001 (trade name) manufactured by Yuka Shell Epoxy Co., Ltd.) 3
0 parts, cresol novolak type epoxy resin (YDCN-701P (trade name) manufactured by Toto Kasei Co., Ltd.) 3
0 parts, resole resin (HP1 manufactured by Hitachi Chemical Co., Ltd.)
80R (trade name) 15 parts, acrylonitrile butadiene rubber (use the same as in Example 1) 17 parts, alkylphenol resin (use the same as in Example 1) 3
Parts, 2-methylimidazole (2MZ (trade name) manufactured by Shikoku Chemicals Co., Ltd.), 5 parts, aluminum hydroxide (same as in Example 1) 10 parts, plating catalyst (same as in Example 1) 5 parts.

Next, via holes are formed by a carbon dioxide laser, and roughening of the insulating layer surface, formation of a copper plating layer, formation of a second circuit layer, and interlayer connection by the via holes are performed in the same manner as in Example 1. It was formed to obtain a three-layer printed wiring board.

Comparative Example 1 An insulating layer was formed in the same manner as in Example 1 except that the plating catalyst was removed from composition 1 of the insulating layer forming material, via holes were provided, and the surface of the insulating layer was roughened. Next, plating pretreatment was performed. The plating pretreatment is performed by dipping in a conditioner (using Hitachi Chemical Co., Ltd., CLC-501 (trade name)) at 60 ° C. for 5 minutes, washing with hot water at 60 ° C. for 1 minute, further washing with water, and electroless containing PdCl _2. Immersion in a catalyst solution for plating (using HS-202B (trade name, manufactured by Hitachi Chemical Co., Ltd.)) at room temperature for 10 minutes, washing with water, activation treatment solution of palladium (ADP-401 (trade name, manufactured by Hitachi Chemical Co., Ltd.) Name)
Immersion at normal temperature for 5 minutes and washing with water in this order.

Thereafter, in the same manner as in Example 1, a copper plating layer was formed, a second circuit layer was formed, and interlayer connections were formed by via holes to obtain a three-layer printed wiring board.

Comparative Example 2 An insulating layer was formed in the same manner as in Example 2 except that the plating catalyst was removed from composition 2 of the material for forming the insulating layer, a via hole was provided, and the surface of the insulating layer was roughened. Thereafter, in the same manner as in Comparative Example 1, a three-layer printed wiring board was obtained by performing plating pretreatment, forming a copper plating layer, forming a second circuit layer, and forming interlayer connections using via holes.

With respect to the three-layer printed wiring board obtained as described above, the adhesive strength (the adhesive strength between the second circuit layer and the insulating layer), electric corrosion resistance and solder heat resistance were examined. Table 1 shows the results.

The test method was as follows. Adhesive strength: Inspection was carried out in accordance with JIS C 6481 "Test method for copper-clad laminates for printed wiring boards". Electrolytic corrosion resistance: Comb patterns of L / S = 100 μm / 100 μm are formed on the inner layer and the outer layer, and in an atmosphere of 85 ° C.-85% RH, a DC of 100 V with the inner layer being minus and the outer layer being plus is applied. Was measured until the resistance value of the sample became 10 ⁸ Ω or less. Solder heat resistance: The time required to cause blistering after floating in a solder bath at 288 ° C. was measured.

[0026]

[Table 1]

[0027]

According to the present invention, the pretreatment step for plating can be omitted, and the cost of the multilayer printed wiring board by the build-up method can be greatly reduced.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view showing a change in a process in the order of (a), (b), (c), (d), and (e).

[Description of Signs] 1 First circuit layer 2 Insulating substrate 3 Insulating layer 4 Via hole 5 Second circuit layer 6 Copper plating layer G Power supply layer and / or ground layer

Claims (1)

[Claims] 1. A step of forming an insulating layer containing a plating catalyst on an insulating substrate having a first circuit layer formed thereon, a step of forming a via hole in the insulating layer, and a step of forming a via hole in the insulating layer. And a step of forming the interlayer connection by the second circuit layer and the via hole by plating the inner wall of the via hole with copper, once or twice or more in this order to form a multilayer printed wiring. Plate manufacturing method.