JP3697726B2 - Manufacturing method of multilayer wiring board - Google Patents
Manufacturing method of multilayer wiring board Download PDFInfo
- Publication number
- JP3697726B2 JP3697726B2 JP27651194A JP27651194A JP3697726B2 JP 3697726 B2 JP3697726 B2 JP 3697726B2 JP 27651194 A JP27651194 A JP 27651194A JP 27651194 A JP27651194 A JP 27651194A JP 3697726 B2 JP3697726 B2 JP 3697726B2
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- wiring board
- insulating layer
- resin
- multilayer wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Images
Landscapes
- Compositions Of Macromolecular Compounds (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【０００１】
【産業上の利用分野】
本発明は、多層配線板の製造方法に関するものである。
【０００２】
【従来の技術】
通常の多層配線板は、内層回路を形成した絶縁基板上に、プリプレグと呼ばれるガラス布にエポキシ樹脂を含浸し、半硬化状態にした材料を銅箔と重ねて熱プレスにより積層一体化した後、ドリルで層間接続用のスルーホールと呼ばれる穴をあけ、スルーホール内壁と銅箔表面上に無電解めっきを行って、必要ならば更に電解めっきを行って回路導体として必要な厚さとした後、不要な銅を除去して多層配線板を製造する。
【０００３】
ところで、近年、電子機器の小型化、軽量化、多機能化が一段と進み、これに伴い、ＬＳＩやチップ部品等の高集積化が進みその形態も多ピン化、小型化へと急速に変化している。この為、多層配線板は、電子部品の実装密度を向上するために、微細配線化の開発が進められている。
しかしながら、配線幅の縮小には技術的に限界があり、現在量産可能な配線幅は７５〜１００μｍである。この為、単に配線幅を縮小するだけでは大幅な配線密度の向上が達成しにくい。
また、配線密度向上の隘路となっているのが、直径３００μｍ前後の面積を占めるスルーホールである。このスルーホールは、一般的にメカニカルドリルで形成されるために比較的に寸法が大きく、この為、配線設計の自由度が乏しくなる。
【０００４】
これらの問題を解決するものとして、感光性を付与した絶縁樹脂を回路形成した絶縁基板上に形成し、フォトプロセスにより絶縁樹脂に微小なバイアホールを形成して層間接続する方法が、特公平４−５５５５５号公報や特開昭６３−１２６２９６号公報に開示されている。
【０００５】
【発明が解決しようとする課題】
前記した従来の方法は、フォトプロセスによって形成した微小なバイアホールで層間接続する多層配線板であり、従来抱えていた多層配線板の配線密度向上の問題に関して大きく寄与するものである。
しかし、前記先行技術は、めっき銅と絶縁樹脂との接着力を高めるために、平均粒径が大きい（１０μｍ以下）耐熱性の樹脂フィラーやゴム成分を感光性樹脂に含有する方法がとられている為、平均粒径が大きい（１０μｍ以下）耐熱性の樹脂フィラーを絶縁層に含有した場合、表面凹凸が大きくなるためライン精度に支障が出ると同時に、エポキシ等の耐熱性フィラーは、通常二重結合を有するブタジエン成分に比べて酸化性粗化液への溶解度が小さく、安定しためっき接着力が得られにくい。
また、ゴム成分は、粗化液溶解性という点で優れているが、線状高分子量状態であるため他材料との相溶性に問題が出やすく、耐熱性の点でも不利になりやすい。
【０００６】
本発明の目的は、めっき導体との接着力、表面平滑性、及び耐熱性に優れた感光性絶縁樹脂を用いた多層配線板を提供するものである。
【０００７】
【課題を解決するための手段】
本発明の多層配線板の製造方法は、第１の回路を形成した絶縁基板の回路表面上に、絶縁層に第１の回路と接続するためのバイアホールを形成し、銅めっきによって絶縁層表面に第２の回路形成及びバイアホールの層間接続を行って多層化する配線板の製造方法において、絶縁層が、架橋したアクリロニトリルブタジエンゴム粒子を含む感光性樹脂及び／または感光性と熱硬化性を併用した樹脂を用いることを特徴とする。
【０００８】
本発明に用いる、架橋したアクリロニトリルブタジエンゴム粒子は、乳化重合後のエマルジョン状態でアクリロニトリルブタジエンゴムを架橋した１次平均粒子径が５０〜１００ nm ｛５００〜１０００オングストローム｝の微小高分子量架橋ゴム粒子であり、カルポキシル基変成または未変成のアクリロニトリルブタジエンゴムは何れも使用できる。
その配合量は、感光性樹脂及び／または感光性と熱硬化性を併用した樹脂の全固形分中に２〜４０重量％となるようにする。好ましくは、５〜２５重量％の範囲である。
架橋したアクリロニトリルブタジエンゴム粒子が２重量％以下では、めっき銅との接着力向上が十分でなく、また、４０重量％以上になると絶縁層の粘着性が増し、フォトマスクやごみが粘着しやすくなるために好ましくない。
【０００９】
アクリロニトリルブタジエンゴム粒子を含有するベースとなる感光性樹脂及び／または感光性と熱硬化性を併用した樹脂としては、特に限定するものではなく、光によって架橋可能な官能基を有した共重合体あるいは単量体を含んだ組成物及び／または光の他に熱で架橋可能な官能基と熱開始剤を混合した組成物であれば何れも可能である。
【００１０】
また、本発明の絶縁層組成物には、微粉末シリカ、水酸化アルミニウム、シリカ、ケイ酸ジルコニウム、炭酸カルシウム、タルク、硫酸バリウム等の無機充填剤を混入すれば化学粗化した際の粗化凹凸を形成しやすいため、めっき銅との接着力向上の点から好ましく、塗膜補強の点でも良い結果が得られる。
【００１１】
以上に説明した絶縁層組成物を用いて、図１によって、本発明の多層配線板を製造する工程を、詳しく説明する。
先ず、第１の回路を形成した絶縁基板を用意する（図１−ａ）。
この絶縁基板は特に限定するものではなく、ガラス布−エポキシ樹脂、紙−フェノール樹脂、紙−エポキシ樹脂、ガラス布・ガラス紙−エポキシ樹脂等通常の配線板に用いる絶縁基板が使用できる。本発明の第１の回路を形成する方法としては、銅箔と前記絶縁基板を張り合わせた銅張り積層板を用い、銅箔の不要な部分をエッチング除去するサブトラクティブ法や、前記絶縁基板の必要な箇所に無電解めっきによって回路を形成するアディティブ法等、通常の配線板の製造法を用いることができる。
【００１２】
次に、第１の回路を形成した回路表面上に前記絶縁層を形成する（図１−ｂ）。この形成方法は、液状の樹脂をロールコート、カーテンコート、ディプコート等の方法で塗布する方式や、前記絶縁樹脂をフィルム化してラミネートで張り合わせる方式を用いることができる。
【００１３】
次に、絶縁層に、第１の回路と接続するバイアホールを形成するために、フォトマスクを介して露光し（図１−ｃ）、未露光部分を現像液により食刻する方法によって絶縁層に第１の回路と接続するバイアホールを形成する（図１−ｄ）。露光は、通常の配線板のレジスト形成方法と同じ手法が用いられる。
また、未露光部分を現像液により食刻する現像液としては、絶縁樹脂組成物をどのような現像タイプにすることで決定されるが、アルカリ現像液、準水系現像液、溶剤現像液など一般的なものを用いることができる。
【００１４】
次に、絶縁層を酸化性粗化液で処理した後、絶縁層上に銅めっきを析出させて第２の回路形成及びバイアホールの層間接続を行う（図１−ｅ）。
この場合、絶縁層を紫外線及び紫外線と熱で硬化させてから酸化性の粗化液に浸漬する手法を用いることもできる。
酸化性粗化液としては、クロム／硫酸粗化液、アルカリ過マンガン酸粗化液、フッ化ナトリウム／クロム／硫酸粗化液、ホウフッ酸粗化液等を用いることができる。
更に第２の回路を形成する方法としては、粗化した絶縁層表面に無電解めっき用の触媒を付与して全面に無電解めっき銅を析出させ、必要な場合には電解めっきによって回路導体を必要な厚さにして、不要な箇所をエッチング除去して形成する方法や、めっき触媒を含有した絶縁層を用いて、めっきレジストを形成して必要な箇所のみ無電解めっきにより回路形成する方法、及びめっき触媒を含有しない絶縁層を粗化し、めっき触媒を付与した後、めっきレジストを形成して必要な箇所のみ無電解めっきにより回路形成する方法等を用いることができる。
【００１５】
本発明を多層化する場合には、以上の方法（図１−ｂ〜図１−ｅ）を繰り返し行い多層化する（工程：図１−ｆ〜図１−ｈ）。この際、好ましくは、次の回路層を形成する前に、その下になる回路層導体表面を粗化して凹凸を形成したり、従来の多層配線板に用いられるように回路層導体表面を酸化して凹凸を形成したり、酸化して形成した凹凸を水素化ホウ素ナトリウムやジメチルアミンボラン等のアルカリ性還元剤を用いて還元して層間の接着力を高めることができる。
【００１６】
【作用】
本発明は、特定の絶縁層を層間絶縁層に用いてビルドアップ方式で多層化する配線板の製造方法であり、めっき銅との接着力が高く、しかも表面平滑性、耐熱性に優れた多層配線板を提供することができる。
【００１７】
【実施例】
実施例１
（１）１８μｍの両面粗化箔を両面に張り付けた銅張りガラス布エポキシ樹脂積層板であるＭＣＬ−Ｅ−６７（日立化成工業株式会社製、商品名）を用い、不要な箇所の銅箔をエッチング除去して、第１の回路を形成する（図１−ａに示す）。
（２）この表面の片面に、下記組成の絶縁樹脂をロールコートにより塗布し、８０℃−１０分間乾燥して膜厚６０μｍの絶縁層を形成した（図１−ｂに示す）。
（組成）
・フタル酸変性ノボラック型エポキシアクリレート、
Ｒ−５２５９（日本化薬株式会社製、商品名）・・・・・・・７０重量部
・架橋カルボン酸変性アクリロニトリルブタジエンゴム粒子、
ＸＥＲ−９１（日本合成ゴム株式会社製、商品名）・・・・・２５重量部
・光開始剤、
イルガキュア６５１（チバガイギー社製、商品名）・・・・・・５重量部
・充填剤、水酸化アルミニウム
ハイジライトＨ−４２Ｍ（昭和電工株式会社製、商品名）・・１０重量部
（３）バイアホールとなる部分に遮蔽部を形成したフォトマスクを介して、露光量３００ｍＪ／ｃｍ2 の紫外線を照射して（図１−ｃに示す）、更に未露光部分を、１．１％炭酸ナトリウム水溶液の現像液で３０℃−２分間選択的に除去してバイアホールを形成した。
（４）紫外線２Ｊ／ｃｍ2を絶縁層に照射して後露光を行う。
（５）絶縁層を化学粗化するために、粗化液として、ＫＭｎＯ4 ：６０ｇ／ｌ、ＮａＯＨ：４０ｇ／ｌの水溶液を作製し、５０℃に加温して５分間浸漬処理する。
ＫＭｎＯ4浸漬処理後は、ＳｎＣｌ2：３０ｇ／ｌ、ＨＣｌ：３００ｍｌ／ｌの水溶液に室温で５分間浸漬処理して中和し、粗化凹凸形状を形成した（図１−ｄに示す）。
（６）第１の絶縁層表面に第２の回路を形成するために、まず、ＰｄＣｌ2を含む無電解めっき用触媒であるＨＳ−２０２Ｂ（日立化成工業株式会社製、商品名）に、室温−１０分間浸漬処理し、水洗し、無電解銅めっきであるＬ−５９めっき液（日立化成工業株式会社製、商品名）に７０℃−３０分間浸漬し、更に硫酸銅電解めっきを行って、絶縁層表面上に厚さ２０μｍの導体層を形成する。
次に、めっき導体の不要な箇所をエッチング除去するためにエッチングレジストを形成し、エッチングし、その後エッチングレジストを除去して、第１の回路と接続したバイアホールを含む第２の回路形成を行う（図１−ｅに示す）。
（７）更に、多層化するために、第２の回路導体表面を、亜塩素酸ナトリウム：５０ｇ／ｌ、ＮａＯＨ：２０ｇ／ｌ、リン酸ナトリウム１０ｇ／ｌの水溶液に８５℃−２０分間浸漬し、水洗して、８０℃−２０分間乾燥して第２の回路導体表面上に酸化銅の凹凸を形成する。
（８）（２）〜（７）の工程を繰り返して多層配線板を作製した（図１−ｆ〜図１−ｈに示した）。
【００１８】
実施例２
実施例１で示した絶縁樹脂組成物を下記組成に変更した。また、現像液は、ジエチレングリコールモノブチルエーテル：２００ｍｌ／ｌ、ホウ砂：１０ｇ／ｌを含む準水系現像液を用いて、４０℃−３０分間現像し、粗化前に、紫外線２Ｊ／ｃｍ2を照射し、１５０℃−３０分間の熱硬化を行った。その他は、実施例１と同様の方法で行った。
（組成）
・ビスフェノールＡ型エポキシ、
エピコート８３４（油化シェル株式会社製、商品名）・・・・１５重量部
・フェノールノボラック型エポキシアクリレート、
ＳＰ−４０１０（昭和高分子株式会社製、商品名）・・・・・５０重量部
・架橋カルボン酸変性アクリロニトリルブタジエンゴム粒子、
ＸＥＲ−９１（日本合成ゴム株式会社製、商品名）・・・・・３０重量部
・光開始剤、
イルガキュア６５１（チバガイギー社製、商品名）・・・・・・５重量部
・熱硬化剤、
ジシアンジアミド・・・・・・・・・・・・・・・・・・・・・２重量部
・充填剤、水酸化アルミニウム
ハイジライトＨ−４２Ｍ（昭和電工株式会社製、商品名）・・１０重量部
【００１９】
実施例３
実施例１で示した絶縁樹脂組成物を下記組成に変更した。また、現像液は、エチルエトキシプロピオネート：１０００ｍｌ／ｌの溶剤系現像液を用いて、３０℃−５分間現像し、粗化前に、紫外線２Ｊ／ｃｍ2を照射し、１５０℃−３０分間の熱硬化を行った。その他は、実施例１と同様の方法で行った。
（組成）
・ビスフェノールＡ型エポキシ、
エピコート８３４（油化シェル株式会社製、商品名）・・・・２０重量部
・ビスフェノールＡ型エポキシアクリレート、
ＶＲ−６０（昭和高分子株式会社製、商品名）・・・・・・・６０重量部
・架橋カルボン酸変性アクリロニトリルブタジエンゴム粒子、
ＸＥＲ−９１（日本合成ゴム株式会社製、商品名）・・・・・１５重量部
・光開始剤、
イルガキュア６５１（チバガイギー社製、商品名）・・・・・・５重量部
・熱硬化剤、
ジシアンジアミド・・・・・・・・・・・・・・・・・・・・・２重量部
・充填剤、水酸化アルミニウム
ハイジライトＨ−４２Ｍ（昭和電工株式会社製、商品名）・・１０重量部
【００２０】
比較例１〜３
実施例１〜３において、架橋ＮＢＲを用いない組成系とした。その他は、実施例１〜３と同様の方法で行った。
以上の様にして作製した多層配線板の特性を、表１に示す。
【００２１】
【表１】
【発明の効果】
以上に説明したように、本発明によって、めっき銅との接着力が高く、耐熱性に優れたビルドアップ方式の多層配線板の製造法を提供することができた。
【図面の簡単な説明】
【図１】（ａ）〜（ｈ）は、本発明の一実施例を説明するための各工程における断面図である。
【符号の説明】
１．絶縁基板
２．第１の回路
３．第１の絶縁層
４．フォトマスク
５．紫外線
６．バイアホール ６１．バイアホール
７．粗化面 ７１．粗化面
８．第２の回路
９．第２の絶縁層
１０．第３の回路[0001]
[Industrial application fields]
The present invention relates to a method for manufacturing a multilayer wiring board.
[0002]
[Prior art]
A normal multilayer wiring board is obtained by impregnating a glass cloth called a prepreg with an epoxy resin on an insulating substrate on which an inner layer circuit is formed, and stacking and integrating a semi-cured material with a copper foil by heat pressing, After drilling holes called through holes for interlayer connection with a drill, electroless plating is performed on the inner walls of the through holes and the copper foil surface, and if necessary, further electrolytic plating is performed to obtain the necessary thickness for the circuit conductor, which is unnecessary. Copper is removed to produce a multilayer wiring board.
[0003]
By the way, in recent years, electronic devices have been further reduced in size, weight and functionality, and along with this, LSIs and chip parts have been highly integrated, and their form has rapidly changed to multi-pin and miniaturization. ing. For this reason, in order to improve the mounting density of electronic components, multilayer wiring boards are being developed for fine wiring.
However, the reduction of the wiring width is technically limited, and the wiring width that can be mass-produced at present is 75 to 100 μm. For this reason, it is difficult to achieve a significant increase in wiring density by simply reducing the wiring width.
In addition, a through-hole that occupies an area of about 300 μm in diameter is a bottleneck for improving the wiring density. Since this through hole is generally formed by a mechanical drill, it has a relatively large size, and therefore, the degree of freedom in wiring design becomes poor.
[0004]
In order to solve these problems, a method in which an insulating resin imparted with photosensitivity is formed on an insulating substrate on which a circuit is formed, a minute via hole is formed in the insulating resin by a photo process, and an interlayer connection is made is used. -55555 and JP-A-63-126296.
[0005]
[Problems to be solved by the invention]
The above-described conventional method is a multilayer wiring board in which interlayer connection is made by a minute via hole formed by a photo process, and greatly contributes to the problem of improving the wiring density of the multilayer wiring board which has been conventionally held.
However, the prior art employs a method in which a heat-resistant resin filler or rubber component having a large average particle size (10 μm or less) is contained in the photosensitive resin in order to increase the adhesion between the plated copper and the insulating resin. Therefore, when a heat-resistant resin filler having a large average particle size (10 μm or less) is contained in the insulating layer, the surface unevenness increases, so that the line accuracy is hindered. Compared with a butadiene component having a heavy bond, the solubility in an oxidizing roughening solution is small, and stable plating adhesion is difficult to obtain.
In addition, the rubber component is excellent in terms of solubility in the roughening solution, but since it is in a linear high molecular weight state, problems with compatibility with other materials are likely to occur, and heat resistance is also disadvantageous.
[0006]
The objective of this invention is providing the multilayer wiring board using the photosensitive insulating resin excellent in the adhesive force with a plating conductor, surface smoothness, and heat resistance.
[0007]
[Means for Solving the Problems]
In the method for manufacturing a multilayer wiring board of the present invention, a via hole for connecting to the first circuit is formed in the insulating layer on the circuit surface of the insulating substrate on which the first circuit is formed, and the surface of the insulating layer is formed by copper plating. In the method of manufacturing a wiring board in which the second circuit formation and via hole interlayer connection are performed to form a multilayer, the insulating layer has a photosensitive resin containing crosslinked acrylonitrile butadiene rubber particles and / or a photosensitive property and a thermosetting property. It is characterized by using the resin used together.
[0008]
The crosslinked acrylonitrile butadiene rubber particles used in the present invention are fine high molecular weight crosslinked rubber particles having a primary average particle diameter of 50 to 100 nm {500 to 1000 angstroms} obtained by crosslinking acrylonitrile butadiene rubber in an emulsion state after emulsion polymerization. There, acrylonitrile-butadiene rubber Karupokishiru groups modified or unmodified are all can be used.
The blending amount thereof is 2 to 40% by weight in the total solid content of the photosensitive resin and / or the resin having both photosensitivity and thermosetting. Preferably, it is 5 to 25% by weight.
When the amount of crosslinked acrylonitrile butadiene rubber particles is 2% by weight or less, the adhesive strength with the plated copper is not sufficiently improved. Therefore, it is not preferable.
[0009]
The photosensitive resin as the base containing acrylonitrile butadiene rubber particles and / or the resin having both photosensitivity and thermosetting are not particularly limited, and may be a copolymer having a functional group capable of being cross-linked by light, or Any composition containing a monomer and / or a composition in which a heat-crosslinkable functional group and a thermal initiator are mixed in addition to light can be used.
[0010]
In addition, if the insulating layer composition of the present invention is mixed with an inorganic filler such as fine powder silica, aluminum hydroxide, silica, zirconium silicate, calcium carbonate, talc, barium sulfate, etc., roughening during chemical roughening Since it is easy to form unevenness, it is preferable from the viewpoint of improving the adhesive strength with the plated copper, and good results can be obtained also in terms of coating film reinforcement.
[0011]
The process for producing the multilayer wiring board of the present invention will be described in detail with reference to FIG. 1 using the insulating layer composition described above.
First, an insulating substrate on which a first circuit is formed is prepared (FIG. 1-a).
The insulating substrate is not particularly limited, and an insulating substrate used for an ordinary wiring board such as glass cloth-epoxy resin, paper-phenol resin, paper-epoxy resin, glass cloth / glass paper-epoxy resin, or the like can be used. As a method for forming the first circuit of the present invention, a copper-clad laminate in which a copper foil and the insulating substrate are bonded together is used, and a subtractive method in which unnecessary portions of the copper foil are removed by etching, or the necessity of the insulating substrate is used. A normal method for manufacturing a wiring board, such as an additive method for forming a circuit by electroless plating at an appropriate location, can be used.
[0012]
Next, the insulating layer is formed on the circuit surface on which the first circuit is formed (FIG. 1-b). As this forming method, a method in which a liquid resin is applied by a method such as roll coating, curtain coating, or dip coating, or a method in which the insulating resin is formed into a film and bonded together by a laminate can be used.
[0013]
Next, in order to form a via hole connected to the first circuit in the insulating layer, the insulating layer is exposed by a photomask (FIG. 1C) and the unexposed portion is etched with a developer. A via hole to be connected to the first circuit is formed (FIG. 1-d). For the exposure, the same technique as the resist forming method for a normal wiring board is used.
In addition, the developer that etches the unexposed portion with a developer is determined depending on what type of development the insulating resin composition is, but an alkali developer, a semi-aqueous developer, a solvent developer, etc. Can be used.
[0014]
Next, the insulating layer is treated with an oxidizing roughening solution, and then copper plating is deposited on the insulating layer to form a second circuit and make a via hole interlayer connection (FIG. 1-e).
In this case, it is also possible to use a method in which the insulating layer is cured with ultraviolet rays and ultraviolet rays and heat and then immersed in an oxidizing roughening solution.
As the oxidizing roughening liquid, a chromium / sulfuric acid roughening liquid, an alkaline permanganic acid roughening liquid, a sodium fluoride / chromium / sulfuric acid roughening liquid, a borofluoric acid roughening liquid, or the like can be used.
Furthermore, as a method for forming the second circuit, a catalyst for electroless plating is applied to the roughened insulating layer surface to deposit electroless plated copper on the entire surface, and if necessary, the circuit conductor is formed by electrolytic plating. A method of forming a necessary thickness by etching away unnecessary portions, a method of forming a plating resist by using an insulating layer containing a plating catalyst, and forming a circuit by electroless plating only at the necessary portions, And after roughening the insulating layer which does not contain a plating catalyst, and providing a plating catalyst, a method of forming a plating resist and forming a circuit by electroless plating only at a necessary portion can be used.
[0015]
When the present invention is multilayered, the above method (FIG. 1-b to FIG. 1-e) is repeated to form a multilayer (step: FIG. 1-f to FIG. 1-h). In this case, preferably, before forming the next circuit layer, the surface of the underlying circuit layer conductor is roughened to form irregularities, or the surface of the circuit layer conductor is oxidized as used in a conventional multilayer wiring board. Then, the unevenness formed by oxidation or the unevenness formed by oxidation can be reduced using an alkaline reducing agent such as sodium borohydride or dimethylamine borane to enhance the adhesion between the layers.
[0016]
[Action]
The present invention is a method of manufacturing a wiring board in which a specific insulating layer is used as an interlayer insulating layer and is multilayered by a build-up method, and has a high adhesive strength with plated copper, and is excellent in surface smoothness and heat resistance. A wiring board can be provided.
[0017]
【Example】
Example 1
(1) Using MCL-E-67 (trade name, manufactured by Hitachi Chemical Co., Ltd.) which is a copper-clad glass cloth epoxy resin laminate with 18 μm double-sided roughened foil on both sides, Etching is removed to form a first circuit (shown in FIG. 1-a).
(2) On one surface of this surface, an insulating resin having the following composition was applied by roll coating and dried at 80 ° C. for 10 minutes to form an insulating layer having a thickness of 60 μm (shown in FIG. 1-b).
(composition)
・ Phthalic acid modified novolak epoxy acrylate,
R-5259 (Nippon Kayaku Co., Ltd., trade name) ... 70 parts by weight Crosslinked carboxylic acid-modified acrylonitrile butadiene rubber particles,
XER-91 (trade name, manufactured by Nippon Synthetic Rubber Co., Ltd.) ... 25 parts by weight / photoinitiator,
Irgacure 651 (Ciba Geigy Corp., trade name) 5 parts by weight Filler, Aluminum Hydroxide Hydrite H-42M (Showa Denko, trade name) 10 parts by weight (3) Via An exposure amount of 300 mJ / cm 2 is passed through a photomask in which a shielding part is formed in a part to be a hole UV rays (shown in FIG. 1-c) were further removed, and the unexposed portions were selectively removed with a 1.1% sodium carbonate aqueous solution at 30 ° C. for 2 minutes to form via holes.
(4) Post-exposure is performed by irradiating the insulating layer with ultraviolet rays 2 J / cm 2 .
(5) In order to chemically roughen the insulating layer, an aqueous solution of KMnO 4 : 60 g / l, NaOH: 40 g / l is prepared as a roughening solution, heated to 50 ° C. and immersed for 5 minutes.
After the KMnO 4 immersion treatment, it was neutralized by immersion in an aqueous solution of SnCl 2 : 30 g / l and HCl: 300 ml / l at room temperature for 5 minutes to form a roughened uneven shape (shown in FIG. 1-d).
(6) In order to form the second circuit on the surface of the first insulating layer, first, HS-202B (trade name, manufactured by Hitachi Chemical Co., Ltd.), which is an electroless plating catalyst containing PdCl 2 , Immersing for 10 minutes, washing with water, immersing in an L-59 plating solution (trade name, manufactured by Hitachi Chemical Co., Ltd.) that is electroless copper plating at 70 ° C. for 30 minutes, and further performing copper sulfate electrolytic plating, A conductor layer having a thickness of 20 μm is formed on the surface of the insulating layer.
Next, an etching resist is formed to remove unnecessary portions of the plated conductor, and etching is performed. Thereafter, the etching resist is removed, and a second circuit including a via hole connected to the first circuit is formed. (Shown in FIG. 1-e).
(7) In order to further increase the number of layers, the surface of the second circuit conductor is immersed in an aqueous solution of sodium chlorite: 50 g / l, NaOH: 20 g / l, sodium phosphate 10 g / l at 85 ° C. for 20 minutes. Then, it is washed with water and dried at 80 ° C. for 20 minutes to form copper oxide irregularities on the surface of the second circuit conductor.
(8) The steps (2) to (7) were repeated to produce a multilayer wiring board (shown in FIGS. 1-f to 1-h).
[0018]
Example 2
The insulating resin composition shown in Example 1 was changed to the following composition. The developer is developed using a semi-aqueous developer containing diethylene glycol monobutyl ether: 200 ml / l and borax: 10 g / l at 40 ° C. for 30 minutes, and irradiated with ultraviolet rays 2 J / cm 2 before roughening. Then, heat curing was performed at 150 ° C. for 30 minutes. Others were performed in the same manner as in Example 1.
(composition)
・ Bisphenol A type epoxy,
Epicoat 834 (trade name, manufactured by Yuka Shell Co., Ltd.) ... 15 parts by weight / phenol novolac epoxy acrylate,
SP-4010 (manufactured by Showa Polymer Co., Ltd., trade name) 50 parts by weight, crosslinked carboxylic acid-modified acrylonitrile butadiene rubber particles,
XER-91 (trade name, manufactured by Nippon Synthetic Rubber Co., Ltd.) ... 30 parts by weight / photoinitiator,
Irgacure 651 (trade name, manufactured by Ciba Geigy) ··· 5 parts by weight · thermosetting agent,
Dicyandiamide ... 2 parts by weight, filler, aluminum hydroxide Heidilite H-42M (made by Showa Denko KK, trade name) ... 10 Weight part [0019]
Example 3
The insulating resin composition shown in Example 1 was changed to the following composition. Further, the developer is a solvent-based developer of ethyl ethoxypropionate: 1000 ml / l, developed at 30 ° C. for 5 minutes, irradiated with ultraviolet rays 2 J / cm 2 before roughening, and 150 ° C.-30. Heat curing for minutes was performed. Others were performed in the same manner as in Example 1.
(composition)
・ Bisphenol A type epoxy,
Epicoat 834 (trade name, manufactured by Yuka Shell Co., Ltd.) ... 20 parts by weight / bisphenol A type epoxy acrylate,
VR-60 (manufactured by Showa Polymer Co., Ltd., trade name) 60 parts by weight cross-linked carboxylic acid-modified acrylonitrile butadiene rubber particles,
XER-91 (trade name, manufactured by Nippon Synthetic Rubber Co., Ltd.) 15 parts by weight / photoinitiator,
Irgacure 651 (trade name, manufactured by Ciba Geigy) ··· 5 parts by weight · thermosetting agent,
Dicyandiamide ... 2 parts by weight, filler, aluminum hydroxide Heidilite H-42M (made by Showa Denko KK, trade name) ... 10 Weight part [0020]
Comparative Examples 1-3
In Examples 1-3, it was set as the composition system which does not use bridge | crosslinking NBR. Others were performed in the same manner as in Examples 1 to 3.
Table 1 shows the characteristics of the multilayer wiring board produced as described above.
[0021]
[Table 1]
【The invention's effect】
As described above, according to the present invention, it was possible to provide a method for producing a build-up multilayer wiring board having high adhesive strength with plated copper and excellent heat resistance.
[Brief description of the drawings]
FIGS. 1A to 1H are cross-sectional views in each step for explaining an embodiment of the present invention.
[Explanation of symbols]
1. 1. Insulating substrate First circuit 3. First insulating
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27651194A JP3697726B2 (en) | 1994-11-10 | 1994-11-10 | Manufacturing method of multilayer wiring board |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP27651194A JP3697726B2 (en) | 1994-11-10 | 1994-11-10 | Manufacturing method of multilayer wiring board |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH08139457A JPH08139457A (en) | 1996-05-31 |
| JP3697726B2 true JP3697726B2 (en) | 2005-09-21 |
Family
ID=17570493
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP27651194A Expired - Fee Related JP3697726B2 (en) | 1994-11-10 | 1994-11-10 | Manufacturing method of multilayer wiring board |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3697726B2 (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP3247091B2 (en) * | 1997-11-28 | 2002-01-15 | 日立化成工業株式会社 | Photocurable resin composition and photosensitive element using the same |
| US6583198B2 (en) | 1997-11-28 | 2003-06-24 | Hitachi Chemical Company, Ltd. | Photo curable resin composition and photosensitive element |
| JP3943883B2 (en) | 2001-10-02 | 2007-07-11 | 新日鐵化学株式会社 | Insulating resin composition and laminate using the same |
| JP4576794B2 (en) * | 2003-02-18 | 2010-11-10 | 日立化成工業株式会社 | Insulating resin composition and use thereof |
-
1994
- 1994-11-10 JP JP27651194A patent/JP3697726B2/en not_active Expired - Fee Related
Also Published As
| Publication number | Publication date |
|---|---|
| JPH08139457A (en) | 1996-05-31 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| JP3400049B2 (en) | Adhesive for printed wiring board and method for manufacturing printed wiring board using this adhesive | |
| JP2776886B2 (en) | Multilayer printed wiring board and method of manufacturing the same | |
| JP3697726B2 (en) | Manufacturing method of multilayer wiring board | |
| JP3069356B2 (en) | Multilayer printed wiring board and method of manufacturing the same | |
| JP3546457B2 (en) | Resin composition and method for producing multilayer wiring board using the same | |
| JP3637613B2 (en) | Manufacturing method of multilayer wiring board | |
| JPH0818239A (en) | Method for manufacturing multi-layer printing wiring board | |
| WO2000062588A1 (en) | Multilayer printed wiring board | |
| JP4556260B2 (en) | Additive insulation film for printed wiring boards | |
| JP5330156B2 (en) | Circuit board manufacturing method and circuit board obtained by the manufacturing method | |
| JP4199151B2 (en) | Adhesive and adhesive layer for printed wiring board | |
| JPH09186462A (en) | Manufacture of multilayered flexible printed wiring board | |
| JP3859030B2 (en) | Manufacturing method of multilayer wiring board | |
| JP5055659B2 (en) | Insulating resin composition, use thereof and method for producing wiring board | |
| JP4126735B2 (en) | Method for producing multilayer wiring board using insulating resin containing specific antioxidant | |
| JP3593351B2 (en) | Method for manufacturing multilayer wiring board | |
| JPH06216535A (en) | Production of wiring board | |
| JP4051587B2 (en) | Method for producing multilayer wiring board using resin composition curable by heat or light | |
| JP2000306429A (en) | Insulation composition and multilayer wiring plate | |
| JPH11103173A (en) | Manufacture of multilayered wiring board using insulating resin loaded with specified reducing agent | |
| JP2001151837A (en) | Insulating resin composition and method of manufacturing multilayer printed circuit board by using the same | |
| JP2951923B2 (en) | Multilayer printed wiring board | |
| JPH11186720A (en) | Manufacturing multilayered wiring board | |
| JPH11284346A (en) | Manufacture of multi-layer printed wiring board | |
| JP3329917B2 (en) | Adhesive for printed wiring board and method for manufacturing printed wiring board using this adhesive |
Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20040623 |
|
| A131 | Notification of reasons for refusal |
Effective date: 20040727 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
| A131 | Notification of reasons for refusal |
Effective date: 20041019 Free format text: JAPANESE INTERMEDIATE CODE: A131 |
|
| A521 | Written amendment |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20041220 |
|
| TRDD | Decision of grant or rejection written | ||
| A01 | Written decision to grant a patent or to grant a registration (utility model) |
Effective date: 20050614 Free format text: JAPANESE INTERMEDIATE CODE: A01 |
|
| A61 | First payment of annual fees (during grant procedure) |
Effective date: 20050627 Free format text: JAPANESE INTERMEDIATE CODE: A61 |
|
| FPAY | Renewal fee payment (prs date is renewal date of database) |
Free format text: PAYMENT UNTIL: 20090715 Year of fee payment: 4 |
|
| LAPS | Cancellation because of no payment of annual fees |