JPS60196994A - Connecting system for circuit - Google Patents

Connecting system for circuit

Info

Publication number
JPS60196994A
JPS60196994A JP5316284A JP5316284A JPS60196994A JP S60196994 A JPS60196994 A JP S60196994A JP 5316284 A JP5316284 A JP 5316284A JP 5316284 A JP5316284 A JP 5316284A JP S60196994 A JPS60196994 A JP S60196994A
Authority
JP
Japan
Prior art keywords
circuit
terminals
transistor
component leads
connection
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5316284A
Other languages
Japanese (ja)
Inventor
大谷 新一
工藤 栄彦
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Nippon Electric Co Ltd filed Critical Nippon Electric Co Ltd
Priority to JP5316284A priority Critical patent/JPS60196994A/en
Publication of JPS60196994A publication Critical patent/JPS60196994A/en
Pending legal-status Critical Current

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  • Structures For Mounting Electric Components On Printed Circuit Boards (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【発明の詳細な説明】 〔発明の属する分野の説明〕 本発明はトランジスタの電極リード等をマイクロ波集積
回路(以下、MICという)の基板等に接続する場合に
、トランジスタの電極リードの根元及び電極リードと上
記基板との接続部分に加わる熱歪みによる機械的ストレ
スを良好に吸収し、トランジスタ回路の安定性及び長寿
命を達成させる接続方式に関するものである。
Detailed Description of the Invention [Description of the Field to which the Invention Pertains] The present invention provides a method for connecting the electrode lead of a transistor to a substrate of a microwave integrated circuit (hereinafter referred to as MIC). The present invention relates to a connection method that satisfactorily absorbs mechanical stress due to thermal strain applied to the connection portion between an electrode lead and the substrate, thereby achieving stability and long life of a transistor circuit.

〔従来の技術の説明〕[Description of conventional technology]

従来のこの種の接続方式は高周波回路(LOOM■Iz
以上の増幅器、逓倍器等)に多く採用されている。即ち
、通常はトランジスタと入出力回路との整合性を良くす
るために、トランジスタの電極リードを極力短かくする
ことが必要であシ、第1図あるいは第2図に示すような
接続方式が採られている。
This type of conventional connection method is used for high frequency circuits (LOOM Iz
(amplifiers, multipliers, etc.). That is, in order to improve the compatibility between the transistor and the input/output circuit, it is usually necessary to make the electrode leads of the transistor as short as possible, and the connection method shown in Figure 1 or Figure 2 is usually adopted. It is being

第1図は従来から用いられている最も単純な接続方式の
一例である。同図(cL)はトランジスタ6とMIC基
板2及び3の接続部の上面図、同図(II、)はその側
面図である。この接続方式の場合、MIC基板2及び3
とトランジスタ6は筐体1に機械的に固定され、トラン
ジスタの電極リード7及び8はMIC基板2及び3に形
成された膜回路パターン4及び5と直接的に半田付は等
の手段で接続されている。この方式では電極リード7及
び8の端部が機械的に固定されてしまうため、次のよう
な欠点が有った。
FIG. 1 is an example of the simplest connection method conventionally used. The figure (cL) is a top view of the connecting portion between the transistor 6 and the MIC substrates 2 and 3, and the figure (II) is a side view thereof. In this connection method, MIC boards 2 and 3
and the transistor 6 are mechanically fixed to the housing 1, and the electrode leads 7 and 8 of the transistors are directly connected to the film circuit patterns 4 and 5 formed on the MIC substrates 2 and 3 by means such as soldering. ing. In this method, the ends of the electrode leads 7 and 8 are mechanically fixed, resulting in the following drawbacks.

即ち、トランジスタ回路全体に温度ストレスが加わると
、筐体1と電極リード7及び8との平均熱膨張係数が異
なるととによる機械的歪みが電極リード7及び8の固定
部分に加わる。この温度ストレスが周期的に複数回だけ
発生すると、この機械的歪みが蓄積疲労となり、終局的
にトランジスタ回路の故障(接続部のクラック等)発生
の原因になる。
That is, when temperature stress is applied to the entire transistor circuit, mechanical strain is applied to the fixed portions of the electrode leads 7 and 8 due to the difference in average coefficient of thermal expansion between the housing 1 and the electrode leads 7 and 8. If this temperature stress occurs cyclically multiple times, this mechanical strain results in cumulative fatigue, which ultimately causes failure of the transistor circuit (such as cracks in the connection portion).

第2図(α) 、 (b)は上記欠点を改善するために
電極リード7及び8にU形のストレスリリーフ7α、8
a。
Figures 2 (α) and (b) show U-shaped stress reliefs 7α, 8 on the electrode leads 7 and 8 in order to improve the above drawbacks.
a.

を設けた接続方式であるが、このストレスリリーフ70
L、8cLがあるために電極リードが長くなり、トラン
ジスタの入出力整合を難かしくする場合が多く、特にギ
ガヘルツ以上の周波数を扱う回路の場合、整合が取れな
くなる場合も有る。
However, this stress relief 70
L and 8 cL make the electrode lead long, which often makes it difficult to match the input and output of the transistor, and in particular, in the case of a circuit that handles frequencies of gigahertz or higher, matching may not be achieved.

〔発明の目的〕 本発明は前記問題点を解消するもので、トランジスタの
電極リード等の端部と膜回路パターン等とを間接的に結
合することにより、電極リード等に生ずる熱応力を吸収
できるようにした回路の接続方式を提供することにある
[Object of the Invention] The present invention solves the above-mentioned problems, and by indirectly connecting the ends of the electrode leads, etc. of a transistor to the film circuit pattern, etc., it is possible to absorb thermal stress occurring in the electrode leads, etc. The object of the present invention is to provide a circuit connection method that achieves this.

〔発明の構成〕[Structure of the invention]

本発明は機械的に固定設置された端子、部品リード等の
相互間を電気的に接続する方式において、前記端子、部
1品リード等に生ずる熱応力を受けて変形−する程度の
機械的剛性(ヤング率)をもつ材料からなり、かつ少く
とも表面の比抵抗が十分低い導電性接続片を電気的に接
続する端子、部品リード等の間に介装し、該端子、部品
リード等の端部を該接続片に結合したことを特徴とする
回路の接続方式である。
The present invention provides a system for electrically connecting terminals, component leads, etc. that are mechanically fixedly installed, with mechanical rigidity to the extent that the terminals, component leads, etc. deform due to thermal stress generated in the terminals, component leads, etc. (Young's modulus) and at least a sufficiently low surface resistivity is interposed between electrically connected terminals, component leads, etc., and the ends of the terminals, component leads, etc. This is a circuit connection method characterized in that a section is connected to the connection piece.

〔実施例〕〔Example〕

以下に、本発明の=実施例を図により説明する。 Embodiments of the present invention will be described below with reference to the drawings.

第3図(α) 、 (b)は本考案の実施例であり、何
カ1〜8は第1図(α) 、 (b)及び第2図(α)
 、 (b)で説明した構成要素と同じである。又9及
び10は熱的ストレスを吸収させる接続片である。接続
片9及びIOは膜回路パターン4及び5の端部と電極リ
ード7及び8の端部とに半田付けされる。この接続片は
アルミニウム等の金FfS 4’A料やセラミック等の
磁器材料の機械的岡り性(ヤング率)に比べ小さい値の
材料(例えばエポキシ系樹脂)を所望の寸法(例えば4
 x 2 X 1.5 ” ynm程度)に加工した後
、−表面に金等の金属を蒸着させてあり、電極リード7
.8に生ずる熱応力を受けて変形し、一方少なくともそ
の表面の比抵抗を十分低くして導電性をもたせである。
Figures 3 (α) and (b) are examples of the present invention, and numbers 1 to 8 are Figure 1 (α), (b) and Figure 2 (α).
, The components are the same as those described in (b). Further, 9 and 10 are connecting pieces for absorbing thermal stress. The connecting pieces 9 and IO are soldered to the ends of the membrane circuit patterns 4 and 5 and the ends of the electrode leads 7 and 8. This connection piece connects a material (e.g. epoxy resin) with a smaller value than the mechanical stiffness (Young's modulus) of a gold FfS 4'A material such as aluminum or a porcelain material such as ceramic to a desired size (e.g. 4'
x 2
.. 8 is deformed by the thermal stress generated on the surface, and at least the specific resistance of its surface is made sufficiently low to provide electrical conductivity.

以上の構造を有する接続方式では、前述した温度ストレ
スによる電極リード部分に発生する熱的ストレスは接続
片9及び10で完全に吸収することができると同時に、
第2図(α) 、 (b)に示す従来の実施例に見られ
たようなトランジスタ回路としての整合性の悪さといっ
た欠点が解決される。又、接続片の取付けはMIC基板
上の他の部品と同時に行なうことができるため、接続片
の取付は位置の精度が上がるので、回路調整時の歩留り
が向上するという利点が有る・第2図(α)、 (b)
の方式ではU形のリード加工を精度良く一行なうには時
間と手間を要する。
In the connection method having the above structure, the thermal stress generated in the electrode lead portion due to the above-mentioned temperature stress can be completely absorbed by the connection pieces 9 and 10, and at the same time,
This solves the drawback of poor matching as a transistor circuit, as seen in the conventional embodiments shown in FIGS. 2(α) and 2(b). In addition, since the connection piece can be attached at the same time as other parts on the MIC board, the positioning accuracy of the connection piece is increased, which has the advantage of improving the yield during circuit adjustment. (Figure 2) (α), (b)
With this method, it takes time and effort to process a U-shaped lead with high precision.

第4図(G) 、 (b)は他の実施例″cあり、コネ
クタ11の中心導体(端子)12と膜回路パターン4と
の接続に本発明を使用したものである。この実施例にお
いても、コネクタ11の中心導体12に生ずる熱応力は
接続片9の変形により吸収することができる。
4(G) and (b) show another embodiment "c" in which the present invention is used to connect the center conductor (terminal) 12 of the connector 11 and the membrane circuit pattern 4. In this embodiment, However, the thermal stress generated in the center conductor 12 of the connector 11 can be absorbed by deforming the connecting piece 9.

〔発明の詳細な説明〕[Detailed description of the invention]

以上説明したとおり、本発明によればトランジスタの電
極リードあるいはコネクタの中心導体等にストレスリリ
ーフを設けることなく、簡単な構造によシ熱的ストレス
による接続部のクラック等を防止できる効果を有するも
のである。
As explained above, according to the present invention, it is possible to prevent cracks in the connection part due to thermal stress with a simple structure without providing stress relief to the electrode leads of the transistor or the center conductor of the connector, etc. It is.

なお、これらの実施例は代表的な応用例を示すものであ
り、このものに限定されるものではない。
Note that these examples show typical application examples and are not limited to these examples.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、第2図(α)は従来の接続方式の上面図
、第1図(b)、第2図(b)は側面図、第3図(a、
)、第4図(α)は本発明の実施例を示す上面図、第3
図(6)、第4図(b)は側面図である。 なお図において、1は筐体、2及び3は磁器基板、4及
び5は膜回路パターン、6はトランジスタ、7及び8は
トランジスタの電極リード、9及び10は接続片、11
はコネクタ、12はコネクタの中。 心導体である。 特許出願人 日本電気株夫会社 第1図 <a) 第2図 (α) 第3図 (α9
Figures 1 (a) and 2 (α) are top views of conventional connection systems, Figures 1 (b) and 2 (b) are side views, and Figures 3 (a,
), FIG. 4(α) is a top view showing an embodiment of the present invention, and FIG.
Figures (6) and 4(b) are side views. In the figure, 1 is a housing, 2 and 3 are ceramic substrates, 4 and 5 are film circuit patterns, 6 is a transistor, 7 and 8 are transistor electrode leads, 9 and 10 are connection pieces, and 11
is the connector, and 12 is inside the connector. It is a heart conductor. Patent Applicant NEC Corporation Figure 1 <a) Figure 2 (α) Figure 3 (α9

Claims (1)

【特許請求の範囲】[Claims] (1)機械的に固定して設置された端子、部品リード等
の相互間を電気的に接続する方式において、前記端子、
部品リード等に生ずる熱一応力を受けて変形する程度の
機械的剛性(ヤング率)をもつ材料からなシ、かつ少く
とも表面の比抵抗が十分に低い導電性接続片を電気的に
接続する端子、部品リード等の間に介装し、該端子、部
品リード等の端部を該接続片に結合したことを特徴とす
る回路の接続方式。
(1) In a method for electrically connecting mechanically fixed terminals, component leads, etc., the terminals,
Electrically connect a conductive connection piece that is made of a material that has enough mechanical rigidity (Young's modulus) to deform in response to thermal stress generated in component leads, etc., and that has at least a sufficiently low surface resistivity. A circuit connection method characterized in that the circuit is interposed between terminals, component leads, etc., and the ends of the terminals, component leads, etc. are connected to the connection piece.
JP5316284A 1984-03-19 1984-03-19 Connecting system for circuit Pending JPS60196994A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5316284A JPS60196994A (en) 1984-03-19 1984-03-19 Connecting system for circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5316284A JPS60196994A (en) 1984-03-19 1984-03-19 Connecting system for circuit

Publications (1)

Publication Number Publication Date
JPS60196994A true JPS60196994A (en) 1985-10-05

Family

ID=12935154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5316284A Pending JPS60196994A (en) 1984-03-19 1984-03-19 Connecting system for circuit

Country Status (1)

Country Link
JP (1) JPS60196994A (en)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5922386A (en) * 1982-07-07 1984-02-04 アルカテル・エヌ・ブイ Electronic part structure
JPS5952687B2 (en) * 1979-08-24 1984-12-21 住友金属工業株式会社 Manufacturing method of tempered high-strength steel plate with excellent low-temperature toughness
JPS6074598A (en) * 1983-09-30 1985-04-26 富士通株式会社 Mounting structure of leadless chip carrier

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5952687B2 (en) * 1979-08-24 1984-12-21 住友金属工業株式会社 Manufacturing method of tempered high-strength steel plate with excellent low-temperature toughness
JPS5922386A (en) * 1982-07-07 1984-02-04 アルカテル・エヌ・ブイ Electronic part structure
JPS6074598A (en) * 1983-09-30 1985-04-26 富士通株式会社 Mounting structure of leadless chip carrier

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